gic.c revision 1.3.2.2
1 1.3.2.2 yamt /* $NetBSD: gic.c,v 1.3.2.2 2012/10/30 17:19:00 yamt Exp $ */ 2 1.3.2.2 yamt /*- 3 1.3.2.2 yamt * Copyright (c) 2012 The NetBSD Foundation, Inc. 4 1.3.2.2 yamt * All rights reserved. 5 1.3.2.2 yamt * 6 1.3.2.2 yamt * This code is derived from software contributed to The NetBSD Foundation 7 1.3.2.2 yamt * by Matt Thomas of 3am Software Foundry. 8 1.3.2.2 yamt * 9 1.3.2.2 yamt * Redistribution and use in source and binary forms, with or without 10 1.3.2.2 yamt * modification, are permitted provided that the following conditions 11 1.3.2.2 yamt * are met: 12 1.3.2.2 yamt * 1. Redistributions of source code must retain the above copyright 13 1.3.2.2 yamt * notice, this list of conditions and the following disclaimer. 14 1.3.2.2 yamt * 2. Redistributions in binary form must reproduce the above copyright 15 1.3.2.2 yamt * notice, this list of conditions and the following disclaimer in the 16 1.3.2.2 yamt * documentation and/or other materials provided with the distribution. 17 1.3.2.2 yamt * 18 1.3.2.2 yamt * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 19 1.3.2.2 yamt * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 20 1.3.2.2 yamt * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 21 1.3.2.2 yamt * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 22 1.3.2.2 yamt * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 1.3.2.2 yamt * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 1.3.2.2 yamt * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 1.3.2.2 yamt * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 1.3.2.2 yamt * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 1.3.2.2 yamt * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 1.3.2.2 yamt * POSSIBILITY OF SUCH DAMAGE. 29 1.3.2.2 yamt */ 30 1.3.2.2 yamt 31 1.3.2.2 yamt #define _INTR_PRIVATE 32 1.3.2.2 yamt 33 1.3.2.2 yamt #include <sys/cdefs.h> 34 1.3.2.2 yamt __KERNEL_RCSID(0, "$NetBSD: gic.c,v 1.3.2.2 2012/10/30 17:19:00 yamt Exp $"); 35 1.3.2.2 yamt 36 1.3.2.2 yamt #include <sys/param.h> 37 1.3.2.2 yamt #include <sys/bus.h> 38 1.3.2.2 yamt #include <sys/device.h> 39 1.3.2.2 yamt #include <sys/evcnt.h> 40 1.3.2.2 yamt #include <sys/intr.h> 41 1.3.2.2 yamt #include <sys/proc.h> 42 1.3.2.2 yamt #include <sys/xcall.h> /* for xc_ipi_handler */ 43 1.3.2.2 yamt 44 1.3.2.2 yamt #include <arm/armreg.h> 45 1.3.2.2 yamt #include <arm/cpufunc.h> 46 1.3.2.2 yamt #include <arm/atomic.h> 47 1.3.2.2 yamt 48 1.3.2.2 yamt #include <arm/cortex/gic_reg.h> 49 1.3.2.2 yamt #include <arm/cortex/mpcore_var.h> 50 1.3.2.2 yamt 51 1.3.2.2 yamt #define ARMGIC_SGI_IPIBASE (16 - NIPI) 52 1.3.2.2 yamt 53 1.3.2.2 yamt static int armgic_match(device_t, cfdata_t, void *); 54 1.3.2.2 yamt static void armgic_attach(device_t, device_t, void *); 55 1.3.2.2 yamt 56 1.3.2.2 yamt static void armgic_set_priority(struct pic_softc *, int); 57 1.3.2.2 yamt static void armgic_unblock_irqs(struct pic_softc *, size_t, uint32_t); 58 1.3.2.2 yamt static void armgic_block_irqs(struct pic_softc *, size_t, uint32_t); 59 1.3.2.2 yamt static void armgic_establish_irq(struct pic_softc *, struct intrsource *); 60 1.3.2.2 yamt #if 0 61 1.3.2.2 yamt static void armgic_source_name(struct pic_softc *, int, char *, size_t); 62 1.3.2.2 yamt #endif 63 1.3.2.2 yamt 64 1.3.2.2 yamt #ifdef MULTIPROCESSOR 65 1.3.2.2 yamt static void armgic_cpu_init(struct pic_softc *, struct cpu_info *); 66 1.3.2.2 yamt static void armgic_ipi_send(struct pic_softc *, const kcpuset_t *, u_long); 67 1.3.2.2 yamt #endif 68 1.3.2.2 yamt 69 1.3.2.2 yamt static const struct pic_ops armgic_picops = { 70 1.3.2.2 yamt .pic_unblock_irqs = armgic_unblock_irqs, 71 1.3.2.2 yamt .pic_block_irqs = armgic_block_irqs, 72 1.3.2.2 yamt .pic_establish_irq = armgic_establish_irq, 73 1.3.2.2 yamt #if 0 74 1.3.2.2 yamt .pic_source_name = armgic_source_name, 75 1.3.2.2 yamt #endif 76 1.3.2.2 yamt .pic_set_priority = armgic_set_priority, 77 1.3.2.2 yamt #ifdef MULTIPROCESSOR 78 1.3.2.2 yamt .pic_cpu_init = armgic_cpu_init, 79 1.3.2.2 yamt .pic_ipi_send = armgic_ipi_send, 80 1.3.2.2 yamt #endif 81 1.3.2.2 yamt }; 82 1.3.2.2 yamt 83 1.3.2.2 yamt #define PICTOSOFTC(pic) ((struct armgic_softc *)(pic)) 84 1.3.2.2 yamt 85 1.3.2.2 yamt static struct armgic_softc { 86 1.3.2.2 yamt struct pic_softc sc_pic; 87 1.3.2.2 yamt device_t sc_dev; 88 1.3.2.2 yamt bus_space_tag_t sc_memt; 89 1.3.2.2 yamt bus_space_handle_t sc_memh; 90 1.3.2.2 yamt size_t sc_gic_lines; 91 1.3.2.2 yamt uint32_t sc_gic_type; 92 1.3.2.2 yamt uint32_t sc_gic_valid_lines[1024/32]; 93 1.3.2.2 yamt uint32_t sc_enabled_local; 94 1.3.2.2 yamt } armgic_softc = { 95 1.3.2.2 yamt .sc_pic = { 96 1.3.2.2 yamt .pic_ops = &armgic_picops, 97 1.3.2.2 yamt .pic_name = "armgic", 98 1.3.2.2 yamt }, 99 1.3.2.2 yamt }; 100 1.3.2.2 yamt 101 1.3.2.2 yamt static struct intrsource armgic_dummy_source; 102 1.3.2.2 yamt 103 1.3.2.2 yamt __CTASSERT(NIPL == 8); 104 1.3.2.2 yamt 105 1.3.2.2 yamt /* 106 1.3.2.2 yamt * GIC register are always in little-endian. 107 1.3.2.2 yamt */ 108 1.3.2.2 yamt static inline uint32_t 109 1.3.2.2 yamt gicc_read(struct armgic_softc *sc, bus_size_t o) 110 1.3.2.2 yamt { 111 1.3.2.2 yamt uint32_t v = bus_space_read_4(sc->sc_memt, sc->sc_memh, GICC_BASE + o); 112 1.3.2.2 yamt return le32toh(v); 113 1.3.2.2 yamt } 114 1.3.2.2 yamt 115 1.3.2.2 yamt static inline void 116 1.3.2.2 yamt gicc_write(struct armgic_softc *sc, bus_size_t o, uint32_t v) 117 1.3.2.2 yamt { 118 1.3.2.2 yamt v = htole32(v); 119 1.3.2.2 yamt bus_space_write_4(sc->sc_memt, sc->sc_memh, GICC_BASE + o, v); 120 1.3.2.2 yamt } 121 1.3.2.2 yamt 122 1.3.2.2 yamt static inline uint32_t 123 1.3.2.2 yamt gicd_read(struct armgic_softc *sc, bus_size_t o) 124 1.3.2.2 yamt { 125 1.3.2.2 yamt uint32_t v = bus_space_read_4(sc->sc_memt, sc->sc_memh, GICD_BASE + o); 126 1.3.2.2 yamt return le32toh(v); 127 1.3.2.2 yamt } 128 1.3.2.2 yamt 129 1.3.2.2 yamt static inline void 130 1.3.2.2 yamt gicd_write(struct armgic_softc *sc, bus_size_t o, uint32_t v) 131 1.3.2.2 yamt { 132 1.3.2.2 yamt v = htole32(v); 133 1.3.2.2 yamt bus_space_write_4(sc->sc_memt, sc->sc_memh, GICD_BASE + o, v); 134 1.3.2.2 yamt } 135 1.3.2.2 yamt 136 1.3.2.2 yamt /* 137 1.3.2.2 yamt * In the GIC prioritization scheme, lower numbers have higher priority. 138 1.3.2.2 yamt */ 139 1.3.2.2 yamt static inline uint32_t 140 1.3.2.2 yamt armgic_ipl_to_priority(int ipl) 141 1.3.2.2 yamt { 142 1.3.2.2 yamt return (IPL_HIGH - ipl) * GICC_PMR_PRIORITIES / NIPL; 143 1.3.2.2 yamt } 144 1.3.2.2 yamt 145 1.3.2.2 yamt static inline int 146 1.3.2.2 yamt armgic_priority_to_ipl(uint32_t priority) 147 1.3.2.2 yamt { 148 1.3.2.2 yamt return IPL_HIGH - priority * NIPL / GICC_PMR_PRIORITIES; 149 1.3.2.2 yamt } 150 1.3.2.2 yamt 151 1.3.2.2 yamt static void 152 1.3.2.2 yamt armgic_unblock_irqs(struct pic_softc *pic, size_t irq_base, uint32_t irq_mask) 153 1.3.2.2 yamt { 154 1.3.2.2 yamt struct armgic_softc * const sc = PICTOSOFTC(pic); 155 1.3.2.2 yamt const size_t group = irq_base / 32; 156 1.3.2.2 yamt 157 1.3.2.2 yamt if (group == 0) 158 1.3.2.2 yamt sc->sc_enabled_local |= irq_mask; 159 1.3.2.2 yamt 160 1.3.2.2 yamt gicd_write(sc, GICD_ISENABLERn(group), irq_mask); 161 1.3.2.2 yamt } 162 1.3.2.2 yamt 163 1.3.2.2 yamt static void 164 1.3.2.2 yamt armgic_block_irqs(struct pic_softc *pic, size_t irq_base, uint32_t irq_mask) 165 1.3.2.2 yamt { 166 1.3.2.2 yamt struct armgic_softc * const sc = PICTOSOFTC(pic); 167 1.3.2.2 yamt const size_t group = irq_base / 32; 168 1.3.2.2 yamt 169 1.3.2.2 yamt if (group == 0) 170 1.3.2.2 yamt sc->sc_enabled_local &= ~irq_mask; 171 1.3.2.2 yamt 172 1.3.2.2 yamt gicd_write(sc, GICD_ICENABLERn(group), irq_mask); 173 1.3.2.2 yamt } 174 1.3.2.2 yamt 175 1.3.2.2 yamt static uint32_t armgic_last_priority; 176 1.3.2.2 yamt 177 1.3.2.2 yamt static void 178 1.3.2.2 yamt armgic_set_priority(struct pic_softc *pic, int ipl) 179 1.3.2.2 yamt { 180 1.3.2.2 yamt struct armgic_softc * const sc = PICTOSOFTC(pic); 181 1.3.2.2 yamt 182 1.3.2.2 yamt const uint32_t priority = armgic_ipl_to_priority(ipl); 183 1.3.2.2 yamt gicc_write(sc, GICC_PMR, priority); 184 1.3.2.2 yamt armgic_last_priority = priority; 185 1.3.2.2 yamt } 186 1.3.2.2 yamt 187 1.3.2.2 yamt #ifdef __HAVE_PIC_FAST_SOFTINTS 188 1.3.2.2 yamt void 189 1.3.2.2 yamt softint_init_md(lwp_t *l, u_int level, uintptr_t *machdep_p) 190 1.3.2.2 yamt { 191 1.3.2.2 yamt lwp_t **lp = &l->l_cpu->ci_softlwps[level]; 192 1.3.2.2 yamt KASSERT(*lp == NULL || *lp == l); 193 1.3.2.2 yamt *lp = l; 194 1.3.2.2 yamt /* 195 1.3.2.2 yamt * Really easy. Just tell it to trigger the local CPU. 196 1.3.2.2 yamt */ 197 1.3.2.2 yamt *machdep_p = GICD_SGIR_TargetListFilter_Me 198 1.3.2.2 yamt | __SHIFTIN(level, GICD_SGIR_SGIINTID); 199 1.3.2.2 yamt } 200 1.3.2.2 yamt 201 1.3.2.2 yamt void 202 1.3.2.2 yamt softint_trigger(uintptr_t machdep) 203 1.3.2.2 yamt { 204 1.3.2.2 yamt 205 1.3.2.2 yamt gicd_write(&armgic_softc, GICD_SGIR, machdep); 206 1.3.2.2 yamt } 207 1.3.2.2 yamt #endif 208 1.3.2.2 yamt 209 1.3.2.2 yamt void 210 1.3.2.2 yamt armgic_irq_handler(void *tf) 211 1.3.2.2 yamt { 212 1.3.2.2 yamt struct cpu_info * const ci = curcpu(); 213 1.3.2.2 yamt struct armgic_softc * const sc = &armgic_softc; 214 1.3.2.2 yamt const int old_ipl = ci->ci_cpl; 215 1.3.2.2 yamt #ifdef DIAGNOSTIC 216 1.3.2.2 yamt const int old_mtx_count = ci->ci_mtx_count; 217 1.3.2.2 yamt const int old_l_biglocks = ci->ci_curlwp->l_biglocks; 218 1.3.2.2 yamt #endif 219 1.3.2.2 yamt #ifdef DEBUG 220 1.3.2.2 yamt size_t n = 0; 221 1.3.2.2 yamt #endif 222 1.3.2.2 yamt 223 1.3.2.2 yamt ci->ci_data.cpu_nintr++; 224 1.3.2.2 yamt 225 1.3.2.2 yamt KASSERTMSG(old_ipl != IPL_HIGH, "old_ipl %d pmr %#x hppir %#x", 226 1.3.2.2 yamt old_ipl, gicc_read(sc, GICC_PMR), gicc_read(sc, GICC_HPPIR)); 227 1.3.2.2 yamt #if 0 228 1.3.2.2 yamt printf("%s(enter): %s: pmr=%u hppir=%u\n", 229 1.3.2.2 yamt __func__, ci->ci_data.cpu_name, 230 1.3.2.2 yamt gicc_read(sc, GICC_PMR), 231 1.3.2.2 yamt gicc_read(sc, GICC_HPPIR)); 232 1.3.2.2 yamt #elif 0 233 1.3.2.2 yamt printf("(%u:%d", ci->ci_index, old_ipl); 234 1.3.2.2 yamt #endif 235 1.3.2.2 yamt 236 1.3.2.2 yamt for (;;) { 237 1.3.2.2 yamt uint32_t iar = gicc_read(sc, GICC_IAR); 238 1.3.2.2 yamt uint32_t irq = __SHIFTOUT(iar, GICC_IAR_IRQ); 239 1.3.2.2 yamt //printf(".%u", irq); 240 1.3.2.2 yamt if (irq == GICC_IAR_IRQ_SPURIOUS) { 241 1.3.2.2 yamt iar = gicc_read(sc, GICC_IAR); 242 1.3.2.2 yamt irq = __SHIFTOUT(iar, GICC_IAR_IRQ); 243 1.3.2.2 yamt if (irq == GICC_IAR_IRQ_SPURIOUS) 244 1.3.2.2 yamt break; 245 1.3.2.2 yamt //printf(".%u", irq); 246 1.3.2.2 yamt } 247 1.3.2.2 yamt 248 1.3.2.2 yamt //const uint32_t cpuid = __SHIFTOUT(iar, GICC_IAR_CPUID_MASK); 249 1.3.2.2 yamt struct intrsource * const is = sc->sc_pic.pic_sources[irq]; 250 1.3.2.2 yamt KASSERT(is != &armgic_dummy_source); 251 1.3.2.2 yamt 252 1.3.2.2 yamt /* 253 1.3.2.2 yamt * GIC has asserted IPL for us so we can just update ci_cpl. 254 1.3.2.2 yamt * 255 1.3.2.2 yamt * But it's not that simple. We may have already bumped ci_cpl 256 1.3.2.2 yamt * due to a high priority interrupt and now we are about to 257 1.3.2.2 yamt * dispatch one lower than the previous. It's possible for 258 1.3.2.2 yamt * that previous interrupt to have deferred some interrupts 259 1.3.2.2 yamt * so we need deal with those when lowering to the current 260 1.3.2.2 yamt * interrupt's ipl. 261 1.3.2.2 yamt * 262 1.3.2.2 yamt * However, if are just raising ipl, we can just update ci_cpl. 263 1.3.2.2 yamt */ 264 1.3.2.2 yamt #if 0 265 1.3.2.2 yamt const int ipl = armgic_priority_to_ipl(gicc_read(sc, GICC_RPR)); 266 1.3.2.2 yamt KASSERTMSG(panicstr != NULL || ipl == is->is_ipl, 267 1.3.2.2 yamt "%s: irq %d: running ipl %d != source ipl %u", 268 1.3.2.2 yamt ci->ci_data.cpu_name, irq, ipl, is->is_ipl); 269 1.3.2.2 yamt #else 270 1.3.2.2 yamt const int ipl = is->is_ipl; 271 1.3.2.2 yamt #endif 272 1.3.2.2 yamt if (__predict_false(ipl < ci->ci_cpl)) { 273 1.3.2.2 yamt //printf("<"); 274 1.3.2.2 yamt pic_do_pending_ints(I32_bit, ipl, tf); 275 1.3.2.2 yamt KASSERT(ci->ci_cpl == ipl); 276 1.3.2.2 yamt } else { 277 1.3.2.2 yamt KASSERTMSG(ipl > ci->ci_cpl, "ipl %d cpl %d hw-ipl %#x", 278 1.3.2.2 yamt ipl, ci->ci_cpl, 279 1.3.2.2 yamt gicc_read(sc, GICC_PMR)); 280 1.3.2.2 yamt //printf(">"); 281 1.3.2.2 yamt gicc_write(sc, GICC_PMR, armgic_ipl_to_priority(ipl)); 282 1.3.2.2 yamt ci->ci_cpl = ipl; 283 1.3.2.2 yamt } 284 1.3.2.2 yamt //printf("$"); 285 1.3.2.2 yamt cpsie(I32_bit); 286 1.3.2.2 yamt pic_dispatch(is, tf); 287 1.3.2.2 yamt cpsid(I32_bit); 288 1.3.2.2 yamt gicc_write(sc, GICC_EOIR, iar); 289 1.3.2.2 yamt #ifdef DEBUG 290 1.3.2.2 yamt n++; 291 1.3.2.2 yamt KDASSERTMSG(n < 5, "%s: processed too many (%zu)", 292 1.3.2.2 yamt ci->ci_data.cpu_name, n); 293 1.3.2.2 yamt #endif 294 1.3.2.2 yamt } 295 1.3.2.2 yamt 296 1.3.2.2 yamt // printf("%s(%p): exit (%zu dispatched)\n", __func__, tf, n); 297 1.3.2.2 yamt /* 298 1.3.2.2 yamt * Now handle any pending ints. 299 1.3.2.2 yamt */ 300 1.3.2.2 yamt //printf("!"); 301 1.3.2.2 yamt KASSERT(old_ipl != IPL_HIGH); 302 1.3.2.2 yamt pic_do_pending_ints(I32_bit, old_ipl, tf); 303 1.3.2.2 yamt KASSERTMSG(ci->ci_cpl == old_ipl, "ci_cpl %d old_ipl %d", ci->ci_cpl, old_ipl); 304 1.3.2.2 yamt KASSERT(old_mtx_count == ci->ci_mtx_count); 305 1.3.2.2 yamt KASSERT(old_l_biglocks == ci->ci_curlwp->l_biglocks); 306 1.3.2.2 yamt #if 0 307 1.3.2.2 yamt printf("%s(exit): %s(%d): pmr=%u hppir=%u\n", 308 1.3.2.2 yamt __func__, ci->ci_data.cpu_name, ci->ci_cpl, 309 1.3.2.2 yamt gicc_read(sc, GICC_PMR), 310 1.3.2.2 yamt gicc_read(sc, GICC_HPPIR)); 311 1.3.2.2 yamt #elif 0 312 1.3.2.2 yamt printf("->%#x)", ((struct trapframe *)tf)->tf_pc); 313 1.3.2.2 yamt #endif 314 1.3.2.2 yamt } 315 1.3.2.2 yamt 316 1.3.2.2 yamt void 317 1.3.2.2 yamt armgic_establish_irq(struct pic_softc *pic, struct intrsource *is) 318 1.3.2.2 yamt { 319 1.3.2.2 yamt struct armgic_softc * const sc = PICTOSOFTC(pic); 320 1.3.2.2 yamt const size_t group = is->is_irq / 32; 321 1.3.2.2 yamt const u_int irq = is->is_irq & 31; 322 1.3.2.2 yamt const u_int byte_shift = 8 * (irq & 3); 323 1.3.2.2 yamt const u_int twopair_shift = 2 * (irq & 15); 324 1.3.2.2 yamt 325 1.3.2.2 yamt KASSERTMSG(sc->sc_gic_valid_lines[group] & __BIT(irq), 326 1.3.2.2 yamt "irq %u: not valid (group[%zu]=0x%08x [0x%08x])", 327 1.3.2.2 yamt is->is_irq, group, sc->sc_gic_valid_lines[group], 328 1.3.2.2 yamt (uint32_t)__BIT(irq)); 329 1.3.2.2 yamt 330 1.3.2.2 yamt KASSERTMSG(is->is_type == IST_LEVEL || is->is_type == IST_EDGE, 331 1.3.2.2 yamt "irq %u: type %u unsupported", is->is_irq, is->is_type); 332 1.3.2.2 yamt 333 1.3.2.2 yamt const bus_size_t targets_reg = GICD_ITARGETSRn(is->is_irq / 4); 334 1.3.2.2 yamt const bus_size_t cfg_reg = GICD_ICFGRn(is->is_irq / 16); 335 1.3.2.2 yamt uint32_t targets = gicd_read(sc, targets_reg); 336 1.3.2.2 yamt uint32_t cfg = gicd_read(sc, cfg_reg); 337 1.3.2.2 yamt 338 1.3.2.2 yamt if (group > 0) { 339 1.3.2.2 yamt /* 340 1.3.2.2 yamt * There are 4 irqs per TARGETS register. For now bind 341 1.3.2.2 yamt * to the primary cpu. 342 1.3.2.2 yamt */ 343 1.3.2.2 yamt targets &= ~(0xff << byte_shift); 344 1.3.2.2 yamt targets |= 1 << byte_shift; 345 1.3.2.2 yamt gicd_write(sc, targets_reg, targets); 346 1.3.2.2 yamt 347 1.3.2.2 yamt /* 348 1.3.2.2 yamt * There are 16 irqs per CFG register. 10=EDGE 00=LEVEL 349 1.3.2.2 yamt */ 350 1.3.2.2 yamt uint32_t new_cfg = cfg; 351 1.3.2.2 yamt uint32_t old_cfg = (cfg >> twopair_shift) & 3; 352 1.3.2.2 yamt if (is->is_type == IST_LEVEL && (old_cfg & 2) != 0) { 353 1.3.2.2 yamt new_cfg &= ~(3 << twopair_shift); 354 1.3.2.2 yamt } else if (is->is_type == IST_EDGE && (old_cfg & 2) == 0) { 355 1.3.2.2 yamt new_cfg |= 2 << twopair_shift; 356 1.3.2.2 yamt } 357 1.3.2.2 yamt if (new_cfg != cfg) { 358 1.3.2.2 yamt gicd_write(sc, cfg_reg, cfg); 359 1.3.2.2 yamt #if 0 360 1.3.2.2 yamt printf("%s: irq %u: cfg changed from %#x to %#x\n", 361 1.3.2.2 yamt pic->pic_name, is->is_irq, cfg, new_cfg); 362 1.3.2.2 yamt #endif 363 1.3.2.2 yamt } 364 1.3.2.2 yamt } 365 1.3.2.2 yamt 366 1.3.2.2 yamt /* 367 1.3.2.2 yamt * There are 4 irqs per PRIORITY register. Map the IPL 368 1.3.2.2 yamt * to GIC priority. 369 1.3.2.2 yamt */ 370 1.3.2.2 yamt const bus_size_t priority_reg = GICD_IPRIORITYRn(is->is_irq / 4); 371 1.3.2.2 yamt uint32_t priority = gicd_read(sc, priority_reg); 372 1.3.2.2 yamt priority &= ~(0xff << byte_shift); 373 1.3.2.2 yamt priority |= armgic_ipl_to_priority(is->is_ipl) << byte_shift; 374 1.3.2.2 yamt gicd_write(sc, priority_reg, priority); 375 1.3.2.2 yamt 376 1.3.2.2 yamt #if 0 377 1.3.2.2 yamt printf("%s: irq %u: target %#x cfg %u priority %#x (%u)\n", 378 1.3.2.2 yamt pic->pic_name, is->is_irq, (targets >> byte_shift) & 0xff, 379 1.3.2.2 yamt (cfg >> twopair_shift) & 3, (priority >> byte_shift) & 0xff, 380 1.3.2.2 yamt is->is_ipl); 381 1.3.2.2 yamt #endif 382 1.3.2.2 yamt } 383 1.3.2.2 yamt 384 1.3.2.2 yamt #ifdef MULTIPROCESSOR 385 1.3.2.2 yamt static void 386 1.3.2.2 yamt armgic_cpu_init_priorities(struct armgic_softc *sc) 387 1.3.2.2 yamt { 388 1.3.2.2 yamt uint32_t enabled = sc->sc_enabled_local; 389 1.3.2.2 yamt for (size_t i = 0; i < 32; i += 4, enabled >>= 4) { 390 1.3.2.2 yamt /* 391 1.3.2.2 yamt * If there are no enabled interrupts for the priority register, 392 1.3.2.2 yamt * don't bother changing it. 393 1.3.2.2 yamt */ 394 1.3.2.2 yamt if ((enabled & 0x0f) == 0) 395 1.3.2.2 yamt continue; 396 1.3.2.2 yamt /* 397 1.3.2.2 yamt * Since priorities are in 3210 order, it' 398 1.3.2.2 yamt */ 399 1.3.2.2 yamt const bus_size_t priority_reg = GICD_IPRIORITYRn(i / 4); 400 1.3.2.2 yamt uint32_t priority = gicd_read(sc, priority_reg); 401 1.3.2.2 yamt uint32_t byte_mask = 0xff; 402 1.3.2.2 yamt size_t byte_shift = 0; 403 1.3.2.2 yamt for (size_t j = 0; j < 4; j++, byte_mask <<= 8, byte_shift += 8) { 404 1.3.2.2 yamt struct intrsource * const is = sc->sc_pic.pic_sources[i+j]; 405 1.3.2.2 yamt if (is == NULL || is == &armgic_dummy_source) 406 1.3.2.2 yamt continue; 407 1.3.2.2 yamt priority &= ~byte_mask; 408 1.3.2.2 yamt priority |= armgic_ipl_to_priority(is->is_ipl) << byte_shift; 409 1.3.2.2 yamt } 410 1.3.2.2 yamt gicd_write(sc, priority_reg, priority); 411 1.3.2.2 yamt } 412 1.3.2.2 yamt } 413 1.3.2.2 yamt 414 1.3.2.2 yamt void 415 1.3.2.2 yamt armgic_cpu_init(struct pic_softc *pic, struct cpu_info *ci) 416 1.3.2.2 yamt { 417 1.3.2.2 yamt struct armgic_softc * const sc = PICTOSOFTC(pic); 418 1.3.2.2 yamt if (!CPU_IS_PRIMARY(ci) && sc->sc_enabled_local) { 419 1.3.2.2 yamt armgic_cpu_init_priorities(sc); 420 1.3.2.2 yamt } 421 1.3.2.2 yamt KASSERTMSG(ci->ci_cpl == IPL_HIGH, "ipl %d not IPL_HIGH", ci->ci_cpl); 422 1.3.2.2 yamt gicc_write(sc, GICC_PMR, armgic_ipl_to_priority(ci->ci_cpl)); // set PMR 423 1.3.2.2 yamt gicc_write(sc, GICC_CTRL, GICC_CTRL_V1_Enable); // enable interrupt 424 1.3.2.2 yamt if (!CPU_IS_PRIMARY(ci) && sc->sc_enabled_local) 425 1.3.2.2 yamt gicd_write(sc, GICD_ISENABLERn(0), sc->sc_enabled_local); 426 1.3.2.2 yamt cpsie(I32_bit); // allow IRQ exceptions 427 1.3.2.2 yamt } 428 1.3.2.2 yamt 429 1.3.2.2 yamt void 430 1.3.2.2 yamt armgic_ipi_send(struct pic_softc *pic, const kcpuset_t *kcp, u_long ipi) 431 1.3.2.2 yamt { 432 1.3.2.2 yamt struct armgic_softc * const sc = PICTOSOFTC(pic); 433 1.3.2.2 yamt 434 1.3.2.2 yamt if (ipi == IPI_NOP) { 435 1.3.2.2 yamt __asm __volatile("sev"); 436 1.3.2.2 yamt return; 437 1.3.2.2 yamt } 438 1.3.2.2 yamt 439 1.3.2.2 yamt uint32_t targets; 440 1.3.2.2 yamt kcpuset_export_u32(kcp, &targets, sizeof(targets)); 441 1.3.2.2 yamt uint32_t sgir = __SHIFTOUT(ARMGIC_SGI_IPIBASE + ipi, GICD_SGIR_SGIINTID); 442 1.3.2.2 yamt sgir |= __SHIFTOUT(targets, GICD_SGIR_TargetList); 443 1.3.2.2 yamt 444 1.3.2.2 yamt printf("%s: %s: %#x", __func__, curcpu()->ci_data.cpu_name, sgir); 445 1.3.2.2 yamt gicd_write(sc, GICD_SGIR, sgir); 446 1.3.2.2 yamt printf("\n"); 447 1.3.2.2 yamt } 448 1.3.2.2 yamt #endif 449 1.3.2.2 yamt 450 1.3.2.2 yamt int 451 1.3.2.2 yamt armgic_match(device_t parent, cfdata_t cf, void *aux) 452 1.3.2.2 yamt { 453 1.3.2.2 yamt struct mpcore_attach_args * const mpcaa = aux; 454 1.3.2.2 yamt 455 1.3.2.2 yamt if (strcmp(cf->cf_name, mpcaa->mpcaa_name) != 0) 456 1.3.2.2 yamt return 0; 457 1.3.2.2 yamt if (!CPU_ID_CORTEX_P(cputype)) 458 1.3.2.2 yamt return 0; 459 1.3.2.2 yamt if (CPU_ID_CORTEX_A8_P(cputype)) 460 1.3.2.2 yamt return 0; 461 1.3.2.2 yamt 462 1.3.2.2 yamt return 1; 463 1.3.2.2 yamt } 464 1.3.2.2 yamt 465 1.3.2.2 yamt void 466 1.3.2.2 yamt armgic_attach(device_t parent, device_t self, void *aux) 467 1.3.2.2 yamt { 468 1.3.2.2 yamt struct armgic_softc * const sc = &armgic_softc; 469 1.3.2.2 yamt struct mpcore_attach_args * const mpcaa = aux; 470 1.3.2.2 yamt 471 1.3.2.2 yamt sc->sc_dev = self; 472 1.3.2.2 yamt self->dv_private = sc; 473 1.3.2.2 yamt 474 1.3.2.2 yamt sc->sc_memt = mpcaa->mpcaa_memt; /* provided for us */ 475 1.3.2.2 yamt sc->sc_memh = mpcaa->mpcaa_memh; /* provided for us */ 476 1.3.2.2 yamt 477 1.3.2.2 yamt sc->sc_gic_type = gicd_read(sc, GICD_TYPER); 478 1.3.2.2 yamt sc->sc_pic.pic_maxsources = GICD_TYPER_LINES(sc->sc_gic_type); 479 1.3.2.2 yamt 480 1.3.2.2 yamt gicc_write(sc, GICC_CTRL, 0); /* disable all interrupts */ 481 1.3.2.2 yamt gicd_write(sc, GICD_CTRL, 0); /* disable all interrupts */ 482 1.3.2.2 yamt 483 1.3.2.2 yamt gicc_write(sc, GICC_PMR, 0xff); 484 1.3.2.2 yamt uint32_t pmr = gicc_read(sc, GICC_PMR); 485 1.3.2.2 yamt u_int priorities = 1 << popcount32(pmr); 486 1.3.2.2 yamt 487 1.3.2.2 yamt /* 488 1.3.2.2 yamt * Let's find out how many real sources we have. 489 1.3.2.2 yamt */ 490 1.3.2.2 yamt for (size_t i = 0, group = 0; 491 1.3.2.2 yamt i < sc->sc_pic.pic_maxsources; 492 1.3.2.2 yamt i += 32, group++) { 493 1.3.2.2 yamt /* 494 1.3.2.2 yamt * To figure what sources are real, one enables all interrupts 495 1.3.2.2 yamt * and then reads back the enable mask so which ones really 496 1.3.2.2 yamt * got enabled. 497 1.3.2.2 yamt */ 498 1.3.2.2 yamt gicd_write(sc, GICD_ISENABLERn(group), 0xffffffff); 499 1.3.2.2 yamt uint32_t valid = gicd_read(sc, GICD_ISENABLERn(group)); 500 1.3.2.2 yamt 501 1.3.2.2 yamt /* 502 1.3.2.2 yamt * Now disable (clear enable) them again. 503 1.3.2.2 yamt */ 504 1.3.2.2 yamt gicd_write(sc, GICD_ICENABLERn(group), valid); 505 1.3.2.2 yamt 506 1.3.2.2 yamt /* 507 1.3.2.2 yamt * Count how many are valid. 508 1.3.2.2 yamt */ 509 1.3.2.2 yamt sc->sc_gic_lines += popcount32(valid); 510 1.3.2.2 yamt sc->sc_gic_valid_lines[group] = valid; 511 1.3.2.2 yamt } 512 1.3.2.2 yamt 513 1.3.2.2 yamt pic_add(&sc->sc_pic, 0); 514 1.3.2.2 yamt 515 1.3.2.2 yamt /* 516 1.3.2.2 yamt * Force the GICD to IPL_HIGH and then enable interrupts. 517 1.3.2.2 yamt */ 518 1.3.2.2 yamt struct cpu_info * const ci = curcpu(); 519 1.3.2.2 yamt KASSERTMSG(ci->ci_cpl == IPL_HIGH, "ipl %d not IPL_HIGH", ci->ci_cpl); 520 1.3.2.2 yamt armgic_set_priority(&sc->sc_pic, ci->ci_cpl); // set PMR 521 1.3.2.2 yamt gicd_write(sc, GICD_CTRL, GICD_CTRL_Enable); // enable Distributer 522 1.3.2.2 yamt gicc_write(sc, GICC_CTRL, GICC_CTRL_V1_Enable); // enable CPU interrupts 523 1.3.2.2 yamt cpsie(I32_bit); // allow interrupt exceptions 524 1.3.2.2 yamt 525 1.3.2.2 yamt /* 526 1.3.2.2 yamt * For each line that isn't valid, we set the intrsource for it to 527 1.3.2.2 yamt * point at a dummy source so that pic_intr_establish will fail for it. 528 1.3.2.2 yamt */ 529 1.3.2.2 yamt for (size_t i = 0, group = 0; 530 1.3.2.2 yamt i < sc->sc_pic.pic_maxsources; 531 1.3.2.2 yamt i += 32, group++) { 532 1.3.2.2 yamt uint32_t invalid = ~sc->sc_gic_valid_lines[group]; 533 1.3.2.2 yamt for (size_t j = 0; invalid && j < 32; j++, invalid >>= 1) { 534 1.3.2.2 yamt if (invalid & 1) { 535 1.3.2.2 yamt sc->sc_pic.pic_sources[i + j] = 536 1.3.2.2 yamt &armgic_dummy_source; 537 1.3.2.2 yamt } 538 1.3.2.2 yamt } 539 1.3.2.2 yamt } 540 1.3.2.2 yamt #ifdef __HAVE_PIC_FAST_SOFTINTS 541 1.3.2.2 yamt intr_establish(SOFTINT_BIO, IPL_SOFTBIO, IST_EDGE, 542 1.3.2.2 yamt pic_handle_softint, (void *)SOFTINT_BIO); 543 1.3.2.2 yamt intr_establish(SOFTINT_CLOCK, IPL_SOFTCLOCK, IST_EDGE, 544 1.3.2.2 yamt pic_handle_softint, (void *)SOFTINT_CLOCK); 545 1.3.2.2 yamt intr_establish(SOFTINT_NET, IPL_SOFTNET, IST_EDGE, 546 1.3.2.2 yamt pic_handle_softint, (void *)SOFTINT_NET); 547 1.3.2.2 yamt intr_establish(SOFTINT_SERIAL, IPL_SOFTSERIAL, IST_EDGE, 548 1.3.2.2 yamt pic_handle_softint, (void *)SOFTINT_SERIAL); 549 1.3.2.2 yamt #endif 550 1.3.2.2 yamt #ifdef MULTIPROCESSOR 551 1.3.2.2 yamt intr_establish(ARMGIC_SGI_IPIBASE + IPI_AST, IPL_VM, IST_EDGE, 552 1.3.2.2 yamt pic_ipi_nop, (void *)-1); 553 1.3.2.2 yamt intr_establish(ARMGIC_SGI_IPIBASE + IPI_XCALL, IPL_VM, IST_EDGE, 554 1.3.2.2 yamt pic_ipi_xcall, (void *)-1); 555 1.3.2.2 yamt #if 0 /* Not needed */ 556 1.3.2.2 yamt intr_establish(ARMGIC_SGI_IPIBASE + IPI_NOP, IPL_VM, IST_EDGE, 557 1.3.2.2 yamt pic_ipi_nop, (void *)-1); 558 1.3.2.2 yamt #endif 559 1.3.2.2 yamt #ifdef __HAVE_PREEMPTION 560 1.3.2.2 yamt intr_establish(ARMGIC_SGI_IPIBASE + IPI_KPREEMPT, IPL_VM, IST_EDGE, 561 1.3.2.2 yamt pic_ipi_nop, (void *)-1); 562 1.3.2.2 yamt #endif 563 1.3.2.2 yamt armgic_cpu_init(&sc->sc_pic, curcpu()); 564 1.3.2.2 yamt #endif 565 1.3.2.2 yamt 566 1.3.2.2 yamt aprint_normal(": Generic Interrupt Controller, " 567 1.3.2.2 yamt "%zu sources (%zu valid)\n", 568 1.3.2.2 yamt sc->sc_pic.pic_maxsources, sc->sc_gic_lines); 569 1.3.2.2 yamt 570 1.3.2.2 yamt const u_int ppis = popcount32(sc->sc_gic_valid_lines[0] >> 16); 571 1.3.2.2 yamt const u_int sgis = popcount32(sc->sc_gic_valid_lines[0] & 0xffff); 572 1.3.2.2 yamt aprint_normal_dev(sc->sc_dev, "%u Priorities, %zu SPIs, %u PPIs, %u SGIs\n", 573 1.3.2.2 yamt priorities, sc->sc_gic_lines - ppis - sgis, ppis, sgis); 574 1.3.2.2 yamt } 575 1.3.2.2 yamt 576 1.3.2.2 yamt CFATTACH_DECL_NEW(armgic, 0, 577 1.3.2.2 yamt armgic_match, armgic_attach, NULL, NULL); 578
Indexes created Wed Oct 01 19:09:53 GMT 2025