pl310.c revision 1.13
1 /* $NetBSD: pl310.c,v 1.13 2014/02/23 21:19:06 matt Exp $ */ 2 3 /*- 4 * Copyright (c) 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: pl310.c,v 1.13 2014/02/23 21:19:06 matt Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/bus.h> 37 #include <sys/cpu.h> 38 #include <sys/device.h> 39 #include <sys/atomic.h> 40 41 #include <arm/locore.h> 42 43 #include <arm/cortex/mpcore_var.h> 44 #include <arm/cortex/pl310_reg.h> 45 #include <arm/cortex/pl310_var.h> 46 47 static int arml2cc_match(device_t, cfdata_t, void *); 48 static void arml2cc_attach(device_t, device_t, void *); 49 50 #define L2CC_BASE 0x2000 51 #define L2CC_SIZE 0x1000 52 53 struct arml2cc_softc { 54 device_t sc_dev; 55 bus_space_tag_t sc_memt; 56 bus_space_handle_t sc_memh; 57 kmutex_t sc_lock; 58 uint32_t sc_waymask; 59 struct evcnt sc_ev_inv __aligned(8); 60 struct evcnt sc_ev_wb; 61 struct evcnt sc_ev_wbinv; 62 bool sc_enabled; 63 }; 64 65 __CTASSERT(offsetof(struct arml2cc_softc, sc_ev_inv.ev_count) % 8 == 0); 66 __CTASSERT(offsetof(struct arml2cc_softc, sc_ev_wb.ev_count) % 8 == 0); 67 __CTASSERT(offsetof(struct arml2cc_softc, sc_ev_wbinv.ev_count) % 8 == 0); 68 69 CFATTACH_DECL_NEW(arml2cc, sizeof(struct arml2cc_softc), 70 arml2cc_match, arml2cc_attach, NULL, NULL); 71 72 static inline void arml2cc_disable(struct arml2cc_softc *); 73 static inline void arml2cc_enable(struct arml2cc_softc *); 74 static void arml2cc_sdcache_wb_range(vaddr_t, paddr_t, psize_t); 75 static void arml2cc_sdcache_inv_range(vaddr_t, paddr_t, psize_t); 76 static void arml2cc_sdcache_wbinv_range(vaddr_t, paddr_t, psize_t); 77 78 static struct arml2cc_softc *arml2cc_sc; 79 80 static inline uint32_t 81 arml2cc_read_4(struct arml2cc_softc *sc, bus_size_t o) 82 { 83 return bus_space_read_4(sc->sc_memt, sc->sc_memh, o); 84 } 85 86 static inline void 87 arml2cc_write_4(struct arml2cc_softc *sc, bus_size_t o, uint32_t v) 88 { 89 bus_space_write_4(sc->sc_memt, sc->sc_memh, o, v); 90 } 91 92 93 /* ARGSUSED */ 94 static int 95 arml2cc_match(device_t parent, cfdata_t cf, void *aux) 96 { 97 struct mpcore_attach_args * const mpcaa = aux; 98 99 if (arml2cc_sc) 100 return 0; 101 102 if (!CPU_ID_CORTEX_A9_P(curcpu()->ci_arm_cpuid)) 103 return 0; 104 105 if (strcmp(mpcaa->mpcaa_name, cf->cf_name) != 0) 106 return 0; 107 108 /* 109 * This isn't present on UP A9s (since CBAR isn't present). 110 */ 111 uint32_t mpidr = armreg_mpidr_read(); 112 if (mpidr == 0 || (mpidr & MPIDR_U)) 113 return 0; 114 115 return 1; 116 } 117 118 static const struct { 119 uint8_t rev; 120 uint8_t str[7]; 121 } pl310_revs[] = { 122 { 0, " r0p0" }, 123 { 2, " r1p0" }, 124 { 4, " r2p0" }, 125 { 5, " r3p0" }, 126 { 6, " r3p1" }, 127 { 8, " r3p2" }, 128 { 9, " r3p3" }, 129 }; 130 131 static void 132 arml2cc_attach(device_t parent, device_t self, void *aux) 133 { 134 struct arml2cc_softc * const sc = device_private(self); 135 struct mpcore_attach_args * const mpcaa = aux; 136 const char * const xname = device_xname(self); 137 138 arml2cc_sc = sc; 139 sc->sc_dev = self; 140 sc->sc_memt = mpcaa->mpcaa_memt; 141 sc->sc_waymask = __BIT(arm_scache.dcache_ways) - 1; 142 143 evcnt_attach_dynamic(&sc->sc_ev_inv, EVCNT_TYPE_MISC, NULL, 144 xname, "L2 inv requests"); 145 evcnt_attach_dynamic(&sc->sc_ev_wb, EVCNT_TYPE_MISC, NULL, 146 xname, "L2 wb requests"); 147 evcnt_attach_dynamic(&sc->sc_ev_wbinv, EVCNT_TYPE_MISC, NULL, 148 xname, "L2 wbinv requests"); 149 150 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_HIGH); 151 152 bus_space_subregion(sc->sc_memt, mpcaa->mpcaa_memh, 153 L2CC_BASE, L2CC_SIZE, &sc->sc_memh); 154 155 uint32_t id = arml2cc_read_4(sc, L2C_CACHE_ID); 156 u_int rev = __SHIFTOUT(id, CACHE_ID_REV); 157 158 const char *revstr = ""; 159 for (size_t i = 0; i < __arraycount(pl310_revs); i++) { 160 if (rev == pl310_revs[i].rev) { 161 revstr = pl310_revs[i].str; 162 break; 163 } 164 } 165 166 const bool enabled_p = arml2cc_read_4(sc, L2C_CTL) != 0; 167 168 aprint_naive("\n"); 169 aprint_normal(": ARM PL310%s L2 Cache Controller%s\n", 170 revstr, enabled_p ? "" : " (disabled)"); 171 172 if (enabled_p) { 173 if (device_cfdata(self)->cf_flags & 1) { 174 arml2cc_disable(sc); 175 aprint_normal_dev(self, "cache %s\n", 176 arml2cc_read_4(sc, L2C_CTL) ? "enabled" : "disabled"); 177 sc->sc_enabled = false; 178 } else { 179 cpufuncs.cf_sdcache_wb_range = arml2cc_sdcache_wb_range; 180 cpufuncs.cf_sdcache_inv_range = arml2cc_sdcache_inv_range; 181 cpufuncs.cf_sdcache_wbinv_range = arml2cc_sdcache_wbinv_range; 182 sc->sc_enabled = true; 183 } 184 } else if ((device_cfdata(self)->cf_flags & 1) == 0) { 185 if (!enabled_p) { 186 arml2cc_enable(sc); 187 aprint_normal_dev(self, "cache %s\n", 188 arml2cc_read_4(sc, L2C_CTL) ? "enabled" : "disabled"); 189 } 190 cpufuncs.cf_sdcache_wb_range = arml2cc_sdcache_wb_range; 191 cpufuncs.cf_sdcache_inv_range = arml2cc_sdcache_inv_range; 192 cpufuncs.cf_sdcache_wbinv_range = arml2cc_sdcache_wbinv_range; 193 sc->sc_enabled = true; 194 } 195 196 KASSERTMSG(arm_pcache.dcache_line_size == arm_scache.dcache_line_size, 197 "pcache %u scache %u", 198 arm_pcache.dcache_line_size, arm_scache.dcache_line_size); 199 } 200 201 static inline void 202 arml2cc_cache_op(struct arml2cc_softc *sc, bus_size_t off, uint32_t val, 203 bool wait) 204 { 205 arml2cc_write_4(sc, off, val); 206 if (wait) { 207 while (arml2cc_read_4(sc, off) & 1) { 208 /* spin */ 209 } 210 } 211 } 212 213 static inline void 214 arml2cc_cache_way_op(struct arml2cc_softc *sc, bus_size_t off, uint32_t way_mask) 215 { 216 arml2cc_write_4(sc, off, way_mask); 217 while (arml2cc_read_4(sc, off) & way_mask) { 218 /* spin */ 219 } 220 } 221 222 static inline void 223 arml2cc_cache_sync(struct arml2cc_softc *sc) 224 { 225 arml2cc_cache_op(sc, L2C_CACHE_SYNC, 0, true); 226 } 227 228 static inline void 229 arml2cc_disable(struct arml2cc_softc *sc) 230 { 231 mutex_spin_enter(&sc->sc_lock); 232 233 arml2cc_cache_way_op(sc, L2C_CLEAN_INV_WAY, sc->sc_waymask); 234 arml2cc_cache_sync(sc); 235 236 arml2cc_write_4(sc, L2C_CTL, 0); // turn it off 237 mutex_spin_exit(&sc->sc_lock); 238 } 239 240 static inline void 241 arml2cc_enable(struct arml2cc_softc *sc) 242 { 243 mutex_spin_enter(&sc->sc_lock); 244 245 arml2cc_write_4(sc, L2C_CTL, 1); // turn it on 246 247 arml2cc_cache_way_op(sc, L2C_INV_WAY, sc->sc_waymask); 248 arml2cc_cache_sync(sc); 249 250 mutex_spin_exit(&sc->sc_lock); 251 } 252 253 void 254 arml2cc_init(bus_space_tag_t bst, bus_space_handle_t bsh, bus_size_t o) 255 { 256 struct arm_cache_info * const info = &arm_scache; 257 258 uint32_t cfg = bus_space_read_4(bst, bsh, o + L2C_CACHE_TYPE); 259 260 info->cache_type = __SHIFTOUT(cfg, CACHE_TYPE_CTYPE); 261 info->cache_unified = __SHIFTOUT(cfg, CACHE_TYPE_HARVARD) == 0; 262 u_int cfg_dsize = __SHIFTOUT(cfg, CACHE_TYPE_DSIZE); 263 264 u_int d_waysize = 8192 << __SHIFTOUT(cfg_dsize, CACHE_TYPE_xWAYSIZE); 265 info->dcache_ways = 8 << __SHIFTOUT(cfg_dsize, CACHE_TYPE_xASSOC); 266 info->dcache_line_size = 32 << __SHIFTOUT(cfg_dsize, CACHE_TYPE_xLINESIZE); 267 info->dcache_size = info->dcache_ways * d_waysize; 268 269 if (info->cache_unified) { 270 info->icache_ways = info->dcache_ways; 271 info->icache_line_size = info->dcache_line_size; 272 info->icache_size = info->dcache_size; 273 } else { 274 u_int cfg_isize = __SHIFTOUT(cfg, CACHE_TYPE_ISIZE); 275 u_int i_waysize = 8192 << __SHIFTOUT(cfg_isize, CACHE_TYPE_xWAYSIZE); 276 info->icache_ways = 8 << __SHIFTOUT(cfg_isize, CACHE_TYPE_xASSOC); 277 info->icache_line_size = 32 << __SHIFTOUT(cfg_isize, CACHE_TYPE_xLINESIZE); 278 info->icache_size = i_waysize * info->icache_ways; 279 } 280 } 281 282 static void 283 arml2cc_cache_range_op(paddr_t pa, psize_t len, bus_size_t cache_op) 284 { 285 struct arml2cc_softc * const sc = arml2cc_sc; 286 const size_t line_size = arm_scache.dcache_line_size; 287 const size_t line_mask = line_size - 1; 288 size_t off = pa & line_mask; 289 if (off) { 290 len += off; 291 pa -= off; 292 } 293 len = roundup2(len, line_size); 294 mutex_spin_enter(&sc->sc_lock); 295 if (__predict_false(!sc->sc_enabled)) { 296 mutex_spin_exit(&sc->sc_lock); 297 return; 298 } 299 for (const paddr_t endpa = pa + len; pa < endpa; pa += line_size) { 300 arml2cc_cache_op(sc, cache_op, pa, false); 301 } 302 arml2cc_cache_sync(sc); 303 mutex_spin_exit(&sc->sc_lock); 304 } 305 306 static void 307 arml2cc_sdcache_inv_range(vaddr_t va, paddr_t pa, psize_t len) 308 { 309 atomic_inc_64(&arml2cc_sc->sc_ev_inv.ev_count); 310 arml2cc_cache_range_op(pa, len, L2C_INV_PA); 311 } 312 313 static void 314 arml2cc_sdcache_wb_range(vaddr_t va, paddr_t pa, psize_t len) 315 { 316 atomic_inc_64(&arml2cc_sc->sc_ev_wb.ev_count); 317 arml2cc_cache_range_op(pa, len, L2C_CLEAN_PA); 318 } 319 320 static void 321 arml2cc_sdcache_wbinv_range(vaddr_t va, paddr_t pa, psize_t len) 322 { 323 atomic_inc_64(&arml2cc_sc->sc_ev_wbinv.ev_count); 324 arml2cc_cache_range_op(pa, len, L2C_CLEAN_INV_PA); 325 } 326
Indexes created Wed Sep 24 05:09:52 GMT 2025