| History log of /src/sys/arch/arm/cortex/pl310.c |
| Revision | | Date | Author | Comments |
| 1.20 |
| 02-Oct-2021 |
skrll | Trailing whitespace
|
| 1.19 |
| 19-Jan-2019 |
jmcneill | Remove hard requirement for "offset" property on Cortex-A5. This is not required w/ FDT.
|
| 1.18 |
| 20-Jun-2018 |
hkenken | branches: 1.18.2;
Add l2cc support.
|
| 1.17 |
| 27-Feb-2015 |
jmcneill | branches: 1.17.16;
allow arml2cc to be used on Cortex-A5 if the "offset" property is specified
|
| 1.16 |
| 01-Dec-2014 |
matt | clean the a9 l2 cache before turning it on.
|
| 1.15 |
| 16-Apr-2014 |
matt | branches: 1.15.2; 1.15.4;
Allow l2cc base to gotten from device properties.
|
| 1.14 |
| 20-Mar-2014 |
matt | branches: 1.14.2;
pl310 cache is PIPT
|
| 1.13 |
| 23-Feb-2014 |
matt | #include <arm/locore.h>
|
| 1.12 |
| 17-Jun-2013 |
matt | branches: 1.12.2; 1.12.6;
KASSERT -> KASSERTMSG
|
| 1.11 |
| 13-Feb-2013 |
matt | simplify cache range op
|
| 1.10 |
| 22-Jan-2013 |
matt | Don't "sync" atomic ops.
Do sync after each range op.
|
| 1.9 |
| 28-Nov-2012 |
matt | Make these compile with gcc4.1 and binutils 2.16
|
| 1.8 |
| 01-Nov-2012 |
matt | branches: 1.8.2;
Invalidate the L2 cache before enabling it.
|
| 1.7 |
| 17-Oct-2012 |
matt | branches: 1.7.2;
Add a missing mutex exit.
|
| 1.6 |
| 22-Sep-2012 |
matt | Don't use an asm in pmap_activate to update the TTBR, use cpu_setttb instead
but add a second argument to it to indicate whether the TLB/caches need to be
flushed. Default cortex to pmap_needs_fixup = 1. But check the MMFR3 field
to see if the fixed can be skipped.
Use a cf_flag bit 0 to indicate whether the A9 L2 cache should disable (bit 0 = 1)
or enabeld (bit = 0).
With these changes, the A9 MMU can use traverse caches to do MMU tablewalks
Also, make sure all memory has the shareable bit for the A9.
|
| 1.5 |
| 14-Sep-2012 |
matt | Add L2 cache flush routines. (not yet enabled).
|
| 1.4 |
| 07-Sep-2012 |
matt | branches: 1.4.2;
Don't disable the L2C is it isn't enabled.
|
| 1.3 |
| 07-Sep-2012 |
matt | Switch cortex_a9 back to need_ptesync = 1
Add code to disable the L2 cache on cortex-a9 (for now).
Add evcnt for all the fault types.
Move cache info in a structure and have one for the pcache and one for scache.
Probe L1/L2 caches properly for ARMv7
|
| 1.2 |
| 02-Sep-2012 |
matt | Add "write-back" before Unified
|
| 1.1 |
| 02-Sep-2012 |
matt | Add driver to attach ARM PL210 L2 Cache Controller
arml2cc0 at armperiph0: ARM PL310 L2 r3p2 Cache Controller
arml2cc0: 256KB/32B 16-way L2 Unified cache
|
| 1.4.2.5 |
| 03-Dec-2017 |
jdolecek | update from HEAD
|
| 1.4.2.4 |
| 20-Aug-2014 |
tls | Rebase to HEAD as of a few days ago.
|
| 1.4.2.3 |
| 23-Jun-2013 |
tls | resync from head
|
| 1.4.2.2 |
| 25-Feb-2013 |
tls | resync with head
|
| 1.4.2.1 |
| 20-Nov-2012 |
tls | Resync to 2012-11-19 00:00:00 UTC
|
| 1.7.2.5 |
| 22-May-2014 |
yamt | sync with head.
for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.
this commit was splitted into small chunks to avoid
a limitation of cvs. ("Protocol error: too many arguments")
|
| 1.7.2.4 |
| 23-Jan-2013 |
yamt | sync with head
|
| 1.7.2.3 |
| 16-Jan-2013 |
yamt | sync with (a bit old) head
|
| 1.7.2.2 |
| 30-Oct-2012 |
yamt | sync with head
|
| 1.7.2.1 |
| 17-Oct-2012 |
yamt | file pl310.c was added on branch yamt-pagecache on 2012-10-30 17:19:00 +0000
|
| 1.8.2.3 |
| 07-Feb-2013 |
matt | Sync with HEAD
|
| 1.8.2.2 |
| 28-Nov-2012 |
matt | Merge improved arm support (especially Cortex) from HEAD
including OMAP and BCM53xx support.
|
| 1.8.2.1 |
| 01-Nov-2012 |
matt | file pl310.c was added on branch matt-nb6-plus on 2012-11-28 22:40:27 +0000
|
| 1.12.6.2 |
| 15-Feb-2014 |
matt | Merge armv7 support from HEAD, specifically support for the BCM5301X
and BCM56340 evbarm kernels.
|
| 1.12.6.1 |
| 17-Jun-2013 |
matt | file pl310.c was added on branch matt-nb5-mips64 on 2014-02-15 16:18:36 +0000
|
| 1.12.2.1 |
| 18-May-2014 |
rmind | sync with head
|
| 1.14.2.1 |
| 10-Aug-2014 |
tls | Rebase.
|
| 1.15.4.1 |
| 06-Apr-2015 |
skrll | Sync with HEAD
|
| 1.15.2.1 |
| 21-Mar-2015 |
snj | Pull up following revision(s) (requested by jmcneill in ticket #598):
sys/arch/arm/amlogic/amlogic_board.c: up to revision 1.9
sys/arch/arm/amlogic/amlogic_canvasreg.h: revision 1.1
sys/arch/arm/amlogic/amlogic_com.c: up to revision 1.4
sys/arch/arm/amlogic/amlogic_comreg.h: up to revision 1.3
sys/arch/arm/amlogic/amlogic_comvar.h: revision 1.1
sys/arch/arm/amlogic/amlogic_cpufreq.c: up to revision 1.2
sys/arch/arm/amlogic/amlogic_crureg.h: up to revision 1.7
sys/arch/arm/amlogic/amlogic_dwctwo.c: up to revision 1.2
sys/arch/arm/amlogic/amlogic_genfb.c: revision 1.1
sys/arch/arm/amlogic/amlogic_gmac.c: up to revision 1.2
sys/arch/arm/amlogic/amlogic_hdmireg.h: revision 1.1
sys/arch/arm/amlogic/amlogic_intr.h: up to revision 1.5
sys/arch/arm/amlogic/amlogic_io.c: up to revision 1.7
sys/arch/arm/amlogic/amlogic_reg.h: up to revision 1.9
sys/arch/arm/amlogic/amlogic_rng.c: revision 1.1
sys/arch/arm/amlogic/amlogic_sdhc.c: up to revision 1.3
sys/arch/arm/amlogic/amlogic_sdhcreg.h: revision 1.1
sys/arch/arm/amlogic/amlogic_space.c: revision 1.1
sys/arch/arm/amlogic/amlogic_var.h: up to revision 1.8
sys/arch/arm/amlogic/amlogic_vpureg.h: revision 1.1
sys/arch/arm/arm/bootconfig.c: revisions 1.7-1.8
sys/arch/arm/conf/files.arm: revision 1.129
sys/arch/arm/cortex/pl310.c: revisions 1.16-1.17
sys/arch/arm/cortex/a9_mpsubr.S: revisions 1.25-1.29
sys/arch/arm/cortex/a9tmr.c: revisions 1.8-1.12
sys/arch/arm/cortex/a9tmr_var.h: revision 1.4
sys/arch/arm/cortex/a9wdt.c: revisions 1.3-1.4
sys/arch/arm/cortex/armperiph.c: revisions 1.5-1.7
sys/arch/arm/arm/cpufunc.c: revision 1.151
sys/arch/arm/include/bootconfig.h: revision 1.7
sys/arch/arm/include/locore.h: revision 1.19
sys/arch/evbarm/amlogic/amlogic_machdep.c: up to revision 1.17
sys/arch/evbarm/amlogic/amlogic_start.S: up to revision 1.2
sys/arch/evbarm/amlogic/genassym.cf: revision 1.1
sys/arch/evbarm/amlogic/platform.h: revision 1.1
sys/arch/evbarm/conf/files.amlogic: up to revision 1.8
sys/arch/evbarm/conf/std.amlogic: up to revision 1.2
sys/arch/evbarm/conf/mk.amlogic: revision 1.1
sys/arch/evbarm/conf/ODROID-C1: up to revision 1.12
sys/arch/evarm/conf/ODROID-C1_INSTALL: revision 1.1
Don't use not as a variable since it's reserved in C++.
--
clean the a9 l2 cache before turning it on.
--
Add Cortex-A17 support
--
Fix CORTEXA17 support
--
Let the "cbar" device property override the cbar value, to work around
broken bootloaders
--
add a helper to update a9tmr frequency
--
detach and re-attach timecounter when updating freq, and reinit timer on
each cpu
--
fix typo
--
add BOOTOPT_TYPE_MACADDR for parsing mac address parameters
--
make sure we set ACTLR.SMP=1 for CPU_CORTEXA5 in !MP case, ok matt@
--
According to the Cortex-A5 TRM, the CBAR register is not implemented and
always reads as 0x00000000. Add ARM_CBAR option to set this in kernel
config.
--
skip a TLBIALL on Cortex-A5 that stops my odroid-c1 from booting, ok matt
--
match on Cortex-A5
--
match on Cortex-A5
--
allow arml2cc to be used on Cortex-A5 if the "offset" property is specified
--
print "A5" instead of "A9" at attach time if running on a Cortex-A5
--
Improve inline asm around dsb/dmb/isb:
- always use volatile and mark them as memory barrier
- use the common version from locore.h in all places not included from
userland
--
Work-in-progress Odroid-C1 support.
--
no need to override ARM_CBAR, remove unused COM_16750 option
--
Add basic serial console support.
--
add dwctwo and usb devices
--
ODROID-C1 SMP support.
--
auto-detect RAM size
--
ODROID-C1 onboard ethernet support.
--
add amlogicrng, add commented-out genfb placeholder
--
enable amlogicsdhc
--
add ODROID-C1 install kernel
--
Add CPUFREQ option to set boot CPU frequency. ODROID-C1 is advertised
as quad-core 1.5GHz but boots up at 1.2GHz; add CPUFREQ=1512 to config
and make sure to set the correct speed before attaching CPUs.
The speed can still be scaled down with machdep.cpu sysctls.
--
disable DEBUG, LOCKDEBUG, VERBOSE_INIT_ARM
--
Basic framebuffer console support. Work in progress.
|
| 1.17.16.2 |
| 26-Jan-2019 |
pgoyette | Sync with HEAD
|
| 1.17.16.1 |
| 25-Jun-2018 |
pgoyette | Sync with HEAD
|
| 1.18.2.1 |
| 10-Jun-2019 |
christos | Sync with HEAD
|
