pl310.c revision 1.2 1 /* $NetBSD: pl310.c,v 1.2 2012/09/02 16:56:41 matt Exp $ */
2
3 /*-
4 * Copyright (c) 2012 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Matt Thomas
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 #include <sys/cdefs.h>
33 __KERNEL_RCSID(0, "$NetBSD: pl310.c,v 1.2 2012/09/02 16:56:41 matt Exp $");
34
35 #include <sys/param.h>
36 #include <sys/bus.h>
37 #include <sys/cpu.h>
38 #include <sys/device.h>
39
40 #include <arm/cortex/mpcore_var.h>
41 #include <arm/cortex/pl310_reg.h>
42
43 static int arml2cc_match(device_t, cfdata_t, void *);
44 static void arml2cc_attach(device_t, device_t, void *);
45
46 #define L2CC_BASE 0x2000
47 #define L2CC_SIZE 0x1000
48
49 struct arml2cc_softc {
50 device_t sc_dev;
51 bus_space_tag_t sc_memt;
52 bus_space_handle_t sc_memh;
53 };
54
55 CFATTACH_DECL_NEW(arml2cc, sizeof(struct arml2cc_softc),
56 arml2cc_match, arml2cc_attach, NULL, NULL);
57
58 static bool attached;
59
60 static inline uint32_t
61 arml2cc_read_4(struct arml2cc_softc *sc, bus_size_t o)
62 {
63 return bus_space_read_4(sc->sc_memt, sc->sc_memh, o);
64 }
65
66 static inline void
67 arml2cc_write_4(struct arml2cc_softc *sc, bus_size_t o, uint32_t v)
68 {
69 bus_space_write_4(sc->sc_memt, sc->sc_memh, o, v);
70 }
71
72
73 /* ARGSUSED */
74 static int
75 arml2cc_match(device_t parent, cfdata_t cf, void *aux)
76 {
77 struct mpcore_attach_args * const mpcaa = aux;
78
79 if (attached)
80 return 0;
81
82 if (!CPU_ID_CORTEX_A9_P(curcpu()->ci_arm_cpuid))
83 return 0;
84
85 if (strcmp(mpcaa->mpcaa_name, cf->cf_name) != 0)
86 return 0;
87
88 /*
89 * This isn't present on UP A9s (since CBAR isn't present).
90 */
91 uint32_t mpidr = armreg_mpidr_read();
92 if (mpidr == 0 || (mpidr & MPIDR_U))
93 return 0;
94
95 return 1;
96 }
97
98 static const struct {
99 uint8_t rev;
100 uint8_t str[7];
101 } pl310_revs[] = {
102 { 0, " r0p0" },
103 { 2, " r1p0" },
104 { 4, " r2p0" },
105 { 5, " r3p0" },
106 { 6, " r3p1" },
107 { 8, " r3p2" },
108 { 9, " r3p3" },
109 };
110
111 static void
112 arml2cc_attach(device_t parent, device_t self, void *aux)
113 {
114 struct arml2cc_softc * const sc = device_private(self);
115 struct mpcore_attach_args * const mpcaa = aux;
116
117 sc->sc_dev = self;
118 sc->sc_memt = mpcaa->mpcaa_memt;
119
120 bus_space_subregion(sc->sc_memt, mpcaa->mpcaa_memh,
121 L2CC_BASE, L2CC_SIZE, &sc->sc_memh);
122
123 uint32_t id = arml2cc_read_4(sc, L2C_CACHE_ID);
124 u_int rev = __SHIFTOUT(id, CACHE_ID_REV);
125
126 const char *revstr = "";
127 for (size_t i = 0; i < __arraycount(pl310_revs); i++) {
128 if (rev == pl310_revs[i].rev) {
129 revstr = pl310_revs[i].str;
130 break;
131 }
132 }
133
134 aprint_naive("\n");
135 aprint_normal(": ARM PL310 L2%s Cache Controller\n", revstr);
136
137 uint32_t cfg = arml2cc_read_4(sc, L2C_CACHE_TYPE);
138 //u_int cfg_ctype = __SHIFTOUT(cfg, CACHE_TYPE_CTYPE);
139 bool cfg_harvard_p = __SHIFTOUT(cfg, CACHE_TYPE_HARVARD) != 0;
140 u_int cfg_dsize = __SHIFTOUT(cfg, CACHE_TYPE_DSIZE);
141 u_int d_waysize = 8192 << __SHIFTOUT(cfg_dsize, CACHE_TYPE_xWAYSIZE);
142 u_int d_assoc = 8 << __SHIFTOUT(cfg_dsize, CACHE_TYPE_xASSOC);
143 u_int d_linesize = 32 << __SHIFTOUT(cfg_dsize, CACHE_TYPE_xLINESIZE);
144 u_int d_size = d_waysize * d_assoc;
145
146 if (cfg_harvard_p) {
147 u_int cfg_isize = __SHIFTOUT(cfg, CACHE_TYPE_ISIZE);
148 u_int i_waysize = 8192 << __SHIFTOUT(cfg_isize, CACHE_TYPE_xWAYSIZE);
149 u_int i_assoc = 8 << __SHIFTOUT(cfg_isize, CACHE_TYPE_xASSOC);
150 u_int i_linesize = 32 << __SHIFTOUT(cfg_isize, CACHE_TYPE_xLINESIZE);
151 u_int i_size = i_waysize * i_assoc;
152
153 aprint_normal_dev(self, "%uKB/%uB %u-way L2 Instruction cache\n",
154 i_size / 1024, i_linesize, i_assoc);
155 }
156
157 aprint_normal_dev(self, "%uKB/%uB %u-way write-back L2 %s cache\n",
158 d_size / 1024, d_linesize, d_assoc,
159 (cfg_harvard_p ? "Data" : "Unified"));
160 }
161