pl310.c revision 1.5
1 /* $NetBSD: pl310.c,v 1.5 2012/09/14 03:51:01 matt Exp $ */ 2 3 /*- 4 * Copyright (c) 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: pl310.c,v 1.5 2012/09/14 03:51:01 matt Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/bus.h> 37 #include <sys/cpu.h> 38 #include <sys/device.h> 39 #include <sys/atomic.h> 40 41 #include <arm/cortex/mpcore_var.h> 42 #include <arm/cortex/pl310_reg.h> 43 #include <arm/cortex/pl310_var.h> 44 45 static int arml2cc_match(device_t, cfdata_t, void *); 46 static void arml2cc_attach(device_t, device_t, void *); 47 48 #define L2CC_BASE 0x2000 49 #define L2CC_SIZE 0x1000 50 51 struct arml2cc_softc { 52 device_t sc_dev; 53 bus_space_tag_t sc_memt; 54 bus_space_handle_t sc_memh; 55 kmutex_t sc_lock; 56 uint32_t sc_waymask; 57 struct evcnt sc_ev_inv __aligned(8); 58 struct evcnt sc_ev_wb; 59 struct evcnt sc_ev_wbinv; 60 bool sc_enabled; 61 }; 62 63 __CTASSERT(offsetof(struct arml2cc_softc, sc_ev_inv.ev_count) % 8 == 0); 64 __CTASSERT(offsetof(struct arml2cc_softc, sc_ev_wb.ev_count) % 8 == 0); 65 __CTASSERT(offsetof(struct arml2cc_softc, sc_ev_wbinv.ev_count) % 8 == 0); 66 67 CFATTACH_DECL_NEW(arml2cc, sizeof(struct arml2cc_softc), 68 arml2cc_match, arml2cc_attach, NULL, NULL); 69 70 static void arml2cc_disable(struct arml2cc_softc *); 71 static void arml2cc_enable(struct arml2cc_softc *); 72 static void arml2cc_sdcache_wb_range(vaddr_t, paddr_t, psize_t); 73 static void arml2cc_sdcache_inv_range(vaddr_t, paddr_t, psize_t); 74 static void arml2cc_sdcache_wbinv_range(vaddr_t, paddr_t, psize_t); 75 76 static struct arml2cc_softc *arml2cc_sc; 77 78 static inline uint32_t 79 arml2cc_read_4(struct arml2cc_softc *sc, bus_size_t o) 80 { 81 return bus_space_read_4(sc->sc_memt, sc->sc_memh, o); 82 } 83 84 static inline void 85 arml2cc_write_4(struct arml2cc_softc *sc, bus_size_t o, uint32_t v) 86 { 87 bus_space_write_4(sc->sc_memt, sc->sc_memh, o, v); 88 } 89 90 91 /* ARGSUSED */ 92 static int 93 arml2cc_match(device_t parent, cfdata_t cf, void *aux) 94 { 95 struct mpcore_attach_args * const mpcaa = aux; 96 97 if (arml2cc_sc) 98 return 0; 99 100 if (!CPU_ID_CORTEX_A9_P(curcpu()->ci_arm_cpuid)) 101 return 0; 102 103 if (strcmp(mpcaa->mpcaa_name, cf->cf_name) != 0) 104 return 0; 105 106 /* 107 * This isn't present on UP A9s (since CBAR isn't present). 108 */ 109 uint32_t mpidr = armreg_mpidr_read(); 110 if (mpidr == 0 || (mpidr & MPIDR_U)) 111 return 0; 112 113 return 1; 114 } 115 116 static const struct { 117 uint8_t rev; 118 uint8_t str[7]; 119 } pl310_revs[] = { 120 { 0, " r0p0" }, 121 { 2, " r1p0" }, 122 { 4, " r2p0" }, 123 { 5, " r3p0" }, 124 { 6, " r3p1" }, 125 { 8, " r3p2" }, 126 { 9, " r3p3" }, 127 }; 128 129 static void 130 arml2cc_attach(device_t parent, device_t self, void *aux) 131 { 132 struct arml2cc_softc * const sc = device_private(self); 133 struct mpcore_attach_args * const mpcaa = aux; 134 const char * const xname = device_xname(self); 135 136 arml2cc_sc = sc; 137 sc->sc_dev = self; 138 sc->sc_memt = mpcaa->mpcaa_memt; 139 sc->sc_waymask = __BIT(arm_scache.dcache_ways) - 1; 140 141 evcnt_attach_dynamic(&sc->sc_ev_inv, EVCNT_TYPE_MISC, NULL, 142 xname, "L2 inv requests"); 143 evcnt_attach_dynamic(&sc->sc_ev_wb, EVCNT_TYPE_MISC, NULL, 144 xname, "L2 wb requests"); 145 evcnt_attach_dynamic(&sc->sc_ev_wbinv, EVCNT_TYPE_MISC, NULL, 146 xname, "L2 wbinv requests"); 147 148 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_HIGH); 149 150 bus_space_subregion(sc->sc_memt, mpcaa->mpcaa_memh, 151 L2CC_BASE, L2CC_SIZE, &sc->sc_memh); 152 153 uint32_t id = arml2cc_read_4(sc, L2C_CACHE_ID); 154 u_int rev = __SHIFTOUT(id, CACHE_ID_REV); 155 156 const char *revstr = ""; 157 for (size_t i = 0; i < __arraycount(pl310_revs); i++) { 158 if (rev == pl310_revs[i].rev) { 159 revstr = pl310_revs[i].str; 160 break; 161 } 162 } 163 164 const bool enabled_p = arml2cc_read_4(sc, L2C_CTL) != 0; 165 166 aprint_naive("\n"); 167 aprint_normal(": ARM PL310%s L2 Cache Controller%s\n", 168 revstr, enabled_p ? "" : " (disabled)"); 169 170 #if 1 171 if (enabled_p) { 172 if (1) { 173 arml2cc_disable(sc); 174 aprint_normal_dev(self, "cache %s\n", 175 arml2cc_read_4(sc, L2C_CTL) ? "enabled" : "disabled"); 176 sc->sc_enabled = false; 177 } else { 178 cpufuncs.cf_sdcache_wb_range = arml2cc_sdcache_wb_range; 179 cpufuncs.cf_sdcache_inv_range = arml2cc_sdcache_inv_range; 180 cpufuncs.cf_sdcache_wbinv_range = arml2cc_sdcache_wbinv_range; 181 sc->sc_enabled = true; 182 } 183 } 184 #else 185 if (!enabled_p) { 186 arml2cc_enable(sc); 187 aprint_normal_dev(self, "cache %s\n", 188 arml2cc_read_4(sc, L2C_CTL) ? "enabled" : "disabled"); 189 } 190 cpufuncs.cf_sdcache_wb_range = arml2cc_sdcache_wb_range; 191 cpufuncs.cf_sdcache_inv_range = arml2cc_sdcache_inv_range; 192 cpufuncs.cf_sdcache_wbinv_range = arml2cc_sdcache_wbinv_range; 193 sc->sc_enabled = true; 194 #endif 195 196 KASSERT(arm_pcache.dcache_line_size == arm_scache.dcache_line_size); 197 } 198 199 static inline void 200 arml2cc_cache_op(struct arml2cc_softc *sc, bus_size_t off, uint32_t val) 201 { 202 arml2cc_write_4(sc, off, val); 203 while (arml2cc_read_4(sc, off) & 1) { 204 /* spin */ 205 } 206 } 207 208 static inline void 209 arml2cc_cache_way_op(struct arml2cc_softc *sc, bus_size_t off, uint32_t way_mask) 210 { 211 arml2cc_write_4(sc, off, way_mask); 212 while (arml2cc_read_4(sc, off) & way_mask) { 213 /* spin */ 214 } 215 } 216 217 static inline void 218 arml2cc_cache_sync(struct arml2cc_softc *sc) 219 { 220 arml2cc_cache_op(sc, L2C_CACHE_SYNC, 0); 221 } 222 223 static inline void 224 arml2cc_disable(struct arml2cc_softc *sc) 225 { 226 mutex_spin_enter(&sc->sc_lock); 227 228 arml2cc_cache_way_op(sc, L2C_CLEAN_INV_WAY, sc->sc_waymask); 229 arml2cc_cache_sync(sc); 230 231 arml2cc_write_4(sc, L2C_CTL, 0); // turn it off 232 mutex_spin_exit(&sc->sc_lock); 233 } 234 235 static inline void 236 arml2cc_enable(struct arml2cc_softc *sc) 237 { 238 mutex_spin_enter(&sc->sc_lock); 239 240 arml2cc_write_4(sc, L2C_CTL, 1); // turn it on 241 242 //arml2cc_cache_way_op(sc, L2C_INV_WAY, sc->sc_waymask); 243 arml2cc_cache_sync(sc); 244 245 mutex_spin_exit(&sc->sc_lock); 246 } 247 248 void 249 arml2cc_init(bus_space_tag_t bst, bus_space_handle_t bsh, bus_size_t o) 250 { 251 struct arm_cache_info * const info = &arm_scache; 252 253 uint32_t cfg = bus_space_read_4(bst, bsh, o + L2C_CACHE_TYPE); 254 255 info->cache_type = __SHIFTOUT(cfg, CACHE_TYPE_CTYPE); 256 info->cache_unified = __SHIFTOUT(cfg, CACHE_TYPE_HARVARD) == 0; 257 u_int cfg_dsize = __SHIFTOUT(cfg, CACHE_TYPE_DSIZE); 258 259 u_int d_waysize = 8192 << __SHIFTOUT(cfg_dsize, CACHE_TYPE_xWAYSIZE); 260 info->dcache_ways = 8 << __SHIFTOUT(cfg_dsize, CACHE_TYPE_xASSOC); 261 info->dcache_line_size = 32 << __SHIFTOUT(cfg_dsize, CACHE_TYPE_xLINESIZE); 262 info->dcache_size = info->dcache_ways * d_waysize; 263 264 if (info->cache_unified) { 265 info->icache_ways = info->dcache_ways; 266 info->icache_line_size = info->dcache_line_size; 267 info->icache_size = info->dcache_size; 268 } else { 269 u_int cfg_isize = __SHIFTOUT(cfg, CACHE_TYPE_ISIZE); 270 u_int i_waysize = 8192 << __SHIFTOUT(cfg_isize, CACHE_TYPE_xWAYSIZE); 271 info->icache_ways = 8 << __SHIFTOUT(cfg_isize, CACHE_TYPE_xASSOC); 272 info->icache_line_size = 32 << __SHIFTOUT(cfg_isize, CACHE_TYPE_xLINESIZE); 273 info->icache_size = i_waysize * info->icache_ways; 274 } 275 } 276 277 static void 278 arml2cc_cache_range_op(paddr_t pa, psize_t len, bus_size_t cache_op) 279 { 280 struct arml2cc_softc * const sc = arml2cc_sc; 281 const size_t line_size = arm_scache.dcache_line_size; 282 const size_t line_mask = line_size - 1; 283 size_t off = pa & line_mask; 284 if (off) { 285 len += off; 286 pa -= off; 287 } 288 len = roundup2(len, line_size); 289 off = pa & PAGE_MASK; 290 for (const paddr_t endpa = pa + len; pa < endpa; off = 0) { 291 psize_t seglen = min(len, PAGE_SIZE - off); 292 293 mutex_spin_enter(&sc->sc_lock); 294 if (!sc->sc_enabled) 295 return; 296 for (paddr_t segend = pa + seglen; pa < segend; pa += line_size) { 297 arml2cc_cache_op(sc, cache_op, pa); 298 } 299 mutex_spin_exit(&sc->sc_lock); 300 } 301 } 302 303 static void 304 arml2cc_sdcache_inv_range(vaddr_t va, paddr_t pa, psize_t len) 305 { 306 atomic_inc_64(&arml2cc_sc->sc_ev_inv.ev_count); 307 arml2cc_cache_range_op(pa, len, L2C_INV_PA); 308 } 309 310 static void 311 arml2cc_sdcache_wb_range(vaddr_t va, paddr_t pa, psize_t len) 312 { 313 atomic_inc_64(&arml2cc_sc->sc_ev_wb.ev_count); 314 arml2cc_cache_range_op(pa, len, L2C_CLEAN_PA); 315 } 316 317 static void 318 arml2cc_sdcache_wbinv_range(vaddr_t va, paddr_t pa, psize_t len) 319 { 320 atomic_inc_64(&arml2cc_sc->sc_ev_wbinv.ev_count); 321 arml2cc_cache_range_op(pa, len, L2C_CLEAN_INV_PA); 322 } 323
Indexes created Wed Oct 01 19:09:53 GMT 2025