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      3 #include "../../../external/gpl2/dts/dist/arch/arm/boot/dts/socfpga_cyclone5_de0_nano_soc.dts"
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      5 / {
      6 	soc {
      7 		timer@fffec600 {
      8 			status = "disabled";
      9 		};
     10 
     11 		gtimer@fffec200 {
     12 			compatible = "arm,cortex-a9-global-timer";
     13 			reg = <0xfffec200 0x20>;
     14 			clocks = <&mpu_periph_clk>;
     15 			interrupts = <1 11 0x301>;
     16 		};
     17 		usb@ffb40000 {
     18 			dr_mode = "host";
     19 		};
     20 		watchdog@ffd02000 {
     21 			resets = <&rst L4WD0_RESET>;
     22 		};
     23 	};
     24 };
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