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      1 /*	$NetBSD: epsmcreg.h,v 1.1 2005/11/12 05:33:23 hamajima Exp $	*/
      2 
      3 /*
      4  * Copyright (c) 2005 HAMAJIMA Katsuomi. All rights reserved.
      5  *
      6  * Redistribution and use in source and binary forms, with or without
      7  * modification, are permitted provided that the following conditions
      8  * are met:
      9  * 1. Redistributions of source code must retain the above copyright
     10  *    notice, this list of conditions and the following disclaimer.
     11  * 2. Redistributions in binary form must reproduce the above copyright
     12  *    notice, this list of conditions and the following disclaimer in the
     13  *    documentation and/or other materials provided with the distribution.
     14  *
     15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
     16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
     19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     25  * SUCH DAMAGE.
     26  */
     27 
     28 /*	Cirrus Logic EP9315
     29 	Static Memory Controller register
     30 	http://www.cirrus.com/jp/pubs/manual/EP9315_Users_Guide.pdf	*/
     31 
     32 #ifndef	_EPSMCREG_H_
     33 #define	_EPSMCREG_H_
     34 
     35 #define	EP93XX_SMC_BCR0		0x00	/* Bank0 Configuration Register (R/W) */
     36 #define	EP93XX_SMC_BCR1		0x04	/* Bank1 Configuration Register (R/W) */
     37 #define	EP93XX_SMC_BCR2		0x08	/* Bank2 Configuration Register (R/W) */
     38 #define	EP93XX_SMC_BCR3		0x0c	/* Bank3 Configuration Register (R/W) */
     39 #define	EP93XX_SMC_BCR6		0x18	/* Bank6 Configuration Register (R/W) */
     40 #define	EP93XX_SMC_BCR7		0x1c	/* Bank7 Configuration Register (R/W) */
     41 #define	 EP93XX_SMC_IDCY_MASK		0x0000000f	/* Idle Cycle */
     42 #define	 EP93XX_SMC_IDCY_SHIFT		0
     43 #define	 EP93XX_SMC_WST1_MASK		0x000003e0	/* Wait State 1 */
     44 #define	 EP93XX_SMC_WST1_SHIFT		5
     45 #define	 EP93XX_SMC_RBLE		(1<<10)		/* Read Byte Lane Enable */
     46 #define	 EP93XX_SMC_WST2_MASK		0x0000f800	/* Wait State 2 */
     47 #define	 EP93XX_SMC_WST2_SHIFT		11
     48 #define	 EP93XX_SMC_WPERR		(1<<25)		/* Write Protect Error status */
     49 #define	 EP93XX_SMC_WP			(1<<26)		/* Write Protect */
     50 #define	 EP93XX_SMC_PME			(1<<27)		/* Page Mode Enable */
     51 #define	 EP93XX_SMC_MW_MASK		0x30000000	/* Memory Width */
     52 #define	 EP93XX_SMC_MW_SHIFT		28
     53 #define	 EP93XX_SMC_EBIBRKDIS		(1<<30)		/* EBI Break Disable */
     54 
     55 #define	EP93XX_PCMCIA0_Attribute 0x20	/* PCMCIA Attribute (R/W) */
     56 #define	EP93XX_PCMCIA0_Common	0x24	/* PCMCIA Common (R/W) */
     57 #define	EP93XX_PCMCIA0_IO	0x28	/* PCMCIA IO (R/W) */
     58 #define	EP93XX_PCMCIA1_Attribute 0x30	/* PCMCIA Attribute (R/W) */
     59 #define	EP93XX_PCMCIA1_Common	0x34	/* PCMCIA Common (R/W) */
     60 #define	EP93XX_PCMCIA1_IO	0x38	/* PCMCIA IO (R/W) */
     61 #define	 EP93XX_PCMCIA_WIDTH_16		(1<<31)		/* width */
     62 #define	 EP93XX_PCMCIA_ACCESS_MASK	0x00ff0000	/* access time */
     63 #define	 EP93XX_PCMCIA_ACCESS_SHIFT	16
     64 #define	 EP93XX_PCMCIA_HOLD_MASK	0x00000f00	/* Hole time */
     65 #define	 EP93XX_PCMCIA_HOLD_SHIFT	8
     66 #define	 EP93XX_PCMCIA_PRECHARGE_MASK	0x000000ff	/* pre-charge delay */
     67 #define	 EP93XX_PCMCIA_PRECHARGE_SHIFT	0
     68 
     69 #define	EP93XX_PCMCIA_Ctrl	0x40	/* PCMCIA Control */
     70 #define	 EP93XX_PCMCIA_WEN		(1<<4)		/* External wait state */
     71 #define	 EP93XX_PCMCIA_RST		(1<<2)		/* Reset PC card */
     72 #define	 EP93XX_PCMCIA_EN_DISABLE	0x0		/* PC card disabled */
     73 #define	 EP93XX_PCMCIA_EN_CF		0x1		/* CF mode */
     74 #define	 EP93XX_PCMCIA_EN_PCMCIA	0x2		/* PCMCIA mode */
     75 #define	 EP93XX_PCMCIA_EN_MASK		0x3
     76 
     77 #endif	/* _EPSMCREG_H_ */
     78