1 1.16 jmcneill /* $NetBSD: gicv3_fdt.c,v 1.16 2021/11/17 21:46:12 jmcneill Exp $ */ 2 1.1 jmcneill 3 1.1 jmcneill /*- 4 1.1 jmcneill * Copyright (c) 2015-2018 Jared McNeill <jmcneill (at) invisible.ca> 5 1.1 jmcneill * All rights reserved. 6 1.1 jmcneill * 7 1.1 jmcneill * Redistribution and use in source and binary forms, with or without 8 1.1 jmcneill * modification, are permitted provided that the following conditions 9 1.1 jmcneill * are met: 10 1.1 jmcneill * 1. Redistributions of source code must retain the above copyright 11 1.1 jmcneill * notice, this list of conditions and the following disclaimer. 12 1.1 jmcneill * 2. Redistributions in binary form must reproduce the above copyright 13 1.1 jmcneill * notice, this list of conditions and the following disclaimer in the 14 1.1 jmcneill * documentation and/or other materials provided with the distribution. 15 1.1 jmcneill * 16 1.1 jmcneill * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 1.1 jmcneill * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 1.1 jmcneill * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 1.1 jmcneill * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 1.1 jmcneill * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 1.1 jmcneill * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 1.1 jmcneill * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 1.1 jmcneill * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 1.1 jmcneill * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 1.1 jmcneill * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 1.1 jmcneill * SUCH DAMAGE. 27 1.1 jmcneill */ 28 1.1 jmcneill 29 1.6 jakllsch #include "pci.h" 30 1.6 jakllsch 31 1.1 jmcneill #define _INTR_PRIVATE 32 1.1 jmcneill 33 1.1 jmcneill #include <sys/cdefs.h> 34 1.16 jmcneill __KERNEL_RCSID(0, "$NetBSD: gicv3_fdt.c,v 1.16 2021/11/17 21:46:12 jmcneill Exp $"); 35 1.1 jmcneill 36 1.1 jmcneill #include <sys/param.h> 37 1.1 jmcneill #include <sys/bus.h> 38 1.1 jmcneill #include <sys/device.h> 39 1.1 jmcneill #include <sys/intr.h> 40 1.1 jmcneill #include <sys/systm.h> 41 1.1 jmcneill #include <sys/kernel.h> 42 1.1 jmcneill #include <sys/lwp.h> 43 1.1 jmcneill #include <sys/kmem.h> 44 1.1 jmcneill #include <sys/queue.h> 45 1.1 jmcneill 46 1.1 jmcneill #include <dev/fdt/fdtvar.h> 47 1.1 jmcneill 48 1.1 jmcneill #include <arm/cortex/gicv3.h> 49 1.6 jakllsch #include <arm/cortex/gicv3_its.h> 50 1.3 jmcneill #include <arm/cortex/gic_reg.h> 51 1.10 jmcneill #include <arm/cortex/gic_v2m.h> 52 1.1 jmcneill 53 1.1 jmcneill #define GICV3_MAXIRQ 1020 54 1.1 jmcneill 55 1.1 jmcneill #define IRQ_PPI(n) ((n) + 16) 56 1.1 jmcneill #define IRQ_SPI(n) ((n) + 32) 57 1.1 jmcneill 58 1.1 jmcneill struct gicv3_fdt_softc; 59 1.1 jmcneill struct gicv3_fdt_irq; 60 1.1 jmcneill 61 1.1 jmcneill static int gicv3_fdt_match(device_t, cfdata_t, void *); 62 1.1 jmcneill static void gicv3_fdt_attach(device_t, device_t, void *); 63 1.1 jmcneill 64 1.1 jmcneill static int gicv3_fdt_map_registers(struct gicv3_fdt_softc *); 65 1.8 hkenken #if NPCI > 0 && defined(__HAVE_PCI_MSI_MSIX) 66 1.10 jmcneill static void gicv3_fdt_attach_mbi(struct gicv3_fdt_softc *); 67 1.6 jakllsch static void gicv3_fdt_attach_its(struct gicv3_fdt_softc *, bus_space_tag_t, int); 68 1.6 jakllsch #endif 69 1.1 jmcneill 70 1.1 jmcneill static int gicv3_fdt_intr(void *); 71 1.1 jmcneill 72 1.1 jmcneill static void * gicv3_fdt_establish(device_t, u_int *, int, int, 73 1.11 jmcneill int (*)(void *), void *, const char *); 74 1.1 jmcneill static void gicv3_fdt_disestablish(device_t, void *); 75 1.1 jmcneill static bool gicv3_fdt_intrstr(device_t, u_int *, char *, size_t); 76 1.1 jmcneill 77 1.1 jmcneill struct fdtbus_interrupt_controller_func gicv3_fdt_funcs = { 78 1.1 jmcneill .establish = gicv3_fdt_establish, 79 1.1 jmcneill .disestablish = gicv3_fdt_disestablish, 80 1.1 jmcneill .intrstr = gicv3_fdt_intrstr 81 1.1 jmcneill }; 82 1.1 jmcneill 83 1.1 jmcneill struct gicv3_fdt_irqhandler { 84 1.1 jmcneill struct gicv3_fdt_irq *ih_irq; 85 1.1 jmcneill int (*ih_fn)(void *); 86 1.1 jmcneill void *ih_arg; 87 1.1 jmcneill bool ih_mpsafe; 88 1.1 jmcneill TAILQ_ENTRY(gicv3_fdt_irqhandler) ih_next; 89 1.1 jmcneill }; 90 1.1 jmcneill 91 1.1 jmcneill struct gicv3_fdt_irq { 92 1.1 jmcneill struct gicv3_fdt_softc *intr_sc; 93 1.1 jmcneill void *intr_ih; 94 1.1 jmcneill void *intr_arg; 95 1.1 jmcneill int intr_refcnt; 96 1.1 jmcneill int intr_ipl; 97 1.1 jmcneill int intr_level; 98 1.1 jmcneill int intr_mpsafe; 99 1.1 jmcneill TAILQ_HEAD(, gicv3_fdt_irqhandler) intr_handlers; 100 1.1 jmcneill int intr_irq; 101 1.1 jmcneill }; 102 1.1 jmcneill 103 1.1 jmcneill struct gicv3_fdt_softc { 104 1.1 jmcneill struct gicv3_softc sc_gic; 105 1.1 jmcneill int sc_phandle; 106 1.1 jmcneill 107 1.1 jmcneill struct gicv3_fdt_irq *sc_irq[GICV3_MAXIRQ]; 108 1.1 jmcneill }; 109 1.1 jmcneill 110 1.12 thorpej static const struct device_compatible_entry gicv3_fdt_quirks[] = { 111 1.12 thorpej { .compat = "rockchip,rk3399", .value = GICV3_QUIRK_RK3399 }, 112 1.14 thorpej DEVICE_COMPAT_EOL 113 1.9 jmcneill }; 114 1.9 jmcneill 115 1.1 jmcneill CFATTACH_DECL_NEW(gicv3_fdt, sizeof(struct gicv3_fdt_softc), 116 1.1 jmcneill gicv3_fdt_match, gicv3_fdt_attach, NULL, NULL); 117 1.1 jmcneill 118 1.12 thorpej static const struct device_compatible_entry compat_data[] = { 119 1.12 thorpej { .compat = "arm,gic-v3" }, 120 1.14 thorpej DEVICE_COMPAT_EOL 121 1.12 thorpej }; 122 1.12 thorpej 123 1.1 jmcneill static int 124 1.1 jmcneill gicv3_fdt_match(device_t parent, cfdata_t cf, void *aux) 125 1.1 jmcneill { 126 1.1 jmcneill struct fdt_attach_args * const faa = aux; 127 1.1 jmcneill const int phandle = faa->faa_phandle; 128 1.1 jmcneill 129 1.15 thorpej return of_compatible_match(phandle, compat_data); 130 1.1 jmcneill } 131 1.1 jmcneill 132 1.1 jmcneill static void 133 1.1 jmcneill gicv3_fdt_attach(device_t parent, device_t self, void *aux) 134 1.1 jmcneill { 135 1.1 jmcneill struct gicv3_fdt_softc * const sc = device_private(self); 136 1.1 jmcneill struct fdt_attach_args * const faa = aux; 137 1.1 jmcneill const int phandle = faa->faa_phandle; 138 1.12 thorpej int error; 139 1.1 jmcneill 140 1.1 jmcneill error = fdtbus_register_interrupt_controller(self, phandle, 141 1.1 jmcneill &gicv3_fdt_funcs); 142 1.1 jmcneill if (error) { 143 1.1 jmcneill aprint_error(": couldn't register with fdtbus: %d\n", error); 144 1.1 jmcneill return; 145 1.1 jmcneill } 146 1.1 jmcneill 147 1.1 jmcneill aprint_naive("\n"); 148 1.1 jmcneill aprint_normal(": GICv3\n"); 149 1.1 jmcneill 150 1.1 jmcneill sc->sc_phandle = phandle; 151 1.1 jmcneill sc->sc_gic.sc_dev = self; 152 1.1 jmcneill sc->sc_gic.sc_bst = faa->faa_bst; 153 1.4 jmcneill sc->sc_gic.sc_dmat = faa->faa_dmat; 154 1.1 jmcneill 155 1.1 jmcneill error = gicv3_fdt_map_registers(sc); 156 1.1 jmcneill if (error) { 157 1.1 jmcneill aprint_error_dev(self, "couldn't map registers\n"); 158 1.1 jmcneill return; 159 1.1 jmcneill } 160 1.1 jmcneill 161 1.2 jmcneill aprint_debug_dev(self, "%d redistributors\n", sc->sc_gic.sc_bsh_r_count); 162 1.1 jmcneill 163 1.9 jmcneill /* Apply quirks */ 164 1.12 thorpej const struct device_compatible_entry *dce = 165 1.15 thorpej of_compatible_lookup(OF_finddevice("/"), gicv3_fdt_quirks); 166 1.12 thorpej if (dce != NULL) { 167 1.12 thorpej sc->sc_gic.sc_quirks |= dce->value; 168 1.9 jmcneill } 169 1.9 jmcneill 170 1.1 jmcneill error = gicv3_init(&sc->sc_gic); 171 1.1 jmcneill if (error) { 172 1.1 jmcneill aprint_error_dev(self, "failed to initialize GIC: %d\n", error); 173 1.1 jmcneill return; 174 1.1 jmcneill } 175 1.1 jmcneill 176 1.8 hkenken #if NPCI > 0 && defined(__HAVE_PCI_MSI_MSIX) 177 1.10 jmcneill if (of_hasprop(phandle, "msi-controller")) { 178 1.10 jmcneill /* Message Based Interrupts */ 179 1.10 jmcneill gicv3_fdt_attach_mbi(sc); 180 1.10 jmcneill } else { 181 1.10 jmcneill /* Interrupt Translation Services */ 182 1.12 thorpej static const struct device_compatible_entry its_compat[] = { 183 1.12 thorpej { .compat = "arm,gic-v3-its" }, 184 1.14 thorpej DEVICE_COMPAT_EOL 185 1.12 thorpej }; 186 1.12 thorpej 187 1.12 thorpej for (int child = OF_child(phandle); child; 188 1.12 thorpej child = OF_peer(child)) { 189 1.10 jmcneill if (!fdtbus_status_okay(child)) 190 1.10 jmcneill continue; 191 1.15 thorpej if (of_compatible_match(child, its_compat)) 192 1.10 jmcneill gicv3_fdt_attach_its(sc, faa->faa_bst, child); 193 1.10 jmcneill } 194 1.6 jakllsch } 195 1.6 jakllsch #endif 196 1.6 jakllsch 197 1.1 jmcneill arm_fdt_irq_set_handler(gicv3_irq_handler); 198 1.1 jmcneill } 199 1.1 jmcneill 200 1.1 jmcneill static int 201 1.1 jmcneill gicv3_fdt_map_registers(struct gicv3_fdt_softc *sc) 202 1.1 jmcneill { 203 1.1 jmcneill struct gicv3_softc *gic = &sc->sc_gic; 204 1.1 jmcneill const int phandle = sc->sc_phandle; 205 1.1 jmcneill u_int redistributor_regions, redistributor_stride; 206 1.1 jmcneill bus_space_handle_t bsh; 207 1.1 jmcneill bus_size_t size, region_off; 208 1.1 jmcneill bus_addr_t addr; 209 1.1 jmcneill size_t reg_off; 210 1.3 jmcneill int n, r, max_redist, redist; 211 1.1 jmcneill 212 1.1 jmcneill if (of_getprop_uint32(phandle, "#redistributor-regions", &redistributor_regions)) 213 1.1 jmcneill redistributor_regions = 1; 214 1.1 jmcneill if (of_getprop_uint32(phandle, "redistributor-stride", &redistributor_stride)) 215 1.1 jmcneill redistributor_stride = 0x20000; 216 1.1 jmcneill 217 1.1 jmcneill /* 218 1.1 jmcneill * Map GIC Distributor interface (GICD) 219 1.1 jmcneill */ 220 1.1 jmcneill if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 221 1.1 jmcneill aprint_error_dev(gic->sc_dev, "couldn't get distributor registers\n"); 222 1.1 jmcneill return ENXIO; 223 1.1 jmcneill } 224 1.1 jmcneill if (bus_space_map(sc->sc_gic.sc_bst, addr, size, 0, &sc->sc_gic.sc_bsh_d) != 0) { 225 1.1 jmcneill aprint_error_dev(gic->sc_dev, "couldn't map distributor registers\n"); 226 1.1 jmcneill return ENXIO; 227 1.1 jmcneill } 228 1.1 jmcneill 229 1.1 jmcneill /* 230 1.1 jmcneill * GIC Redistributors (GICR) 231 1.1 jmcneill */ 232 1.3 jmcneill for (reg_off = 1, max_redist = 0, n = 0; n < redistributor_regions; n++, reg_off++) { 233 1.1 jmcneill if (fdtbus_get_reg(phandle, reg_off, NULL, &size) != 0) { 234 1.1 jmcneill aprint_error_dev(gic->sc_dev, "couldn't get redistributor registers\n"); 235 1.1 jmcneill return ENXIO; 236 1.1 jmcneill } 237 1.3 jmcneill max_redist += howmany(size, redistributor_stride); 238 1.1 jmcneill } 239 1.3 jmcneill gic->sc_bsh_r = kmem_alloc(sizeof(bus_space_handle_t) * max_redist, KM_SLEEP); 240 1.3 jmcneill for (reg_off = 1, redist = 0, n = 0; n < redistributor_regions; n++, reg_off++) { 241 1.1 jmcneill if (fdtbus_get_reg(phandle, reg_off, &addr, &size) != 0) { 242 1.1 jmcneill aprint_error_dev(gic->sc_dev, "couldn't get redistributor registers\n"); 243 1.1 jmcneill return ENXIO; 244 1.1 jmcneill } 245 1.1 jmcneill if (bus_space_map(sc->sc_gic.sc_bst, addr, size, 0, &bsh) != 0) { 246 1.1 jmcneill aprint_error_dev(gic->sc_dev, "couldn't map redistributor registers\n"); 247 1.1 jmcneill return ENXIO; 248 1.1 jmcneill } 249 1.1 jmcneill const int count = howmany(size, redistributor_stride); 250 1.1 jmcneill for (r = 0, region_off = 0; r < count; r++, region_off += redistributor_stride) { 251 1.3 jmcneill if (bus_space_subregion(sc->sc_gic.sc_bst, bsh, region_off, redistributor_stride, &gic->sc_bsh_r[redist++]) != 0) { 252 1.1 jmcneill aprint_error_dev(gic->sc_dev, "couldn't subregion redistributor registers\n"); 253 1.1 jmcneill return ENXIO; 254 1.1 jmcneill } 255 1.3 jmcneill 256 1.3 jmcneill /* If this is the last redist in this region, skip to the next one */ 257 1.3 jmcneill const uint32_t typer = bus_space_read_4(sc->sc_gic.sc_bst, gic->sc_bsh_r[redist - 1], GICR_TYPER); 258 1.3 jmcneill if (typer & GICR_TYPER_Last) 259 1.3 jmcneill break; 260 1.1 jmcneill } 261 1.1 jmcneill } 262 1.3 jmcneill gic->sc_bsh_r_count = redist; 263 1.1 jmcneill 264 1.1 jmcneill return 0; 265 1.1 jmcneill } 266 1.1 jmcneill 267 1.8 hkenken #if NPCI > 0 && defined(__HAVE_PCI_MSI_MSIX) 268 1.6 jakllsch static void 269 1.10 jmcneill gicv3_fdt_attach_mbi(struct gicv3_fdt_softc *sc) 270 1.10 jmcneill { 271 1.10 jmcneill struct gic_v2m_frame *frame; 272 1.10 jmcneill const u_int *ranges; 273 1.10 jmcneill bus_addr_t addr; 274 1.10 jmcneill int len, frame_count; 275 1.10 jmcneill 276 1.16 jmcneill /* 277 1.16 jmcneill * If a GICD alias frame containing only the SET/CLRSPI registers 278 1.16 jmcneill * exists, the base address will be reported by the 'mbi-alias' 279 1.16 jmcneill * property. If this doesn't exist, use the GICD register frame 280 1.16 jmcneill * instead. 281 1.16 jmcneill */ 282 1.16 jmcneill if (of_getprop_uint64(sc->sc_phandle, "mbi-alias", &addr) != 0 && 283 1.16 jmcneill fdtbus_get_reg(sc->sc_phandle, 0, &addr, NULL) != 0) { 284 1.16 jmcneill aprint_error_dev(sc->sc_gic.sc_dev, "couldn't find MBI register frame\n"); 285 1.10 jmcneill return; 286 1.10 jmcneill } 287 1.10 jmcneill 288 1.10 jmcneill ranges = fdtbus_get_prop(sc->sc_phandle, "mbi-ranges", &len); 289 1.10 jmcneill if (ranges == NULL) { 290 1.10 jmcneill aprint_error_dev(sc->sc_gic.sc_dev, "missing 'mbi-ranges' property\n"); 291 1.10 jmcneill return; 292 1.10 jmcneill } 293 1.10 jmcneill 294 1.10 jmcneill frame_count = 0; 295 1.10 jmcneill while (len >= 8) { 296 1.10 jmcneill const u_int base_spi = be32dec(&ranges[0]); 297 1.10 jmcneill const u_int num_spis = be32dec(&ranges[1]); 298 1.10 jmcneill 299 1.10 jmcneill frame = kmem_zalloc(sizeof(*frame), KM_SLEEP); 300 1.10 jmcneill frame->frame_reg = addr; 301 1.10 jmcneill frame->frame_pic = pic_list[0]; 302 1.10 jmcneill frame->frame_base = base_spi; 303 1.10 jmcneill frame->frame_count = num_spis; 304 1.10 jmcneill 305 1.10 jmcneill if (gic_v2m_init(frame, sc->sc_gic.sc_dev, frame_count++) != 0) { 306 1.10 jmcneill aprint_error_dev(sc->sc_gic.sc_dev, "failed to initialize MBI frame\n"); 307 1.10 jmcneill } else { 308 1.10 jmcneill aprint_normal_dev(sc->sc_gic.sc_dev, "MBI frame @ %#" PRIx64 309 1.10 jmcneill ", SPIs %u-%u\n", frame->frame_reg, 310 1.10 jmcneill frame->frame_base, frame->frame_base + frame->frame_count - 1); 311 1.10 jmcneill } 312 1.10 jmcneill 313 1.10 jmcneill ranges += 2; 314 1.10 jmcneill len -= 8; 315 1.10 jmcneill } 316 1.10 jmcneill } 317 1.10 jmcneill 318 1.10 jmcneill static void 319 1.6 jakllsch gicv3_fdt_attach_its(struct gicv3_fdt_softc *sc, bus_space_tag_t bst, int phandle) 320 1.6 jakllsch { 321 1.6 jakllsch bus_space_handle_t bsh; 322 1.6 jakllsch bus_addr_t addr; 323 1.6 jakllsch bus_size_t size; 324 1.6 jakllsch 325 1.6 jakllsch if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 326 1.6 jakllsch aprint_error_dev(sc->sc_gic.sc_dev, "couldn't get ITS address\n"); 327 1.6 jakllsch return; 328 1.6 jakllsch } 329 1.6 jakllsch 330 1.6 jakllsch if (bus_space_map(bst, addr, size, 0, &bsh) != 0) { 331 1.6 jakllsch aprint_error_dev(sc->sc_gic.sc_dev, "couldn't map ITS\n"); 332 1.6 jakllsch return; 333 1.6 jakllsch } 334 1.6 jakllsch 335 1.6 jakllsch gicv3_its_init(&sc->sc_gic, bsh, addr, 0); 336 1.6 jakllsch 337 1.6 jakllsch aprint_verbose_dev(sc->sc_gic.sc_dev, "ITS @ %#" PRIxBUSADDR "\n", 338 1.6 jakllsch addr); 339 1.6 jakllsch } 340 1.6 jakllsch #endif 341 1.6 jakllsch 342 1.1 jmcneill static void * 343 1.1 jmcneill gicv3_fdt_establish(device_t dev, u_int *specifier, int ipl, int flags, 344 1.11 jmcneill int (*func)(void *), void *arg, const char *xname) 345 1.1 jmcneill { 346 1.1 jmcneill struct gicv3_fdt_softc * const sc = device_private(dev); 347 1.1 jmcneill struct gicv3_fdt_irq *firq; 348 1.1 jmcneill struct gicv3_fdt_irqhandler *firqh; 349 1.1 jmcneill 350 1.1 jmcneill /* 1st cell is the interrupt type; 0 is SPI, 1 is PPI */ 351 1.1 jmcneill /* 2nd cell is the interrupt number */ 352 1.1 jmcneill /* 3rd cell is flags */ 353 1.1 jmcneill /* 4th cell is affinity */ 354 1.1 jmcneill 355 1.1 jmcneill const u_int type = be32toh(specifier[0]); 356 1.1 jmcneill const u_int intr = be32toh(specifier[1]); 357 1.1 jmcneill const u_int irq = type == 0 ? IRQ_SPI(intr) : IRQ_PPI(intr); 358 1.1 jmcneill const u_int trig = be32toh(specifier[2]) & 0xf; 359 1.7 thorpej const u_int level = (trig & FDT_INTR_TYPE_DOUBLE_EDGE) 360 1.7 thorpej ? IST_EDGE : IST_LEVEL; 361 1.1 jmcneill 362 1.1 jmcneill const u_int mpsafe = (flags & FDT_INTR_MPSAFE) ? IST_MPSAFE : 0; 363 1.1 jmcneill 364 1.1 jmcneill firq = sc->sc_irq[irq]; 365 1.1 jmcneill if (firq == NULL) { 366 1.1 jmcneill firq = kmem_alloc(sizeof(*firq), KM_SLEEP); 367 1.1 jmcneill firq->intr_sc = sc; 368 1.1 jmcneill firq->intr_refcnt = 0; 369 1.1 jmcneill firq->intr_arg = arg; 370 1.1 jmcneill firq->intr_ipl = ipl; 371 1.1 jmcneill firq->intr_level = level; 372 1.1 jmcneill firq->intr_mpsafe = mpsafe; 373 1.1 jmcneill TAILQ_INIT(&firq->intr_handlers); 374 1.1 jmcneill firq->intr_irq = irq; 375 1.1 jmcneill if (arg == NULL) { 376 1.11 jmcneill firq->intr_ih = intr_establish_xname(irq, ipl, 377 1.11 jmcneill level | mpsafe, func, NULL, xname); 378 1.1 jmcneill } else { 379 1.11 jmcneill firq->intr_ih = intr_establish_xname(irq, ipl, 380 1.11 jmcneill level | mpsafe, gicv3_fdt_intr, firq, xname); 381 1.1 jmcneill } 382 1.1 jmcneill if (firq->intr_ih == NULL) { 383 1.1 jmcneill kmem_free(firq, sizeof(*firq)); 384 1.1 jmcneill return NULL; 385 1.1 jmcneill } 386 1.1 jmcneill sc->sc_irq[irq] = firq; 387 1.1 jmcneill } else { 388 1.1 jmcneill if (firq->intr_arg == NULL && arg != NULL) { 389 1.1 jmcneill device_printf(dev, "cannot share irq with NULL arg\n"); 390 1.1 jmcneill return NULL; 391 1.1 jmcneill } 392 1.1 jmcneill if (firq->intr_ipl != ipl) { 393 1.1 jmcneill device_printf(dev, "cannot share irq with different " 394 1.1 jmcneill "ipl\n"); 395 1.1 jmcneill return NULL; 396 1.1 jmcneill } 397 1.1 jmcneill if (firq->intr_level != level) { 398 1.1 jmcneill device_printf(dev, "cannot share edge and level " 399 1.1 jmcneill "interrupts\n"); 400 1.1 jmcneill return NULL; 401 1.1 jmcneill } 402 1.1 jmcneill if (firq->intr_mpsafe != mpsafe) { 403 1.1 jmcneill device_printf(dev, "cannot share between " 404 1.1 jmcneill "mpsafe/non-mpsafe\n"); 405 1.1 jmcneill return NULL; 406 1.1 jmcneill } 407 1.1 jmcneill } 408 1.1 jmcneill 409 1.1 jmcneill firq->intr_refcnt++; 410 1.1 jmcneill 411 1.1 jmcneill firqh = kmem_alloc(sizeof(*firqh), KM_SLEEP); 412 1.1 jmcneill firqh->ih_mpsafe = (flags & FDT_INTR_MPSAFE) != 0; 413 1.1 jmcneill firqh->ih_irq = firq; 414 1.1 jmcneill firqh->ih_fn = func; 415 1.1 jmcneill firqh->ih_arg = arg; 416 1.1 jmcneill TAILQ_INSERT_TAIL(&firq->intr_handlers, firqh, ih_next); 417 1.1 jmcneill 418 1.1 jmcneill return firq->intr_ih; 419 1.1 jmcneill } 420 1.1 jmcneill 421 1.1 jmcneill static void 422 1.1 jmcneill gicv3_fdt_disestablish(device_t dev, void *ih) 423 1.1 jmcneill { 424 1.1 jmcneill struct gicv3_fdt_softc * const sc = device_private(dev); 425 1.1 jmcneill struct gicv3_fdt_irqhandler *firqh; 426 1.1 jmcneill struct gicv3_fdt_irq *firq; 427 1.1 jmcneill u_int n; 428 1.1 jmcneill 429 1.1 jmcneill for (n = 0; n < GICV3_MAXIRQ; n++) { 430 1.1 jmcneill firq = sc->sc_irq[n]; 431 1.5 jakllsch if (firq == NULL || firq->intr_ih != ih) 432 1.1 jmcneill continue; 433 1.1 jmcneill 434 1.1 jmcneill KASSERT(firq->intr_refcnt > 0); 435 1.1 jmcneill 436 1.1 jmcneill if (firq->intr_refcnt > 1) 437 1.1 jmcneill panic("%s: cannot disestablish shared irq", __func__); 438 1.1 jmcneill 439 1.1 jmcneill firqh = TAILQ_FIRST(&firq->intr_handlers); 440 1.1 jmcneill kmem_free(firqh, sizeof(*firqh)); 441 1.1 jmcneill intr_disestablish(firq->intr_ih); 442 1.1 jmcneill kmem_free(firq, sizeof(*firq)); 443 1.1 jmcneill sc->sc_irq[n] = NULL; 444 1.1 jmcneill return; 445 1.1 jmcneill } 446 1.1 jmcneill 447 1.1 jmcneill panic("%s: interrupt not established", __func__); 448 1.1 jmcneill } 449 1.1 jmcneill 450 1.1 jmcneill static int 451 1.1 jmcneill gicv3_fdt_intr(void *priv) 452 1.1 jmcneill { 453 1.1 jmcneill struct gicv3_fdt_irq *firq = priv; 454 1.1 jmcneill struct gicv3_fdt_irqhandler *firqh; 455 1.1 jmcneill int handled = 0; 456 1.1 jmcneill 457 1.1 jmcneill TAILQ_FOREACH(firqh, &firq->intr_handlers, ih_next) 458 1.1 jmcneill handled += firqh->ih_fn(firqh->ih_arg); 459 1.1 jmcneill 460 1.1 jmcneill return handled; 461 1.1 jmcneill } 462 1.1 jmcneill 463 1.1 jmcneill static bool 464 1.1 jmcneill gicv3_fdt_intrstr(device_t dev, u_int *specifier, char *buf, size_t buflen) 465 1.1 jmcneill { 466 1.1 jmcneill /* 1st cell is the interrupt type; 0 is SPI, 1 is PPI */ 467 1.1 jmcneill /* 2nd cell is the interrupt number */ 468 1.1 jmcneill /* 3rd cell is flags */ 469 1.1 jmcneill /* 4th cell is affinity */ 470 1.1 jmcneill 471 1.1 jmcneill if (!specifier) 472 1.1 jmcneill return false; 473 1.1 jmcneill const u_int type = be32toh(specifier[0]); 474 1.1 jmcneill const u_int intr = be32toh(specifier[1]); 475 1.1 jmcneill const u_int irq = type == 0 ? IRQ_SPI(intr) : IRQ_PPI(intr); 476 1.1 jmcneill 477 1.1 jmcneill snprintf(buf, buflen, "GICv3 irq %d", irq); 478 1.1 jmcneill 479 1.1 jmcneill return true; 480 1.1 jmcneill } 481