1 /* $NetBSD: gicv3_fdt.c,v 1.16 2021/11/17 21:46:12 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2015-2018 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include "pci.h" 30 31 #define _INTR_PRIVATE 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: gicv3_fdt.c,v 1.16 2021/11/17 21:46:12 jmcneill Exp $"); 35 36 #include <sys/param.h> 37 #include <sys/bus.h> 38 #include <sys/device.h> 39 #include <sys/intr.h> 40 #include <sys/systm.h> 41 #include <sys/kernel.h> 42 #include <sys/lwp.h> 43 #include <sys/kmem.h> 44 #include <sys/queue.h> 45 46 #include <dev/fdt/fdtvar.h> 47 48 #include <arm/cortex/gicv3.h> 49 #include <arm/cortex/gicv3_its.h> 50 #include <arm/cortex/gic_reg.h> 51 #include <arm/cortex/gic_v2m.h> 52 53 #define GICV3_MAXIRQ 1020 54 55 #define IRQ_PPI(n) ((n) + 16) 56 #define IRQ_SPI(n) ((n) + 32) 57 58 struct gicv3_fdt_softc; 59 struct gicv3_fdt_irq; 60 61 static int gicv3_fdt_match(device_t, cfdata_t, void *); 62 static void gicv3_fdt_attach(device_t, device_t, void *); 63 64 static int gicv3_fdt_map_registers(struct gicv3_fdt_softc *); 65 #if NPCI > 0 && defined(__HAVE_PCI_MSI_MSIX) 66 static void gicv3_fdt_attach_mbi(struct gicv3_fdt_softc *); 67 static void gicv3_fdt_attach_its(struct gicv3_fdt_softc *, bus_space_tag_t, int); 68 #endif 69 70 static int gicv3_fdt_intr(void *); 71 72 static void * gicv3_fdt_establish(device_t, u_int *, int, int, 73 int (*)(void *), void *, const char *); 74 static void gicv3_fdt_disestablish(device_t, void *); 75 static bool gicv3_fdt_intrstr(device_t, u_int *, char *, size_t); 76 77 struct fdtbus_interrupt_controller_func gicv3_fdt_funcs = { 78 .establish = gicv3_fdt_establish, 79 .disestablish = gicv3_fdt_disestablish, 80 .intrstr = gicv3_fdt_intrstr 81 }; 82 83 struct gicv3_fdt_irqhandler { 84 struct gicv3_fdt_irq *ih_irq; 85 int (*ih_fn)(void *); 86 void *ih_arg; 87 bool ih_mpsafe; 88 TAILQ_ENTRY(gicv3_fdt_irqhandler) ih_next; 89 }; 90 91 struct gicv3_fdt_irq { 92 struct gicv3_fdt_softc *intr_sc; 93 void *intr_ih; 94 void *intr_arg; 95 int intr_refcnt; 96 int intr_ipl; 97 int intr_level; 98 int intr_mpsafe; 99 TAILQ_HEAD(, gicv3_fdt_irqhandler) intr_handlers; 100 int intr_irq; 101 }; 102 103 struct gicv3_fdt_softc { 104 struct gicv3_softc sc_gic; 105 int sc_phandle; 106 107 struct gicv3_fdt_irq *sc_irq[GICV3_MAXIRQ]; 108 }; 109 110 static const struct device_compatible_entry gicv3_fdt_quirks[] = { 111 { .compat = "rockchip,rk3399", .value = GICV3_QUIRK_RK3399 }, 112 DEVICE_COMPAT_EOL 113 }; 114 115 CFATTACH_DECL_NEW(gicv3_fdt, sizeof(struct gicv3_fdt_softc), 116 gicv3_fdt_match, gicv3_fdt_attach, NULL, NULL); 117 118 static const struct device_compatible_entry compat_data[] = { 119 { .compat = "arm,gic-v3" }, 120 DEVICE_COMPAT_EOL 121 }; 122 123 static int 124 gicv3_fdt_match(device_t parent, cfdata_t cf, void *aux) 125 { 126 struct fdt_attach_args * const faa = aux; 127 const int phandle = faa->faa_phandle; 128 129 return of_compatible_match(phandle, compat_data); 130 } 131 132 static void 133 gicv3_fdt_attach(device_t parent, device_t self, void *aux) 134 { 135 struct gicv3_fdt_softc * const sc = device_private(self); 136 struct fdt_attach_args * const faa = aux; 137 const int phandle = faa->faa_phandle; 138 int error; 139 140 error = fdtbus_register_interrupt_controller(self, phandle, 141 &gicv3_fdt_funcs); 142 if (error) { 143 aprint_error(": couldn't register with fdtbus: %d\n", error); 144 return; 145 } 146 147 aprint_naive("\n"); 148 aprint_normal(": GICv3\n"); 149 150 sc->sc_phandle = phandle; 151 sc->sc_gic.sc_dev = self; 152 sc->sc_gic.sc_bst = faa->faa_bst; 153 sc->sc_gic.sc_dmat = faa->faa_dmat; 154 155 error = gicv3_fdt_map_registers(sc); 156 if (error) { 157 aprint_error_dev(self, "couldn't map registers\n"); 158 return; 159 } 160 161 aprint_debug_dev(self, "%d redistributors\n", sc->sc_gic.sc_bsh_r_count); 162 163 /* Apply quirks */ 164 const struct device_compatible_entry *dce = 165 of_compatible_lookup(OF_finddevice("/"), gicv3_fdt_quirks); 166 if (dce != NULL) { 167 sc->sc_gic.sc_quirks |= dce->value; 168 } 169 170 error = gicv3_init(&sc->sc_gic); 171 if (error) { 172 aprint_error_dev(self, "failed to initialize GIC: %d\n", error); 173 return; 174 } 175 176 #if NPCI > 0 && defined(__HAVE_PCI_MSI_MSIX) 177 if (of_hasprop(phandle, "msi-controller")) { 178 /* Message Based Interrupts */ 179 gicv3_fdt_attach_mbi(sc); 180 } else { 181 /* Interrupt Translation Services */ 182 static const struct device_compatible_entry its_compat[] = { 183 { .compat = "arm,gic-v3-its" }, 184 DEVICE_COMPAT_EOL 185 }; 186 187 for (int child = OF_child(phandle); child; 188 child = OF_peer(child)) { 189 if (!fdtbus_status_okay(child)) 190 continue; 191 if (of_compatible_match(child, its_compat)) 192 gicv3_fdt_attach_its(sc, faa->faa_bst, child); 193 } 194 } 195 #endif 196 197 arm_fdt_irq_set_handler(gicv3_irq_handler); 198 } 199 200 static int 201 gicv3_fdt_map_registers(struct gicv3_fdt_softc *sc) 202 { 203 struct gicv3_softc *gic = &sc->sc_gic; 204 const int phandle = sc->sc_phandle; 205 u_int redistributor_regions, redistributor_stride; 206 bus_space_handle_t bsh; 207 bus_size_t size, region_off; 208 bus_addr_t addr; 209 size_t reg_off; 210 int n, r, max_redist, redist; 211 212 if (of_getprop_uint32(phandle, "#redistributor-regions", &redistributor_regions)) 213 redistributor_regions = 1; 214 if (of_getprop_uint32(phandle, "redistributor-stride", &redistributor_stride)) 215 redistributor_stride = 0x20000; 216 217 /* 218 * Map GIC Distributor interface (GICD) 219 */ 220 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 221 aprint_error_dev(gic->sc_dev, "couldn't get distributor registers\n"); 222 return ENXIO; 223 } 224 if (bus_space_map(sc->sc_gic.sc_bst, addr, size, 0, &sc->sc_gic.sc_bsh_d) != 0) { 225 aprint_error_dev(gic->sc_dev, "couldn't map distributor registers\n"); 226 return ENXIO; 227 } 228 229 /* 230 * GIC Redistributors (GICR) 231 */ 232 for (reg_off = 1, max_redist = 0, n = 0; n < redistributor_regions; n++, reg_off++) { 233 if (fdtbus_get_reg(phandle, reg_off, NULL, &size) != 0) { 234 aprint_error_dev(gic->sc_dev, "couldn't get redistributor registers\n"); 235 return ENXIO; 236 } 237 max_redist += howmany(size, redistributor_stride); 238 } 239 gic->sc_bsh_r = kmem_alloc(sizeof(bus_space_handle_t) * max_redist, KM_SLEEP); 240 for (reg_off = 1, redist = 0, n = 0; n < redistributor_regions; n++, reg_off++) { 241 if (fdtbus_get_reg(phandle, reg_off, &addr, &size) != 0) { 242 aprint_error_dev(gic->sc_dev, "couldn't get redistributor registers\n"); 243 return ENXIO; 244 } 245 if (bus_space_map(sc->sc_gic.sc_bst, addr, size, 0, &bsh) != 0) { 246 aprint_error_dev(gic->sc_dev, "couldn't map redistributor registers\n"); 247 return ENXIO; 248 } 249 const int count = howmany(size, redistributor_stride); 250 for (r = 0, region_off = 0; r < count; r++, region_off += redistributor_stride) { 251 if (bus_space_subregion(sc->sc_gic.sc_bst, bsh, region_off, redistributor_stride, &gic->sc_bsh_r[redist++]) != 0) { 252 aprint_error_dev(gic->sc_dev, "couldn't subregion redistributor registers\n"); 253 return ENXIO; 254 } 255 256 /* If this is the last redist in this region, skip to the next one */ 257 const uint32_t typer = bus_space_read_4(sc->sc_gic.sc_bst, gic->sc_bsh_r[redist - 1], GICR_TYPER); 258 if (typer & GICR_TYPER_Last) 259 break; 260 } 261 } 262 gic->sc_bsh_r_count = redist; 263 264 return 0; 265 } 266 267 #if NPCI > 0 && defined(__HAVE_PCI_MSI_MSIX) 268 static void 269 gicv3_fdt_attach_mbi(struct gicv3_fdt_softc *sc) 270 { 271 struct gic_v2m_frame *frame; 272 const u_int *ranges; 273 bus_addr_t addr; 274 int len, frame_count; 275 276 /* 277 * If a GICD alias frame containing only the SET/CLRSPI registers 278 * exists, the base address will be reported by the 'mbi-alias' 279 * property. If this doesn't exist, use the GICD register frame 280 * instead. 281 */ 282 if (of_getprop_uint64(sc->sc_phandle, "mbi-alias", &addr) != 0 && 283 fdtbus_get_reg(sc->sc_phandle, 0, &addr, NULL) != 0) { 284 aprint_error_dev(sc->sc_gic.sc_dev, "couldn't find MBI register frame\n"); 285 return; 286 } 287 288 ranges = fdtbus_get_prop(sc->sc_phandle, "mbi-ranges", &len); 289 if (ranges == NULL) { 290 aprint_error_dev(sc->sc_gic.sc_dev, "missing 'mbi-ranges' property\n"); 291 return; 292 } 293 294 frame_count = 0; 295 while (len >= 8) { 296 const u_int base_spi = be32dec(&ranges[0]); 297 const u_int num_spis = be32dec(&ranges[1]); 298 299 frame = kmem_zalloc(sizeof(*frame), KM_SLEEP); 300 frame->frame_reg = addr; 301 frame->frame_pic = pic_list[0]; 302 frame->frame_base = base_spi; 303 frame->frame_count = num_spis; 304 305 if (gic_v2m_init(frame, sc->sc_gic.sc_dev, frame_count++) != 0) { 306 aprint_error_dev(sc->sc_gic.sc_dev, "failed to initialize MBI frame\n"); 307 } else { 308 aprint_normal_dev(sc->sc_gic.sc_dev, "MBI frame @ %#" PRIx64 309 ", SPIs %u-%u\n", frame->frame_reg, 310 frame->frame_base, frame->frame_base + frame->frame_count - 1); 311 } 312 313 ranges += 2; 314 len -= 8; 315 } 316 } 317 318 static void 319 gicv3_fdt_attach_its(struct gicv3_fdt_softc *sc, bus_space_tag_t bst, int phandle) 320 { 321 bus_space_handle_t bsh; 322 bus_addr_t addr; 323 bus_size_t size; 324 325 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 326 aprint_error_dev(sc->sc_gic.sc_dev, "couldn't get ITS address\n"); 327 return; 328 } 329 330 if (bus_space_map(bst, addr, size, 0, &bsh) != 0) { 331 aprint_error_dev(sc->sc_gic.sc_dev, "couldn't map ITS\n"); 332 return; 333 } 334 335 gicv3_its_init(&sc->sc_gic, bsh, addr, 0); 336 337 aprint_verbose_dev(sc->sc_gic.sc_dev, "ITS @ %#" PRIxBUSADDR "\n", 338 addr); 339 } 340 #endif 341 342 static void * 343 gicv3_fdt_establish(device_t dev, u_int *specifier, int ipl, int flags, 344 int (*func)(void *), void *arg, const char *xname) 345 { 346 struct gicv3_fdt_softc * const sc = device_private(dev); 347 struct gicv3_fdt_irq *firq; 348 struct gicv3_fdt_irqhandler *firqh; 349 350 /* 1st cell is the interrupt type; 0 is SPI, 1 is PPI */ 351 /* 2nd cell is the interrupt number */ 352 /* 3rd cell is flags */ 353 /* 4th cell is affinity */ 354 355 const u_int type = be32toh(specifier[0]); 356 const u_int intr = be32toh(specifier[1]); 357 const u_int irq = type == 0 ? IRQ_SPI(intr) : IRQ_PPI(intr); 358 const u_int trig = be32toh(specifier[2]) & 0xf; 359 const u_int level = (trig & FDT_INTR_TYPE_DOUBLE_EDGE) 360 ? IST_EDGE : IST_LEVEL; 361 362 const u_int mpsafe = (flags & FDT_INTR_MPSAFE) ? IST_MPSAFE : 0; 363 364 firq = sc->sc_irq[irq]; 365 if (firq == NULL) { 366 firq = kmem_alloc(sizeof(*firq), KM_SLEEP); 367 firq->intr_sc = sc; 368 firq->intr_refcnt = 0; 369 firq->intr_arg = arg; 370 firq->intr_ipl = ipl; 371 firq->intr_level = level; 372 firq->intr_mpsafe = mpsafe; 373 TAILQ_INIT(&firq->intr_handlers); 374 firq->intr_irq = irq; 375 if (arg == NULL) { 376 firq->intr_ih = intr_establish_xname(irq, ipl, 377 level | mpsafe, func, NULL, xname); 378 } else { 379 firq->intr_ih = intr_establish_xname(irq, ipl, 380 level | mpsafe, gicv3_fdt_intr, firq, xname); 381 } 382 if (firq->intr_ih == NULL) { 383 kmem_free(firq, sizeof(*firq)); 384 return NULL; 385 } 386 sc->sc_irq[irq] = firq; 387 } else { 388 if (firq->intr_arg == NULL && arg != NULL) { 389 device_printf(dev, "cannot share irq with NULL arg\n"); 390 return NULL; 391 } 392 if (firq->intr_ipl != ipl) { 393 device_printf(dev, "cannot share irq with different " 394 "ipl\n"); 395 return NULL; 396 } 397 if (firq->intr_level != level) { 398 device_printf(dev, "cannot share edge and level " 399 "interrupts\n"); 400 return NULL; 401 } 402 if (firq->intr_mpsafe != mpsafe) { 403 device_printf(dev, "cannot share between " 404 "mpsafe/non-mpsafe\n"); 405 return NULL; 406 } 407 } 408 409 firq->intr_refcnt++; 410 411 firqh = kmem_alloc(sizeof(*firqh), KM_SLEEP); 412 firqh->ih_mpsafe = (flags & FDT_INTR_MPSAFE) != 0; 413 firqh->ih_irq = firq; 414 firqh->ih_fn = func; 415 firqh->ih_arg = arg; 416 TAILQ_INSERT_TAIL(&firq->intr_handlers, firqh, ih_next); 417 418 return firq->intr_ih; 419 } 420 421 static void 422 gicv3_fdt_disestablish(device_t dev, void *ih) 423 { 424 struct gicv3_fdt_softc * const sc = device_private(dev); 425 struct gicv3_fdt_irqhandler *firqh; 426 struct gicv3_fdt_irq *firq; 427 u_int n; 428 429 for (n = 0; n < GICV3_MAXIRQ; n++) { 430 firq = sc->sc_irq[n]; 431 if (firq == NULL || firq->intr_ih != ih) 432 continue; 433 434 KASSERT(firq->intr_refcnt > 0); 435 436 if (firq->intr_refcnt > 1) 437 panic("%s: cannot disestablish shared irq", __func__); 438 439 firqh = TAILQ_FIRST(&firq->intr_handlers); 440 kmem_free(firqh, sizeof(*firqh)); 441 intr_disestablish(firq->intr_ih); 442 kmem_free(firq, sizeof(*firq)); 443 sc->sc_irq[n] = NULL; 444 return; 445 } 446 447 panic("%s: interrupt not established", __func__); 448 } 449 450 static int 451 gicv3_fdt_intr(void *priv) 452 { 453 struct gicv3_fdt_irq *firq = priv; 454 struct gicv3_fdt_irqhandler *firqh; 455 int handled = 0; 456 457 TAILQ_FOREACH(firqh, &firq->intr_handlers, ih_next) 458 handled += firqh->ih_fn(firqh->ih_arg); 459 460 return handled; 461 } 462 463 static bool 464 gicv3_fdt_intrstr(device_t dev, u_int *specifier, char *buf, size_t buflen) 465 { 466 /* 1st cell is the interrupt type; 0 is SPI, 1 is PPI */ 467 /* 2nd cell is the interrupt number */ 468 /* 3rd cell is flags */ 469 /* 4th cell is affinity */ 470 471 if (!specifier) 472 return false; 473 const u_int type = be32toh(specifier[0]); 474 const u_int intr = be32toh(specifier[1]); 475 const u_int irq = type == 0 ? IRQ_SPI(intr) : IRQ_PPI(intr); 476 477 snprintf(buf, buflen, "GICv3 irq %d", irq); 478 479 return true; 480 } 481
Indexes created Sat Sep 20 22:09:52 GMT 2025