1 /* $NetBSD: plfb_fdt.c,v 1.6 2025/09/06 22:53:47 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * ARM PrimeCell PL111 framebuffer console driver 31 */ 32 33 #include "opt_wsdisplay_compat.h" 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: plfb_fdt.c,v 1.6 2025/09/06 22:53:47 thorpej Exp $"); 37 38 #include <sys/param.h> 39 #include <sys/types.h> 40 #include <sys/systm.h> 41 #include <sys/device.h> 42 #include <sys/conf.h> 43 #include <sys/bus.h> 44 #include <sys/kmem.h> 45 #include <sys/sysctl.h> 46 47 #include <dev/wsfb/genfbvar.h> 48 49 #include <dev/fdt/fdtvar.h> 50 #include <dev/fdt/fdt_console.h> 51 #include <dev/fdt/display_timing.h> 52 53 #define LCDTIMING0 0x000 54 #define LCDTIMING0_HBP __BITS(31,24) 55 #define LCDTIMING0_HFP __BITS(23,16) 56 #define LCDTIMING0_HSW __BITS(15,8) 57 #define LCDTIMING0_PPL __BITS(7,2) 58 #define LCDTIMING1 0x004 59 #define LCDTIMING1_VBP __BITS(31,24) 60 #define LCDTIMING1_VFP __BITS(23,16) 61 #define LCDTIMING1_VSW __BITS(15,10) 62 #define LCDTIMING1_LPP __BITS(9,0) 63 #define LCDUPBASE 0x010 64 #define LCDLPBASE 0x014 65 #define LCDCONTROL 0x018 66 #define LCDCONTROL_PWR __BIT(11) 67 #define LCDCONTROL_BGR __BIT(8) 68 #define LCDCONTROL_BPP __BITS(3,1) 69 #define LCDCONTROL_BPP_24 __SHIFTIN(5, LCDCONTROL_BPP) 70 #define LCDCONTROL_EN __BIT(0) 71 72 #define PLFB_BPP 32 73 74 static int plfb_console_phandle = -1; 75 76 struct plfb_softc { 77 struct genfb_softc sc_gen; 78 bus_space_tag_t sc_bst; 79 bus_space_handle_t sc_bsh; 80 int sc_phandle; 81 82 bus_space_handle_t sc_vram_bsh; 83 bus_addr_t sc_vram_addr; 84 bus_size_t sc_vram_size; 85 uintptr_t sc_vram; 86 87 uint32_t sc_wstype; 88 }; 89 90 static int plfb_match(device_t, cfdata_t, void *); 91 static void plfb_attach(device_t, device_t, void *); 92 93 static int plfb_ioctl(void *, void *, u_long, void *, int, lwp_t *); 94 static paddr_t plfb_mmap(void *, void *, off_t, int); 95 static bool plfb_shutdown(device_t, int); 96 97 static void plfb_init(struct plfb_softc *); 98 99 static const struct device_compatible_entry compat_data[] = { 100 { .compat = "arm,pl111" }, 101 DEVICE_COMPAT_EOL 102 }; 103 104 CFATTACH_DECL_NEW(plfb_fdt, sizeof(struct plfb_softc), 105 plfb_match, plfb_attach, NULL, NULL); 106 107 #define FB_READ(sc, reg) \ 108 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 109 #define FB_WRITE(sc, reg, val) \ 110 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 111 112 static int 113 plfb_match(device_t parent, cfdata_t match, void *aux) 114 { 115 struct fdt_attach_args * const faa = aux; 116 117 return of_compatible_match(faa->faa_phandle, compat_data); 118 } 119 120 static void 121 plfb_attach(device_t parent, device_t self, void *aux) 122 { 123 struct plfb_softc *sc = device_private(self); 124 prop_dictionary_t dict = device_properties(self); 125 struct fdt_attach_args * const faa = aux; 126 const int phandle = faa->faa_phandle; 127 struct genfb_ops ops; 128 struct clk *clk; 129 bus_addr_t addr; 130 bus_size_t size; 131 132 sc->sc_gen.sc_dev = self; 133 sc->sc_phandle = phandle; 134 sc->sc_bst = faa->faa_bst; 135 136 /* Enable clocks */ 137 for (int i = 0; (clk = fdtbus_clock_get_index(phandle, i)); i++) 138 if (clk_enable(clk) != 0) { 139 aprint_error(": couldn't enable clock #%d\n", i); 140 return; 141 } 142 143 /* Map CLCD registers */ 144 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 145 aprint_error(": missing 'reg' property\n"); 146 return; 147 } 148 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh)) { 149 aprint_error(": couldn't map device\n"); 150 return; 151 } 152 153 /* Map VRAM */ 154 const int vram_phandle = fdtbus_get_phandle(phandle, "memory-region"); 155 if (vram_phandle == -1) { 156 /* 157 * The 'memory-region' property is optional. If 158 * absent, we can allocate FB from main RAM. (TODO) 159 */ 160 aprint_error(": missing 'memory-region' property\n"); 161 return; 162 } 163 if (fdtbus_get_reg(vram_phandle, 0, &sc->sc_vram_addr, 164 &sc->sc_vram_size) != 0) { 165 aprint_error(": missing 'reg' property on memory-region\n"); 166 return; 167 } 168 if (bus_space_map(sc->sc_bst, sc->sc_vram_addr, sc->sc_vram_size, 169 BUS_SPACE_MAP_LINEAR, &sc->sc_vram_bsh)) { 170 aprint_error(": couldn't map vram\n"); 171 return; 172 } 173 sc->sc_vram = (uintptr_t)bus_space_vaddr(sc->sc_bst, sc->sc_vram_bsh); 174 175 plfb_init(sc); 176 177 aprint_naive("\n"); 178 aprint_normal("\n"); 179 180 sc->sc_wstype = WSDISPLAY_TYPE_PLFB; 181 182 #ifdef WSDISPLAY_MULTICONS 183 const bool is_console = true; 184 genfb_cnattach(); 185 #else 186 const bool is_console = phandle == plfb_console_phandle; 187 if (is_console) 188 aprint_normal_dev(self, "switching to framebuffer console\n"); 189 #endif 190 191 prop_dictionary_set_bool(dict, "is_console", is_console); 192 193 genfb_init(&sc->sc_gen); 194 195 if (sc->sc_gen.sc_width == 0 || 196 sc->sc_gen.sc_fbsize == 0) { 197 aprint_normal_dev(self, "disabled\n"); 198 return; 199 } 200 201 pmf_device_register1(self, NULL, NULL, plfb_shutdown); 202 203 memset(&ops, 0, sizeof(ops)); 204 ops.genfb_ioctl = plfb_ioctl; 205 ops.genfb_mmap = plfb_mmap; 206 207 genfb_attach(&sc->sc_gen, &ops); 208 } 209 210 static int 211 plfb_ioctl(void *v, void *vs, u_long cmd, void *data, int flag, lwp_t *l) 212 { 213 struct plfb_softc *sc = v; 214 struct wsdisplayio_bus_id *busid; 215 216 switch (cmd) { 217 case WSDISPLAYIO_GTYPE: 218 *(u_int *)data = sc->sc_wstype; 219 return 0; 220 case WSDISPLAYIO_GET_BUSID: 221 busid = data; 222 busid->bus_type = WSDISPLAYIO_BUS_SOC; 223 return 0; 224 case WSDISPLAYIO_GET_FBINFO: 225 { 226 struct wsdisplayio_fbinfo *fbi = data; 227 struct rasops_info *ri = &sc->sc_gen.vd.active->scr_ri; 228 229 return wsdisplayio_get_fbinfo(ri, fbi); 230 } 231 default: 232 return EPASSTHROUGH; 233 } 234 } 235 236 static paddr_t 237 plfb_mmap(void *v, void *vs, off_t offset, int prot) 238 { 239 struct plfb_softc *sc = v; 240 241 if (offset < 0 || offset >= sc->sc_vram_size) 242 return -1; 243 244 return bus_space_mmap(sc->sc_bst, sc->sc_vram_addr, offset, prot, 245 BUS_SPACE_MAP_LINEAR | BUS_SPACE_MAP_PREFETCHABLE); 246 } 247 248 static bool 249 plfb_shutdown(device_t self, int flags) 250 { 251 genfb_enable_polling(self); 252 return true; 253 } 254 255 static int 256 plfb_get_panel_timing(struct plfb_softc *sc, struct display_timing *timing) 257 { 258 int panel, panel_timing; 259 260 panel = of_find_firstchild_byname(sc->sc_phandle, "panel"); 261 if (panel <= 0) 262 return ENOENT; 263 panel_timing = of_find_firstchild_byname(panel, "panel-timing"); 264 if (panel_timing <= 0) 265 return ENOENT; 266 267 return display_timing_parse(panel_timing, timing); 268 } 269 270 static void 271 plfb_init(struct plfb_softc *sc) 272 { 273 prop_dictionary_t dict = device_properties(sc->sc_gen.sc_dev); 274 struct display_timing timing; 275 276 if (plfb_get_panel_timing(sc, &timing) != 0) { 277 /* No timings specified in DT, assume 800x600 */ 278 timing.hactive = 800; 279 timing.hback_porch = 128; 280 timing.hfront_porch = 24; 281 timing.hsync_len = 72; 282 timing.vactive = 600; 283 timing.vback_porch = 22; 284 timing.vfront_porch = 1; 285 timing.vsync_len = 2; 286 } 287 288 prop_dictionary_set_uint32(dict, "width", timing.hactive); 289 prop_dictionary_set_uint32(dict, "height", timing.vactive); 290 prop_dictionary_set_uint8(dict, "depth", PLFB_BPP); 291 prop_dictionary_set_bool(dict, "dblscan", 0); 292 prop_dictionary_set_bool(dict, "interlace", 0); 293 prop_dictionary_set_uint16(dict, "linebytes", timing.hactive * (PLFB_BPP / 8)); 294 prop_dictionary_set_uint32(dict, "address", sc->sc_vram_addr); 295 prop_dictionary_set_uint32(dict, "virtual_address", sc->sc_vram); 296 297 /* FB base address */ 298 FB_WRITE(sc, LCDUPBASE, sc->sc_vram_addr); 299 FB_WRITE(sc, LCDLPBASE, 0); 300 301 /* CRTC timings */ 302 FB_WRITE(sc, LCDTIMING0, 303 __SHIFTIN(timing.hback_porch - 1, LCDTIMING0_HBP) | 304 __SHIFTIN(timing.hfront_porch - 1, LCDTIMING0_HFP) | 305 __SHIFTIN(timing.hsync_len - 1, LCDTIMING0_HSW) | 306 __SHIFTIN((timing.hactive / 16) - 1, LCDTIMING0_PPL)); 307 FB_WRITE(sc, LCDTIMING1, 308 __SHIFTIN(timing.vback_porch - 1, LCDTIMING1_VBP) | 309 __SHIFTIN(timing.vfront_porch - 1, LCDTIMING1_VFP) | 310 __SHIFTIN(timing.vsync_len - 1, LCDTIMING1_VSW) | 311 __SHIFTIN(timing.vactive - 1, LCDTIMING1_LPP)); 312 313 /* Configure and enable CLCD */ 314 FB_WRITE(sc, LCDCONTROL, 315 LCDCONTROL_PWR | LCDCONTROL_EN | LCDCONTROL_BPP_24 | 316 LCDCONTROL_BGR); 317 } 318 319 static int 320 plfb_console_match(int phandle) 321 { 322 return of_compatible_match(phandle, compat_data); 323 } 324 325 static void 326 plfb_console_consinit(struct fdt_attach_args *faa, u_int uart_freq) 327 { 328 plfb_console_phandle = faa->faa_phandle; 329 genfb_cnattach(); 330 } 331 332 static const struct fdt_console plfb_fdt_console = { 333 .match = plfb_console_match, 334 .consinit = plfb_console_consinit 335 }; 336 337 FDT_CONSOLE(plfb, &plfb_fdt_console); 338
Indexes created Sun Sep 21 20:09:37 GMT 2025