plfb_fdt.c revision 1.2.4.2 1 /* $NetBSD: plfb_fdt.c,v 1.2.4.2 2017/08/28 17:51:30 skrll Exp $ */
2
3 /*-
4 * Copyright (c) 2017 Jared McNeill <jmcneill (at) invisible.ca>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26 * POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 /*
30 * ARM PrimeCell PL111 framebuffer console driver
31 */
32
33 #include <sys/cdefs.h>
34 __KERNEL_RCSID(0, "$NetBSD: plfb_fdt.c,v 1.2.4.2 2017/08/28 17:51:30 skrll Exp $");
35
36 #include <sys/param.h>
37 #include <sys/types.h>
38 #include <sys/systm.h>
39 #include <sys/device.h>
40 #include <sys/conf.h>
41 #include <sys/bus.h>
42 #include <sys/kmem.h>
43 #include <sys/sysctl.h>
44
45 #include <dev/wsfb/genfbvar.h>
46
47 #include <dev/fdt/fdtvar.h>
48 #include <dev/fdt/display_timing.h>
49
50 #define LCDTIMING0 0x000
51 #define LCDTIMING0_HBP __BITS(31,24)
52 #define LCDTIMING0_HFP __BITS(23,16)
53 #define LCDTIMING0_HSW __BITS(15,8)
54 #define LCDTIMING0_PPL __BITS(7,2)
55 #define LCDTIMING1 0x004
56 #define LCDTIMING1_VBP __BITS(31,24)
57 #define LCDTIMING1_VFP __BITS(23,16)
58 #define LCDTIMING1_VSW __BITS(15,10)
59 #define LCDTIMING1_LPP __BITS(9,0)
60 #define LCDUPBASE 0x010
61 #define LCDLPBASE 0x014
62 #define LCDCONTROL 0x018
63 #define LCDCONTROL_PWR __BIT(11)
64 #define LCDCONTROL_BGR __BIT(8)
65 #define LCDCONTROL_BPP __BITS(3,1)
66 #define LCDCONTROL_BPP_24 __SHIFTIN(5, LCDCONTROL_BPP)
67 #define LCDCONTROL_EN __BIT(0)
68
69 #define PLFB_BPP 32
70
71 static int plfb_console_phandle = -1;
72
73 struct plfb_softc {
74 struct genfb_softc sc_gen;
75 bus_space_tag_t sc_bst;
76 bus_space_handle_t sc_bsh;
77 int sc_phandle;
78
79 bus_space_handle_t sc_vram_bsh;
80 bus_addr_t sc_vram_addr;
81 bus_size_t sc_vram_size;
82 uintptr_t sc_vram;
83
84 uint32_t sc_wstype;
85 };
86
87 static int plfb_match(device_t, cfdata_t, void *);
88 static void plfb_attach(device_t, device_t, void *);
89
90 static int plfb_ioctl(void *, void *, u_long, void *, int, lwp_t *);
91 static paddr_t plfb_mmap(void *, void *, off_t, int);
92 static bool plfb_shutdown(device_t, int);
93
94 static void plfb_init(struct plfb_softc *);
95
96 static const char * const compatible[] = {
97 "arm,pl111",
98 NULL
99 };
100
101 CFATTACH_DECL_NEW(plfb_fdt, sizeof(struct plfb_softc),
102 plfb_match, plfb_attach, NULL, NULL);
103
104 #define FB_READ(sc, reg) \
105 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
106 #define FB_WRITE(sc, reg, val) \
107 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
108
109 static int
110 plfb_match(device_t parent, cfdata_t match, void *aux)
111 {
112 struct fdt_attach_args * const faa = aux;
113
114 return of_match_compatible(faa->faa_phandle, compatible);
115 }
116
117 static void
118 plfb_attach(device_t parent, device_t self, void *aux)
119 {
120 struct plfb_softc *sc = device_private(self);
121 prop_dictionary_t dict = device_properties(self);
122 struct fdt_attach_args * const faa = aux;
123 const int phandle = faa->faa_phandle;
124 struct genfb_ops ops;
125 struct clk *clk;
126 bus_addr_t addr;
127 bus_size_t size;
128
129 sc->sc_gen.sc_dev = self;
130 sc->sc_phandle = phandle;
131 sc->sc_bst = faa->faa_bst;
132
133 /* Enable clocks */
134 for (int i = 0; (clk = fdtbus_clock_get_index(phandle, i)); i++)
135 if (clk_enable(clk) != 0) {
136 aprint_error(": couldn't enable clock #%d\n", i);
137 return;
138 }
139
140 /* Map CLCD registers */
141 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) {
142 aprint_error(": missing 'reg' property\n");
143 return;
144 }
145 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh)) {
146 aprint_error(": couldn't map device\n");
147 return;
148 }
149
150 /* Map VRAM */
151 const int vram_phandle = fdtbus_get_phandle(phandle, "memory-region");
152 if (vram_phandle == -1) {
153 /*
154 * The 'memory-region' property is optional. If
155 * absent, we can allocate FB from main RAM. (TODO)
156 */
157 aprint_error(": missing 'memory-region' property\n");
158 return;
159 }
160 if (fdtbus_get_reg(vram_phandle, 0, &sc->sc_vram_addr,
161 &sc->sc_vram_size) != 0) {
162 aprint_error(": missing 'reg' property on memory-region\n");
163 return;
164 }
165 if (bus_space_map(sc->sc_bst, sc->sc_vram_addr, sc->sc_vram_size,
166 BUS_SPACE_MAP_LINEAR, &sc->sc_vram_bsh)) {
167 aprint_error(": couldn't map vram\n");
168 return;
169 }
170 sc->sc_vram = (uintptr_t)bus_space_vaddr(sc->sc_bst, sc->sc_vram_bsh);
171
172 plfb_init(sc);
173
174 sc->sc_wstype = WSDISPLAY_TYPE_PLFB;
175 prop_dictionary_set_bool(dict, "is_console",
176 phandle == plfb_console_phandle);
177
178 genfb_init(&sc->sc_gen);
179
180 if (sc->sc_gen.sc_width == 0 ||
181 sc->sc_gen.sc_fbsize == 0) {
182 aprint_normal(": disabled\n");
183 return;
184 }
185
186 pmf_device_register1(self, NULL, NULL, plfb_shutdown);
187
188 memset(&ops, 0, sizeof(ops));
189 ops.genfb_ioctl = plfb_ioctl;
190 ops.genfb_mmap = plfb_mmap;
191
192 aprint_naive("\n");
193 aprint_normal("\n");
194
195 genfb_attach(&sc->sc_gen, &ops);
196 }
197
198 static int
199 plfb_ioctl(void *v, void *vs, u_long cmd, void *data, int flag, lwp_t *l)
200 {
201 struct plfb_softc *sc = v;
202 struct wsdisplayio_bus_id *busid;
203
204 switch (cmd) {
205 case WSDISPLAYIO_GTYPE:
206 *(u_int *)data = sc->sc_wstype;
207 return 0;
208 case WSDISPLAYIO_GET_BUSID:
209 busid = data;
210 busid->bus_type = WSDISPLAYIO_BUS_SOC;
211 return 0;
212 case WSDISPLAYIO_GET_FBINFO:
213 {
214 struct wsdisplayio_fbinfo *fbi = data;
215 struct rasops_info *ri = &sc->sc_gen.vd.active->scr_ri;
216
217 return wsdisplayio_get_fbinfo(ri, fbi);
218 }
219 default:
220 return EPASSTHROUGH;
221 }
222 }
223
224 static paddr_t
225 plfb_mmap(void *v, void *vs, off_t offset, int prot)
226 {
227 struct plfb_softc *sc = v;
228
229 if (offset < 0 || offset >= sc->sc_vram_size)
230 return -1;
231
232 return bus_space_mmap(sc->sc_bst, sc->sc_vram_addr, offset, prot,
233 BUS_SPACE_MAP_LINEAR | BUS_SPACE_MAP_PREFETCHABLE);
234 }
235
236 static bool
237 plfb_shutdown(device_t self, int flags)
238 {
239 genfb_enable_polling(self);
240 return true;
241 }
242
243 static int
244 plfb_get_panel_timing(struct plfb_softc *sc, struct display_timing *timing)
245 {
246 int panel, panel_timing;
247
248 panel = of_find_firstchild_byname(sc->sc_phandle, "panel");
249 if (panel <= 0)
250 return ENOENT;
251 panel_timing = of_find_firstchild_byname(panel, "panel-timing");
252 if (panel_timing <= 0)
253 return ENOENT;
254
255 return display_timing_parse(panel_timing, timing);
256 }
257
258 static void
259 plfb_init(struct plfb_softc *sc)
260 {
261 prop_dictionary_t dict = device_properties(sc->sc_gen.sc_dev);
262 struct display_timing timing;
263
264 if (plfb_get_panel_timing(sc, &timing) != 0) {
265 aprint_error_dev(sc->sc_gen.sc_dev,
266 "couldn't get panel timings\n");
267 return;
268 }
269
270 prop_dictionary_set_uint32(dict, "width", timing.hactive);
271 prop_dictionary_set_uint32(dict, "height", timing.vactive);
272 prop_dictionary_set_uint8(dict, "depth", PLFB_BPP);
273 prop_dictionary_set_bool(dict, "dblscan", 0);
274 prop_dictionary_set_bool(dict, "interlace", 0);
275 prop_dictionary_set_uint16(dict, "linebytes", timing.hactive * (PLFB_BPP / 8));
276 prop_dictionary_set_uint32(dict, "address", sc->sc_vram_addr);
277 prop_dictionary_set_uint32(dict, "virtual_address", sc->sc_vram);
278
279 /* FB base address */
280 FB_WRITE(sc, LCDUPBASE, sc->sc_vram_addr);
281 FB_WRITE(sc, LCDLPBASE, 0);
282
283 /* CRTC timings */
284 FB_WRITE(sc, LCDTIMING0,
285 __SHIFTIN(timing.hback_porch - 1, LCDTIMING0_HBP) |
286 __SHIFTIN(timing.hfront_porch - 1, LCDTIMING0_HFP) |
287 __SHIFTIN(timing.hsync_len - 1, LCDTIMING0_HSW) |
288 __SHIFTIN((timing.hactive / 16) - 1, LCDTIMING0_PPL));
289 FB_WRITE(sc, LCDTIMING1,
290 __SHIFTIN(timing.vback_porch - 1, LCDTIMING1_VBP) |
291 __SHIFTIN(timing.vfront_porch - 1, LCDTIMING1_VFP) |
292 __SHIFTIN(timing.vsync_len - 1, LCDTIMING1_VSW) |
293 __SHIFTIN(timing.vactive - 1, LCDTIMING1_LPP));
294
295 /* Configure and enable CLCD */
296 FB_WRITE(sc, LCDCONTROL,
297 LCDCONTROL_PWR | LCDCONTROL_EN | LCDCONTROL_BPP_24 |
298 LCDCONTROL_BGR);
299 }
300
301 static int
302 plfb_console_match(int phandle)
303 {
304 return of_match_compatible(phandle, compatible);
305 }
306
307 static void
308 plfb_console_consinit(struct fdt_attach_args *faa, u_int uart_freq)
309 {
310 plfb_console_phandle = faa->faa_phandle;
311 genfb_cnattach();
312 }
313
314 static const struct fdt_console plfb_fdt_console = {
315 .match = plfb_console_match,
316 .consinit = plfb_console_consinit
317 };
318
319 FDT_CONSOLE(plfb, &plfb_fdt_console);
320