plfb_fdt.c revision 1.5
1 /* $NetBSD: plfb_fdt.c,v 1.5 2021/01/27 03:10:19 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * ARM PrimeCell PL111 framebuffer console driver 31 */ 32 33 #include "opt_wsdisplay_compat.h" 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: plfb_fdt.c,v 1.5 2021/01/27 03:10:19 thorpej Exp $"); 37 38 #include <sys/param.h> 39 #include <sys/types.h> 40 #include <sys/systm.h> 41 #include <sys/device.h> 42 #include <sys/conf.h> 43 #include <sys/bus.h> 44 #include <sys/kmem.h> 45 #include <sys/sysctl.h> 46 47 #include <dev/wsfb/genfbvar.h> 48 49 #include <dev/fdt/fdtvar.h> 50 #include <dev/fdt/display_timing.h> 51 52 #define LCDTIMING0 0x000 53 #define LCDTIMING0_HBP __BITS(31,24) 54 #define LCDTIMING0_HFP __BITS(23,16) 55 #define LCDTIMING0_HSW __BITS(15,8) 56 #define LCDTIMING0_PPL __BITS(7,2) 57 #define LCDTIMING1 0x004 58 #define LCDTIMING1_VBP __BITS(31,24) 59 #define LCDTIMING1_VFP __BITS(23,16) 60 #define LCDTIMING1_VSW __BITS(15,10) 61 #define LCDTIMING1_LPP __BITS(9,0) 62 #define LCDUPBASE 0x010 63 #define LCDLPBASE 0x014 64 #define LCDCONTROL 0x018 65 #define LCDCONTROL_PWR __BIT(11) 66 #define LCDCONTROL_BGR __BIT(8) 67 #define LCDCONTROL_BPP __BITS(3,1) 68 #define LCDCONTROL_BPP_24 __SHIFTIN(5, LCDCONTROL_BPP) 69 #define LCDCONTROL_EN __BIT(0) 70 71 #define PLFB_BPP 32 72 73 static int plfb_console_phandle = -1; 74 75 struct plfb_softc { 76 struct genfb_softc sc_gen; 77 bus_space_tag_t sc_bst; 78 bus_space_handle_t sc_bsh; 79 int sc_phandle; 80 81 bus_space_handle_t sc_vram_bsh; 82 bus_addr_t sc_vram_addr; 83 bus_size_t sc_vram_size; 84 uintptr_t sc_vram; 85 86 uint32_t sc_wstype; 87 }; 88 89 static int plfb_match(device_t, cfdata_t, void *); 90 static void plfb_attach(device_t, device_t, void *); 91 92 static int plfb_ioctl(void *, void *, u_long, void *, int, lwp_t *); 93 static paddr_t plfb_mmap(void *, void *, off_t, int); 94 static bool plfb_shutdown(device_t, int); 95 96 static void plfb_init(struct plfb_softc *); 97 98 static const struct device_compatible_entry compat_data[] = { 99 { .compat = "arm,pl111" }, 100 DEVICE_COMPAT_EOL 101 }; 102 103 CFATTACH_DECL_NEW(plfb_fdt, sizeof(struct plfb_softc), 104 plfb_match, plfb_attach, NULL, NULL); 105 106 #define FB_READ(sc, reg) \ 107 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 108 #define FB_WRITE(sc, reg, val) \ 109 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 110 111 static int 112 plfb_match(device_t parent, cfdata_t match, void *aux) 113 { 114 struct fdt_attach_args * const faa = aux; 115 116 return of_compatible_match(faa->faa_phandle, compat_data); 117 } 118 119 static void 120 plfb_attach(device_t parent, device_t self, void *aux) 121 { 122 struct plfb_softc *sc = device_private(self); 123 prop_dictionary_t dict = device_properties(self); 124 struct fdt_attach_args * const faa = aux; 125 const int phandle = faa->faa_phandle; 126 struct genfb_ops ops; 127 struct clk *clk; 128 bus_addr_t addr; 129 bus_size_t size; 130 131 sc->sc_gen.sc_dev = self; 132 sc->sc_phandle = phandle; 133 sc->sc_bst = faa->faa_bst; 134 135 /* Enable clocks */ 136 for (int i = 0; (clk = fdtbus_clock_get_index(phandle, i)); i++) 137 if (clk_enable(clk) != 0) { 138 aprint_error(": couldn't enable clock #%d\n", i); 139 return; 140 } 141 142 /* Map CLCD registers */ 143 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 144 aprint_error(": missing 'reg' property\n"); 145 return; 146 } 147 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh)) { 148 aprint_error(": couldn't map device\n"); 149 return; 150 } 151 152 /* Map VRAM */ 153 const int vram_phandle = fdtbus_get_phandle(phandle, "memory-region"); 154 if (vram_phandle == -1) { 155 /* 156 * The 'memory-region' property is optional. If 157 * absent, we can allocate FB from main RAM. (TODO) 158 */ 159 aprint_error(": missing 'memory-region' property\n"); 160 return; 161 } 162 if (fdtbus_get_reg(vram_phandle, 0, &sc->sc_vram_addr, 163 &sc->sc_vram_size) != 0) { 164 aprint_error(": missing 'reg' property on memory-region\n"); 165 return; 166 } 167 if (bus_space_map(sc->sc_bst, sc->sc_vram_addr, sc->sc_vram_size, 168 BUS_SPACE_MAP_LINEAR, &sc->sc_vram_bsh)) { 169 aprint_error(": couldn't map vram\n"); 170 return; 171 } 172 sc->sc_vram = (uintptr_t)bus_space_vaddr(sc->sc_bst, sc->sc_vram_bsh); 173 174 plfb_init(sc); 175 176 aprint_naive("\n"); 177 aprint_normal("\n"); 178 179 sc->sc_wstype = WSDISPLAY_TYPE_PLFB; 180 181 #ifdef WSDISPLAY_MULTICONS 182 const bool is_console = true; 183 genfb_cnattach(); 184 #else 185 const bool is_console = phandle == plfb_console_phandle; 186 if (is_console) 187 aprint_normal_dev(self, "switching to framebuffer console\n"); 188 #endif 189 190 prop_dictionary_set_bool(dict, "is_console", is_console); 191 192 genfb_init(&sc->sc_gen); 193 194 if (sc->sc_gen.sc_width == 0 || 195 sc->sc_gen.sc_fbsize == 0) { 196 aprint_normal_dev(self, "disabled\n"); 197 return; 198 } 199 200 pmf_device_register1(self, NULL, NULL, plfb_shutdown); 201 202 memset(&ops, 0, sizeof(ops)); 203 ops.genfb_ioctl = plfb_ioctl; 204 ops.genfb_mmap = plfb_mmap; 205 206 genfb_attach(&sc->sc_gen, &ops); 207 } 208 209 static int 210 plfb_ioctl(void *v, void *vs, u_long cmd, void *data, int flag, lwp_t *l) 211 { 212 struct plfb_softc *sc = v; 213 struct wsdisplayio_bus_id *busid; 214 215 switch (cmd) { 216 case WSDISPLAYIO_GTYPE: 217 *(u_int *)data = sc->sc_wstype; 218 return 0; 219 case WSDISPLAYIO_GET_BUSID: 220 busid = data; 221 busid->bus_type = WSDISPLAYIO_BUS_SOC; 222 return 0; 223 case WSDISPLAYIO_GET_FBINFO: 224 { 225 struct wsdisplayio_fbinfo *fbi = data; 226 struct rasops_info *ri = &sc->sc_gen.vd.active->scr_ri; 227 228 return wsdisplayio_get_fbinfo(ri, fbi); 229 } 230 default: 231 return EPASSTHROUGH; 232 } 233 } 234 235 static paddr_t 236 plfb_mmap(void *v, void *vs, off_t offset, int prot) 237 { 238 struct plfb_softc *sc = v; 239 240 if (offset < 0 || offset >= sc->sc_vram_size) 241 return -1; 242 243 return bus_space_mmap(sc->sc_bst, sc->sc_vram_addr, offset, prot, 244 BUS_SPACE_MAP_LINEAR | BUS_SPACE_MAP_PREFETCHABLE); 245 } 246 247 static bool 248 plfb_shutdown(device_t self, int flags) 249 { 250 genfb_enable_polling(self); 251 return true; 252 } 253 254 static int 255 plfb_get_panel_timing(struct plfb_softc *sc, struct display_timing *timing) 256 { 257 int panel, panel_timing; 258 259 panel = of_find_firstchild_byname(sc->sc_phandle, "panel"); 260 if (panel <= 0) 261 return ENOENT; 262 panel_timing = of_find_firstchild_byname(panel, "panel-timing"); 263 if (panel_timing <= 0) 264 return ENOENT; 265 266 return display_timing_parse(panel_timing, timing); 267 } 268 269 static void 270 plfb_init(struct plfb_softc *sc) 271 { 272 prop_dictionary_t dict = device_properties(sc->sc_gen.sc_dev); 273 struct display_timing timing; 274 275 if (plfb_get_panel_timing(sc, &timing) != 0) { 276 /* No timings specified in DT, assume 800x600 */ 277 timing.hactive = 800; 278 timing.hback_porch = 128; 279 timing.hfront_porch = 24; 280 timing.hsync_len = 72; 281 timing.vactive = 600; 282 timing.vback_porch = 22; 283 timing.vfront_porch = 1; 284 timing.vsync_len = 2; 285 } 286 287 prop_dictionary_set_uint32(dict, "width", timing.hactive); 288 prop_dictionary_set_uint32(dict, "height", timing.vactive); 289 prop_dictionary_set_uint8(dict, "depth", PLFB_BPP); 290 prop_dictionary_set_bool(dict, "dblscan", 0); 291 prop_dictionary_set_bool(dict, "interlace", 0); 292 prop_dictionary_set_uint16(dict, "linebytes", timing.hactive * (PLFB_BPP / 8)); 293 prop_dictionary_set_uint32(dict, "address", sc->sc_vram_addr); 294 prop_dictionary_set_uint32(dict, "virtual_address", sc->sc_vram); 295 296 /* FB base address */ 297 FB_WRITE(sc, LCDUPBASE, sc->sc_vram_addr); 298 FB_WRITE(sc, LCDLPBASE, 0); 299 300 /* CRTC timings */ 301 FB_WRITE(sc, LCDTIMING0, 302 __SHIFTIN(timing.hback_porch - 1, LCDTIMING0_HBP) | 303 __SHIFTIN(timing.hfront_porch - 1, LCDTIMING0_HFP) | 304 __SHIFTIN(timing.hsync_len - 1, LCDTIMING0_HSW) | 305 __SHIFTIN((timing.hactive / 16) - 1, LCDTIMING0_PPL)); 306 FB_WRITE(sc, LCDTIMING1, 307 __SHIFTIN(timing.vback_porch - 1, LCDTIMING1_VBP) | 308 __SHIFTIN(timing.vfront_porch - 1, LCDTIMING1_VFP) | 309 __SHIFTIN(timing.vsync_len - 1, LCDTIMING1_VSW) | 310 __SHIFTIN(timing.vactive - 1, LCDTIMING1_LPP)); 311 312 /* Configure and enable CLCD */ 313 FB_WRITE(sc, LCDCONTROL, 314 LCDCONTROL_PWR | LCDCONTROL_EN | LCDCONTROL_BPP_24 | 315 LCDCONTROL_BGR); 316 } 317 318 static int 319 plfb_console_match(int phandle) 320 { 321 return of_compatible_match(phandle, compat_data); 322 } 323 324 static void 325 plfb_console_consinit(struct fdt_attach_args *faa, u_int uart_freq) 326 { 327 plfb_console_phandle = faa->faa_phandle; 328 genfb_cnattach(); 329 } 330 331 static const struct fdt_console plfb_fdt_console = { 332 .match = plfb_console_match, 333 .consinit = plfb_console_consinit 334 }; 335 336 FDT_CONSOLE(plfb, &plfb_fdt_console); 337
Indexes created Mon Sep 22 13:09:51 GMT 2025