footbridge.c revision 1.1
1 /* $NetBSD: footbridge.c,v 1.1 2001/06/09 10:29:12 chris Exp $ */ 2 3 /* 4 * Copyright (c) 1997,1998 Mark Brinicombe. 5 * Copyright (c) 1997,1998 Causality Limited 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Mark Brinicombe 19 * for the NetBSD Project. 20 * 4. The name of the company nor the name of the author may be used to 21 * endorse or promote products derived from this software without specific 22 * prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 25 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 26 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 28 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 */ 36 37 #include "opt_cputypes.h" 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/kernel.h> 42 #include <sys/conf.h> 43 #include <sys/malloc.h> 44 #include <sys/device.h> 45 46 #include <dev/pci/pcivar.h> 47 #define _ARM32_BUS_DMA_PRIVATE 48 #include <machine/bus.h> 49 #include <machine/irqhandler.h> 50 #include <machine/cpufunc.h> 51 #include <arm/footbridge/footbridgevar.h> 52 #include <arm/footbridge/dc21285reg.h> 53 #include <arm/footbridge/dc21285mem.h> 54 55 /* 56 * DC21285 'Footbridge' device 57 * 58 * This probes and attaches the footbridge device 59 * It then configures any children 60 */ 61 62 /* Declare prototypes */ 63 64 static int footbridge_match __P((struct device *parent, struct cfdata *cf, 65 void *aux)); 66 static void footbridge_attach __P((struct device *parent, struct device *self, 67 void *aux)); 68 static int footbridge_print __P((void *aux, const char *pnp)); 69 static int footbridge_intr __P((void *arg)); 70 void footbridge_sa110_cc_setup __P((void)); 71 72 /* Driver and attach structures */ 73 struct cfattach footbridge_ca = { 74 sizeof(struct footbridge_softc), footbridge_match, footbridge_attach 75 }; 76 77 /* Various bus space tags */ 78 extern struct bus_space footbridge_bs_tag; 79 extern void footbridge_create_io_bs_tag(bus_space_tag_t t, void *cookie); 80 extern void footbridge_create_mem_bs_tag(bus_space_tag_t t, void *cookie); 81 struct bus_space footbridge_csr_tag; 82 struct bus_space footbridge_pci_io_bs_tag; 83 struct bus_space footbridge_pci_mem_bs_tag; 84 extern struct arm32_pci_chipset footbridge_pci_chipset; 85 extern struct arm32_bus_dma_tag footbridge_pci_bus_dma_tag; 86 87 /* Used in footbridge_clock.c */ 88 struct footbridge_softc *clock_sc; 89 90 /* Set to non-zero to enable verbose reporting of footbridge system ints */ 91 int footbridge_intr_report = 0; 92 93 int footbridge_found; 94 95 void 96 footbridge_pci_bs_tag_init(void) 97 { 98 /* Set up the PCI bus tags */ 99 footbridge_create_io_bs_tag(&footbridge_pci_io_bs_tag, 100 (void *)DC21285_PCI_IO_VBASE); 101 footbridge_create_mem_bs_tag(&footbridge_pci_mem_bs_tag, 102 (void *)DC21285_PCI_MEM_BASE); 103 } 104 105 /* 106 * int footbridgeprint(void *aux, const char *name) 107 * 108 * print configuration info for children 109 */ 110 111 static int 112 footbridge_print(aux, pnp) 113 void *aux; 114 const char *pnp; 115 { 116 union footbridge_attach_args *fba = aux; 117 118 if (pnp) 119 printf("%s at %s", fba->fba_name, pnp); 120 if (strcmp(fba->fba_name, "pci") == 0) 121 printf(" bus %d", fba->fba_pba.pba_bus); 122 return(UNCONF); 123 } 124 125 /* 126 * int footbridge_match(struct device *parent, struct cfdata *cf, void *aux) 127 * 128 * Just return ok for this if it is device 0 129 */ 130 131 static int 132 footbridge_match(parent, cf, aux) 133 struct device *parent; 134 struct cfdata *cf; 135 void *aux; 136 { 137 if (footbridge_found) 138 return(0); 139 return(1); 140 } 141 142 143 /* 144 * void footbridge_attach(struct device *parent, struct device *dev, void *aux) 145 * 146 */ 147 148 static void 149 footbridge_attach(parent, self, aux) 150 struct device *parent; 151 struct device *self; 152 void *aux; 153 { 154 struct footbridge_softc *sc = (struct footbridge_softc *)self; 155 union footbridge_attach_args fba; 156 int vendor, device, rev; 157 158 /* There can only be 1 footbridge. */ 159 footbridge_found = 1; 160 161 clock_sc = sc; 162 163 sc->sc_iot = &footbridge_bs_tag; 164 165 /* Map the Footbridge */ 166 if (bus_space_map(sc->sc_iot, DC21285_ARMCSR_VBASE, 167 DC21285_ARMCSR_VSIZE, 0, &sc->sc_ioh)) 168 panic("%s: Cannot map registers\n", self->dv_xname); 169 170 /* Read the ID to make sure it is what we think it is */ 171 vendor = bus_space_read_2(sc->sc_iot, sc->sc_ioh, VENDOR_ID); 172 device = bus_space_read_2(sc->sc_iot, sc->sc_ioh, DEVICE_ID); 173 rev = bus_space_read_1(sc->sc_iot, sc->sc_ioh, REVISION); 174 if (vendor != DC21285_VENDOR_ID && device != DC21285_DEVICE_ID) 175 panic("%s: Unrecognised ID\n", self->dv_xname); 176 177 printf(": DC21285 rev %d\n", rev); 178 179 /* Disable all interrupts from the footbridge */ 180 bus_space_write_4(sc->sc_iot, sc->sc_ioh, IRQ_ENABLE_CLEAR, 0xffffffff); 181 bus_space_write_4(sc->sc_iot, sc->sc_ioh, FIQ_ENABLE_CLEAR, 0xffffffff); 182 183 /* bus_space_write_4(sc->sc_iot, sc->sc_ioh, 0x18, 0x40000000);*/ 184 185 /* Install a generic handler to catch a load of system interrupts */ 186 sc->sc_serr_ih = intr_claim(IRQ_SERR, IPL_NONE, 187 "serr", footbridge_intr, sc); 188 sc->sc_sdram_par_ih = intr_claim(IRQ_SDRAM_PARITY, IPL_NONE, 189 "sdram parity", footbridge_intr, sc); 190 sc->sc_data_par_ih = intr_claim(IRQ_DATA_PARITY, IPL_NONE, 191 "data parity", footbridge_intr, sc); 192 sc->sc_master_abt_ih = intr_claim(IRQ_MASTER_ABORT, IPL_NONE, 193 "mast abt", footbridge_intr, sc); 194 sc->sc_target_abt_ih = intr_claim(IRQ_TARGET_ABORT, IPL_NONE, 195 "targ abt", footbridge_intr, sc); 196 sc->sc_parity_ih = intr_claim(IRQ_PARITY, IPL_NONE, 197 "parity", footbridge_intr, sc); 198 199 /* Set up the PCI bus tags */ 200 footbridge_create_io_bs_tag(&footbridge_pci_io_bs_tag, 201 (void *)DC21285_PCI_IO_VBASE); 202 footbridge_create_mem_bs_tag(&footbridge_pci_mem_bs_tag, 203 (void *)DC21285_PCI_MEM_BASE); 204 205 /* Attach the PCI bus */ 206 fba.fba_pba.pba_busname = "pci"; 207 fba.fba_pba.pba_pc = &footbridge_pci_chipset; 208 fba.fba_pba.pba_iot = &footbridge_pci_io_bs_tag; 209 fba.fba_pba.pba_memt = &footbridge_pci_mem_bs_tag; 210 fba.fba_pba.pba_dmat = &footbridge_pci_bus_dma_tag; 211 fba.fba_pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED; 212 fba.fba_pba.pba_bus = 0; 213 config_found(self, &fba.fba_pba, footbridge_print); 214 215 /* Attach a time-of-day clock device */ 216 fba.fba_tca.ta_name = "todclock"; 217 fba.fba_tca.ta_rtc_arg = NULL; 218 fba.fba_tca.ta_rtc_write = NULL; 219 fba.fba_tca.ta_rtc_read = NULL; 220 fba.fba_tca.ta_flags = TODCLOCK_FLAG_FAKE; 221 config_found(self, &fba.fba_tca, footbridge_print); 222 223 /* Attach uart device */ 224 fba.fba_fca.fca_name = "fcom"; 225 fba.fba_fca.fca_iot = sc->sc_iot; 226 fba.fba_fca.fca_ioh = sc->sc_ioh; 227 fba.fba_fca.fca_rx_irq = IRQ_SERIAL_RX; 228 fba.fba_fca.fca_tx_irq = IRQ_SERIAL_TX; 229 config_found(self, &fba.fba_fca, footbridge_print); 230 231 /* Setup fast SA110 cache clean area */ 232 #ifdef CPU_SA110 233 if (cputype == CPU_ID_SA110) 234 footbridge_sa110_cc_setup(); 235 #endif /* CPU_SA110 */ 236 237 } 238 239 /* Generic footbridge interrupt handler */ 240 241 int 242 footbridge_intr(arg) 243 void *arg; 244 { 245 struct footbridge_softc *sc = arg; 246 u_int ctrl, intr; 247 248 /* 249 * Read the footbridge control register and check for 250 * SERR and parity errors 251 */ 252 ctrl = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SA_CONTROL); 253 intr = ctrl & (RECEIVED_SERR | SA_SDRAM_PARITY_ERROR | 254 PCI_SDRAM_PARITY_ERROR | DMA_SDRAM_PARITY_ERROR); 255 if (intr) { 256 /* Report the interrupt if reporting is enabled */ 257 if (footbridge_intr_report) 258 printf("footbridge_intr: ctrl=%08x\n", intr); 259 /* Clear the interrupt state */ 260 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SA_CONTROL, 261 ctrl | intr); 262 } 263 /* 264 * Read the PCI status register and check for errors 265 */ 266 ctrl = bus_space_read_4(sc->sc_iot, sc->sc_ioh, PCI_COMMAND_STATUS_REG); 267 intr = ctrl & (PCI_STATUS_PARITY_ERROR | PCI_STATUS_MASTER_TARGET_ABORT 268 | PCI_STATUS_MASTER_ABORT | PCI_STATUS_SPECIAL_ERROR 269 | PCI_STATUS_PARITY_DETECT); 270 if (intr) { 271 /* Report the interrupt if reporting is enabled */ 272 if (footbridge_intr_report) 273 printf("footbridge_intr: pcistat=%08x\n", intr); 274 /* Clear the interrupt state */ 275 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 276 PCI_COMMAND_STATUS_REG, ctrl | intr); 277 } 278 return(0); 279 } 280 281 /* End of footbridge.c */ 282
Indexes created Tue Sep 30 06:09:59 GMT 2025