footbridge.c revision 1.17.24.1
1 /* $NetBSD: footbridge.c,v 1.17.24.1 2007/08/11 21:14:49 chris Exp $ */ 2 3 /* 4 * Copyright (c) 1997,1998 Mark Brinicombe. 5 * Copyright (c) 1997,1998 Causality Limited 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Mark Brinicombe 19 * for the NetBSD Project. 20 * 4. The name of the company nor the name of the author may be used to 21 * endorse or promote products derived from this software without specific 22 * prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 25 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 26 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 28 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: footbridge.c,v 1.17.24.1 2007/08/11 21:14:49 chris Exp $"); 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/kernel.h> 43 #include <sys/conf.h> 44 #include <sys/malloc.h> 45 #include <sys/device.h> 46 47 #include <dev/pci/pcivar.h> 48 #define _ARM32_BUS_DMA_PRIVATE 49 #include <machine/bus.h> 50 #include <machine/intr.h> 51 52 #include <arm/cpuconf.h> 53 #include <arm/cpufunc.h> 54 55 #include <arm/footbridge/footbridgevar.h> 56 #include <arm/footbridge/dc21285reg.h> 57 #include <arm/footbridge/dc21285mem.h> 58 #include <arm/footbridge/footbridge.h> 59 60 /* 61 * DC21285 'Footbridge' device 62 * 63 * This probes and attaches the footbridge device 64 * It then configures any children 65 */ 66 67 /* Declare prototypes */ 68 69 static int footbridge_match __P((struct device *parent, struct cfdata *cf, 70 void *aux)); 71 static void footbridge_attach __P((struct device *parent, struct device *self, 72 void *aux)); 73 static int footbridge_print __P((void *aux, const char *pnp)); 74 static int footbridge_intr __P((void *arg)); 75 76 /* Driver and attach structures */ 77 CFATTACH_DECL(footbridge, sizeof(struct footbridge_softc), 78 footbridge_match, footbridge_attach, NULL, NULL); 79 80 /* Various bus space tags */ 81 extern struct bus_space footbridge_bs_tag; 82 extern void footbridge_create_io_bs_tag(bus_space_tag_t t, void *cookie); 83 extern void footbridge_create_mem_bs_tag(bus_space_tag_t t, void *cookie); 84 struct bus_space footbridge_csr_tag; 85 struct bus_space footbridge_pci_io_bs_tag; 86 struct bus_space footbridge_pci_mem_bs_tag; 87 extern struct arm32_pci_chipset footbridge_pci_chipset; 88 extern struct arm32_bus_dma_tag footbridge_pci_bus_dma_tag; 89 90 /* Used in footbridge_clock.c */ 91 struct footbridge_softc *clock_sc; 92 93 /* Set to non-zero to enable verbose reporting of footbridge system ints */ 94 int footbridge_intr_report = 0; 95 96 int footbridge_found; 97 98 void 99 footbridge_pci_bs_tag_init(void) 100 { 101 /* Set up the PCI bus tags */ 102 footbridge_create_io_bs_tag(&footbridge_pci_io_bs_tag, 103 (void *)DC21285_PCI_IO_VBASE); 104 footbridge_create_mem_bs_tag(&footbridge_pci_mem_bs_tag, 105 (void *)DC21285_PCI_MEM_BASE); 106 } 107 108 /* 109 * int footbridgeprint(void *aux, const char *name) 110 * 111 * print configuration info for children 112 */ 113 114 static int 115 footbridge_print(aux, pnp) 116 void *aux; 117 const char *pnp; 118 { 119 union footbridge_attach_args *fba = aux; 120 121 if (pnp) 122 aprint_normal("%s at %s", fba->fba_name, pnp); 123 return(UNCONF); 124 } 125 126 /* 127 * int footbridge_match(struct device *parent, struct cfdata *cf, void *aux) 128 * 129 * Just return ok for this if it is device 0 130 */ 131 132 static int 133 footbridge_match(parent, cf, aux) 134 struct device *parent; 135 struct cfdata *cf; 136 void *aux; 137 { 138 if (footbridge_found) 139 return(0); 140 return(1); 141 } 142 143 144 /* 145 * void footbridge_attach(struct device *parent, struct device *dev, void *aux) 146 * 147 */ 148 149 static void 150 footbridge_attach(parent, self, aux) 151 struct device *parent; 152 struct device *self; 153 void *aux; 154 { 155 struct footbridge_softc *sc = (struct footbridge_softc *)self; 156 union footbridge_attach_args fba; 157 int vendor, device, rev; 158 159 /* There can only be 1 footbridge. */ 160 footbridge_found = 1; 161 162 clock_sc = sc; 163 164 sc->sc_iot = &footbridge_bs_tag; 165 166 /* Map the Footbridge */ 167 if (bus_space_map(sc->sc_iot, DC21285_ARMCSR_VBASE, 168 DC21285_ARMCSR_VSIZE, 0, &sc->sc_ioh)) 169 panic("%s: Cannot map registers", self->dv_xname); 170 171 /* Read the ID to make sure it is what we think it is */ 172 vendor = bus_space_read_2(sc->sc_iot, sc->sc_ioh, VENDOR_ID); 173 device = bus_space_read_2(sc->sc_iot, sc->sc_ioh, DEVICE_ID); 174 rev = bus_space_read_1(sc->sc_iot, sc->sc_ioh, REVISION); 175 if (vendor != DC21285_VENDOR_ID && device != DC21285_DEVICE_ID) 176 panic("%s: Unrecognised ID", self->dv_xname); 177 178 printf(": DC21285 rev %d\n", rev); 179 180 /* Disable all interrupts from the footbridge */ 181 bus_space_write_4(sc->sc_iot, sc->sc_ioh, IRQ_ENABLE_CLEAR, 0xffffffff); 182 bus_space_write_4(sc->sc_iot, sc->sc_ioh, FIQ_ENABLE_CLEAR, 0xffffffff); 183 184 /* setup footbridge irqs */ 185 footbridge_intr_init(); 186 187 /* bus_space_write_4(sc->sc_iot, sc->sc_ioh, 0x18, 0x40000000);*/ 188 189 /* Install a generic handler to catch a load of system interrupts */ 190 sc->sc_serr_ih = footbridge_intr_claim(IRQ_SERR, IPL_HIGH, 191 "serr", footbridge_intr, sc); 192 sc->sc_sdram_par_ih = footbridge_intr_claim(IRQ_SDRAM_PARITY, IPL_HIGH, 193 "sdram parity", footbridge_intr, sc); 194 sc->sc_data_par_ih = footbridge_intr_claim(IRQ_DATA_PARITY, IPL_HIGH, 195 "data parity", footbridge_intr, sc); 196 sc->sc_master_abt_ih = footbridge_intr_claim(IRQ_MASTER_ABORT, IPL_HIGH, 197 "mast abt", footbridge_intr, sc); 198 sc->sc_target_abt_ih = footbridge_intr_claim(IRQ_TARGET_ABORT, IPL_HIGH, 199 "targ abt", footbridge_intr, sc); 200 sc->sc_parity_ih = footbridge_intr_claim(IRQ_PARITY, IPL_HIGH, 201 "parity", footbridge_intr, sc); 202 203 /* Set up the PCI bus tags */ 204 footbridge_create_io_bs_tag(&footbridge_pci_io_bs_tag, 205 (void *)DC21285_PCI_IO_VBASE); 206 footbridge_create_mem_bs_tag(&footbridge_pci_mem_bs_tag, 207 (void *)DC21285_PCI_MEM_BASE); 208 209 /* calibrate the delay loop */ 210 calibrate_delay(); 211 /* Attach the PCI bus */ 212 fba.fba_pba.pba_pc = &footbridge_pci_chipset; 213 fba.fba_pba.pba_iot = &footbridge_pci_io_bs_tag; 214 fba.fba_pba.pba_memt = &footbridge_pci_mem_bs_tag; 215 fba.fba_pba.pba_dmat = &footbridge_pci_bus_dma_tag; 216 fba.fba_pba.pba_dmat64 = NULL; 217 fba.fba_pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED; 218 fba.fba_pba.pba_bus = 0; 219 fba.fba_pba.pba_bridgetag = NULL; 220 config_found_ia(self, "pcibus", &fba.fba_pba, pcibusprint); 221 222 /* Attach uart device */ 223 fba.fba_fca.fca_name = "fcom"; 224 fba.fba_fca.fca_iot = sc->sc_iot; 225 fba.fba_fca.fca_ioh = sc->sc_ioh; 226 fba.fba_fca.fca_rx_irq = IRQ_SERIAL_RX; 227 fba.fba_fca.fca_tx_irq = IRQ_SERIAL_TX; 228 config_found_ia(self, "footbridge", &fba.fba_fca, footbridge_print); 229 230 /* Setup fast SA110 cache clean area */ 231 #ifdef CPU_SA110 232 if (cputype == CPU_ID_SA110) 233 footbridge_sa110_cc_setup(); 234 #endif /* CPU_SA110 */ 235 236 } 237 238 /* Generic footbridge interrupt handler */ 239 240 int 241 footbridge_intr(arg) 242 void *arg; 243 { 244 struct footbridge_softc *sc = arg; 245 u_int ctrl, intr; 246 247 /* 248 * Read the footbridge control register and check for 249 * SERR and parity errors 250 */ 251 ctrl = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SA_CONTROL); 252 intr = ctrl & (RECEIVED_SERR | SA_SDRAM_PARITY_ERROR | 253 PCI_SDRAM_PARITY_ERROR | DMA_SDRAM_PARITY_ERROR); 254 if (intr) { 255 /* Report the interrupt if reporting is enabled */ 256 if (footbridge_intr_report) 257 printf("footbridge_intr: ctrl=%08x\n", intr); 258 /* Clear the interrupt state */ 259 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SA_CONTROL, 260 ctrl | intr); 261 } 262 /* 263 * Read the PCI status register and check for errors 264 */ 265 ctrl = bus_space_read_4(sc->sc_iot, sc->sc_ioh, PCI_COMMAND_STATUS_REG); 266 intr = ctrl & (PCI_STATUS_PARITY_ERROR | PCI_STATUS_MASTER_TARGET_ABORT 267 | PCI_STATUS_MASTER_ABORT | PCI_STATUS_SPECIAL_ERROR 268 | PCI_STATUS_PARITY_DETECT); 269 if (intr) { 270 /* Report the interrupt if reporting is enabled */ 271 if (footbridge_intr_report) 272 printf("footbridge_intr: pcistat=%08x\n", intr); 273 /* Clear the interrupt state */ 274 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 275 PCI_COMMAND_STATUS_REG, ctrl | intr); 276 } 277 return(0); 278 } 279 280 /* End of footbridge.c */ 281
Indexes created Wed Oct 29 03:09:52 GMT 2025