footbridge.c revision 1.20
1 /* $NetBSD: footbridge.c,v 1.20 2009/03/14 15:36:02 dsl Exp $ */ 2 3 /* 4 * Copyright (c) 1997,1998 Mark Brinicombe. 5 * Copyright (c) 1997,1998 Causality Limited 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Mark Brinicombe 19 * for the NetBSD Project. 20 * 4. The name of the company nor the name of the author may be used to 21 * endorse or promote products derived from this software without specific 22 * prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 25 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 26 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 28 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: footbridge.c,v 1.20 2009/03/14 15:36:02 dsl Exp $"); 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/kernel.h> 43 #include <sys/conf.h> 44 #include <sys/malloc.h> 45 #include <sys/device.h> 46 #include <uvm/uvm_extern.h> 47 48 #include <dev/pci/pcivar.h> 49 #define _ARM32_BUS_DMA_PRIVATE 50 #include <machine/bus.h> 51 #include <machine/intr.h> 52 #include <machine/bootconfig.h> 53 54 #include <arm/cpuconf.h> 55 #include <arm/cpufunc.h> 56 57 #include <arm/footbridge/footbridgevar.h> 58 #include <arm/footbridge/dc21285reg.h> 59 #include <arm/footbridge/dc21285mem.h> 60 #include <arm/footbridge/footbridge.h> 61 62 /* 63 * DC21285 'Footbridge' device 64 * 65 * This probes and attaches the footbridge device 66 * It then configures any children 67 */ 68 69 /* Declare prototypes */ 70 71 static int footbridge_match(struct device *parent, struct cfdata *cf, 72 void *aux); 73 static void footbridge_attach(struct device *parent, struct device *self, 74 void *aux); 75 static int footbridge_print(void *aux, const char *pnp); 76 static int footbridge_intr(void *arg); 77 78 /* Driver and attach structures */ 79 CFATTACH_DECL(footbridge, sizeof(struct footbridge_softc), 80 footbridge_match, footbridge_attach, NULL, NULL); 81 82 /* Various bus space tags */ 83 extern struct bus_space footbridge_bs_tag; 84 extern void footbridge_create_io_bs_tag(bus_space_tag_t t, void *cookie); 85 extern void footbridge_create_mem_bs_tag(bus_space_tag_t t, void *cookie); 86 struct bus_space footbridge_csr_tag; 87 struct bus_space footbridge_pci_io_bs_tag; 88 struct bus_space footbridge_pci_mem_bs_tag; 89 extern struct arm32_pci_chipset footbridge_pci_chipset; 90 extern struct arm32_bus_dma_tag footbridge_pci_bus_dma_tag; 91 extern struct arm32_dma_range footbridge_dma_ranges[1]; 92 93 /* Used in footbridge_clock.c */ 94 struct footbridge_softc *clock_sc; 95 96 /* Set to non-zero to enable verbose reporting of footbridge system ints */ 97 int footbridge_intr_report = 0; 98 99 int footbridge_found; 100 101 void 102 footbridge_pci_bs_tag_init(void) 103 { 104 /* Set up the PCI bus tags */ 105 footbridge_create_io_bs_tag(&footbridge_pci_io_bs_tag, 106 (void *)DC21285_PCI_IO_VBASE); 107 footbridge_create_mem_bs_tag(&footbridge_pci_mem_bs_tag, 108 (void *)DC21285_PCI_MEM_BASE); 109 } 110 111 /* 112 * int footbridgeprint(void *aux, const char *name) 113 * 114 * print configuration info for children 115 */ 116 117 static int 118 footbridge_print(void *aux, const char *pnp) 119 { 120 union footbridge_attach_args *fba = aux; 121 122 if (pnp) 123 aprint_normal("%s at %s", fba->fba_name, pnp); 124 return(UNCONF); 125 } 126 127 /* 128 * int footbridge_match(struct device *parent, struct cfdata *cf, void *aux) 129 * 130 * Just return ok for this if it is device 0 131 */ 132 133 static int 134 footbridge_match(struct device *parent, struct cfdata *cf, void *aux) 135 { 136 if (footbridge_found) 137 return(0); 138 return(1); 139 } 140 141 142 /* 143 * void footbridge_attach(struct device *parent, struct device *dev, void *aux) 144 * 145 */ 146 147 static void 148 footbridge_attach(struct device *parent, struct device *self, void *aux) 149 { 150 struct footbridge_softc *sc = (struct footbridge_softc *)self; 151 union footbridge_attach_args fba; 152 int vendor, device, rev; 153 154 /* There can only be 1 footbridge. */ 155 footbridge_found = 1; 156 157 clock_sc = sc; 158 159 sc->sc_iot = &footbridge_bs_tag; 160 161 /* Map the Footbridge */ 162 if (bus_space_map(sc->sc_iot, DC21285_ARMCSR_VBASE, 163 DC21285_ARMCSR_VSIZE, 0, &sc->sc_ioh)) 164 panic("%s: Cannot map registers", self->dv_xname); 165 166 /* Read the ID to make sure it is what we think it is */ 167 vendor = bus_space_read_2(sc->sc_iot, sc->sc_ioh, VENDOR_ID); 168 device = bus_space_read_2(sc->sc_iot, sc->sc_ioh, DEVICE_ID); 169 rev = bus_space_read_1(sc->sc_iot, sc->sc_ioh, REVISION); 170 if (vendor != DC21285_VENDOR_ID && device != DC21285_DEVICE_ID) 171 panic("%s: Unrecognised ID", self->dv_xname); 172 173 printf(": DC21285 rev %d\n", rev); 174 175 /* Disable all interrupts from the footbridge */ 176 bus_space_write_4(sc->sc_iot, sc->sc_ioh, IRQ_ENABLE_CLEAR, 0xffffffff); 177 bus_space_write_4(sc->sc_iot, sc->sc_ioh, FIQ_ENABLE_CLEAR, 0xffffffff); 178 179 /* bus_space_write_4(sc->sc_iot, sc->sc_ioh, 0x18, 0x40000000);*/ 180 181 /* Install a generic handler to catch a load of system interrupts */ 182 sc->sc_serr_ih = footbridge_intr_claim(IRQ_SERR, IPL_HIGH, 183 "serr", footbridge_intr, sc); 184 sc->sc_sdram_par_ih = footbridge_intr_claim(IRQ_SDRAM_PARITY, IPL_HIGH, 185 "sdram parity", footbridge_intr, sc); 186 sc->sc_data_par_ih = footbridge_intr_claim(IRQ_DATA_PARITY, IPL_HIGH, 187 "data parity", footbridge_intr, sc); 188 sc->sc_master_abt_ih = footbridge_intr_claim(IRQ_MASTER_ABORT, IPL_HIGH, 189 "mast abt", footbridge_intr, sc); 190 sc->sc_target_abt_ih = footbridge_intr_claim(IRQ_TARGET_ABORT, IPL_HIGH, 191 "targ abt", footbridge_intr, sc); 192 sc->sc_parity_ih = footbridge_intr_claim(IRQ_PARITY, IPL_HIGH, 193 "parity", footbridge_intr, sc); 194 195 /* Set up the PCI bus tags */ 196 footbridge_create_io_bs_tag(&footbridge_pci_io_bs_tag, 197 (void *)DC21285_PCI_IO_VBASE); 198 footbridge_create_mem_bs_tag(&footbridge_pci_mem_bs_tag, 199 (void *)DC21285_PCI_MEM_BASE); 200 201 /* calibrate the delay loop */ 202 calibrate_delay(); 203 204 /* it seems that the default of the memory being visible from 0 upwards 205 * on the PCI bus causes issues when DMAing from traditional PC VGA 206 * address. This breaks dumping core on cats, as DMAing pages in the 207 * range 0xb800-0xc000 cause the system to hang. This suggests that 208 * the VGA BIOS is taking over those addresses. 209 * (note that the range 0xb800-c000 is on an S3 card, others may vary 210 * 211 * To workaround this the SDRAM window on the PCI bus is shifted 212 * to 0x20000000, and the DMA range setup to match. 213 */ 214 { 215 /* first calculate the correct base address mask */ 216 int memory_size = bootconfig.dram[0].pages * PAGE_SIZE; 217 uint32_t mask; 218 219 /* window has to be at least 256KB, and up to 256MB */ 220 for (mask = 0x00040000; mask < 0x10000000; mask <<= 1) 221 if (mask >= memory_size) 222 break; 223 mask--; 224 mask &= SDRAM_MASK_256MB; 225 226 /* 227 * configure the mask, the offset into SDRAM and the address 228 * SDRAM is exposed on the PCI bus. 229 */ 230 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SDRAM_BA_MASK, mask); 231 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SDRAM_BA_OFFSET, 0); 232 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SDRAM_MEMORY_ADDR, 0x20000000); 233 234 /* configure the dma range for the footbridge to match */ 235 footbridge_dma_ranges[0].dr_sysbase = bootconfig.dram[0].address; 236 footbridge_dma_ranges[0].dr_busbase = 0x20000000; 237 footbridge_dma_ranges[0].dr_len = memory_size; 238 } 239 240 /* Attach the PCI bus */ 241 fba.fba_pba.pba_pc = &footbridge_pci_chipset; 242 fba.fba_pba.pba_iot = &footbridge_pci_io_bs_tag; 243 fba.fba_pba.pba_memt = &footbridge_pci_mem_bs_tag; 244 fba.fba_pba.pba_dmat = &footbridge_pci_bus_dma_tag; 245 fba.fba_pba.pba_dmat64 = NULL; 246 fba.fba_pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED; 247 fba.fba_pba.pba_bus = 0; 248 fba.fba_pba.pba_bridgetag = NULL; 249 config_found_ia(self, "pcibus", &fba.fba_pba, pcibusprint); 250 251 /* Attach uart device */ 252 fba.fba_fca.fca_name = "fcom"; 253 fba.fba_fca.fca_iot = sc->sc_iot; 254 fba.fba_fca.fca_ioh = sc->sc_ioh; 255 fba.fba_fca.fca_rx_irq = IRQ_SERIAL_RX; 256 fba.fba_fca.fca_tx_irq = IRQ_SERIAL_TX; 257 config_found_ia(self, "footbridge", &fba.fba_fca, footbridge_print); 258 259 /* Setup fast SA110 cache clean area */ 260 #ifdef CPU_SA110 261 if (cputype == CPU_ID_SA110) 262 footbridge_sa110_cc_setup(); 263 #endif /* CPU_SA110 */ 264 265 } 266 267 /* Generic footbridge interrupt handler */ 268 269 int 270 footbridge_intr(void *arg) 271 { 272 struct footbridge_softc *sc = arg; 273 u_int ctrl, intr; 274 275 /* 276 * Read the footbridge control register and check for 277 * SERR and parity errors 278 */ 279 ctrl = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SA_CONTROL); 280 intr = ctrl & (RECEIVED_SERR | SA_SDRAM_PARITY_ERROR | 281 PCI_SDRAM_PARITY_ERROR | DMA_SDRAM_PARITY_ERROR); 282 if (intr) { 283 /* Report the interrupt if reporting is enabled */ 284 if (footbridge_intr_report) 285 printf("footbridge_intr: ctrl=%08x\n", intr); 286 /* Clear the interrupt state */ 287 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SA_CONTROL, 288 ctrl | intr); 289 } 290 /* 291 * Read the PCI status register and check for errors 292 */ 293 ctrl = bus_space_read_4(sc->sc_iot, sc->sc_ioh, PCI_COMMAND_STATUS_REG); 294 intr = ctrl & (PCI_STATUS_PARITY_ERROR | PCI_STATUS_MASTER_TARGET_ABORT 295 | PCI_STATUS_MASTER_ABORT | PCI_STATUS_SPECIAL_ERROR 296 | PCI_STATUS_PARITY_DETECT); 297 if (intr) { 298 /* Report the interrupt if reporting is enabled */ 299 if (footbridge_intr_report) 300 printf("footbridge_intr: pcistat=%08x\n", intr); 301 /* Clear the interrupt state */ 302 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 303 PCI_COMMAND_STATUS_REG, ctrl | intr); 304 } 305 return(0); 306 } 307 308 /* End of footbridge.c */ 309
Indexes created Tue Sep 30 20:09:53 GMT 2025