footbridge.c revision 1.3
1 /* $NetBSD: footbridge.c,v 1.3 2001/11/23 19:21:47 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1997,1998 Mark Brinicombe. 5 * Copyright (c) 1997,1998 Causality Limited 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Mark Brinicombe 19 * for the NetBSD Project. 20 * 4. The name of the company nor the name of the author may be used to 21 * endorse or promote products derived from this software without specific 22 * prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 25 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 26 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 28 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 */ 36 37 #include "opt_cputypes.h" 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/kernel.h> 42 #include <sys/conf.h> 43 #include <sys/malloc.h> 44 #include <sys/device.h> 45 46 #include <dev/pci/pcivar.h> 47 #define _ARM32_BUS_DMA_PRIVATE 48 #include <machine/bus.h> 49 #include <machine/intr.h> 50 51 #include <arm/cpufunc.h> 52 53 #include <arm/footbridge/footbridgevar.h> 54 #include <arm/footbridge/dc21285reg.h> 55 #include <arm/footbridge/dc21285mem.h> 56 57 /* 58 * DC21285 'Footbridge' device 59 * 60 * This probes and attaches the footbridge device 61 * It then configures any children 62 */ 63 64 /* Declare prototypes */ 65 66 static int footbridge_match __P((struct device *parent, struct cfdata *cf, 67 void *aux)); 68 static void footbridge_attach __P((struct device *parent, struct device *self, 69 void *aux)); 70 static int footbridge_print __P((void *aux, const char *pnp)); 71 static int footbridge_intr __P((void *arg)); 72 void footbridge_sa110_cc_setup __P((void)); 73 74 /* Driver and attach structures */ 75 struct cfattach footbridge_ca = { 76 sizeof(struct footbridge_softc), footbridge_match, footbridge_attach 77 }; 78 79 /* Various bus space tags */ 80 extern struct bus_space footbridge_bs_tag; 81 extern void footbridge_create_io_bs_tag(bus_space_tag_t t, void *cookie); 82 extern void footbridge_create_mem_bs_tag(bus_space_tag_t t, void *cookie); 83 struct bus_space footbridge_csr_tag; 84 struct bus_space footbridge_pci_io_bs_tag; 85 struct bus_space footbridge_pci_mem_bs_tag; 86 extern struct arm32_pci_chipset footbridge_pci_chipset; 87 extern struct arm32_bus_dma_tag footbridge_pci_bus_dma_tag; 88 89 /* Used in footbridge_clock.c */ 90 struct footbridge_softc *clock_sc; 91 92 /* Set to non-zero to enable verbose reporting of footbridge system ints */ 93 int footbridge_intr_report = 0; 94 95 int footbridge_found; 96 97 void 98 footbridge_pci_bs_tag_init(void) 99 { 100 /* Set up the PCI bus tags */ 101 footbridge_create_io_bs_tag(&footbridge_pci_io_bs_tag, 102 (void *)DC21285_PCI_IO_VBASE); 103 footbridge_create_mem_bs_tag(&footbridge_pci_mem_bs_tag, 104 (void *)DC21285_PCI_MEM_BASE); 105 } 106 107 /* 108 * int footbridgeprint(void *aux, const char *name) 109 * 110 * print configuration info for children 111 */ 112 113 static int 114 footbridge_print(aux, pnp) 115 void *aux; 116 const char *pnp; 117 { 118 union footbridge_attach_args *fba = aux; 119 120 if (pnp) 121 printf("%s at %s", fba->fba_name, pnp); 122 if (strcmp(fba->fba_name, "pci") == 0) 123 printf(" bus %d", fba->fba_pba.pba_bus); 124 return(UNCONF); 125 } 126 127 /* 128 * int footbridge_match(struct device *parent, struct cfdata *cf, void *aux) 129 * 130 * Just return ok for this if it is device 0 131 */ 132 133 static int 134 footbridge_match(parent, cf, aux) 135 struct device *parent; 136 struct cfdata *cf; 137 void *aux; 138 { 139 if (footbridge_found) 140 return(0); 141 return(1); 142 } 143 144 145 /* 146 * void footbridge_attach(struct device *parent, struct device *dev, void *aux) 147 * 148 */ 149 150 static void 151 footbridge_attach(parent, self, aux) 152 struct device *parent; 153 struct device *self; 154 void *aux; 155 { 156 struct footbridge_softc *sc = (struct footbridge_softc *)self; 157 union footbridge_attach_args fba; 158 int vendor, device, rev; 159 160 /* There can only be 1 footbridge. */ 161 footbridge_found = 1; 162 163 clock_sc = sc; 164 165 sc->sc_iot = &footbridge_bs_tag; 166 167 /* Map the Footbridge */ 168 if (bus_space_map(sc->sc_iot, DC21285_ARMCSR_VBASE, 169 DC21285_ARMCSR_VSIZE, 0, &sc->sc_ioh)) 170 panic("%s: Cannot map registers\n", self->dv_xname); 171 172 /* Read the ID to make sure it is what we think it is */ 173 vendor = bus_space_read_2(sc->sc_iot, sc->sc_ioh, VENDOR_ID); 174 device = bus_space_read_2(sc->sc_iot, sc->sc_ioh, DEVICE_ID); 175 rev = bus_space_read_1(sc->sc_iot, sc->sc_ioh, REVISION); 176 if (vendor != DC21285_VENDOR_ID && device != DC21285_DEVICE_ID) 177 panic("%s: Unrecognised ID\n", self->dv_xname); 178 179 printf(": DC21285 rev %d\n", rev); 180 181 /* Disable all interrupts from the footbridge */ 182 bus_space_write_4(sc->sc_iot, sc->sc_ioh, IRQ_ENABLE_CLEAR, 0xffffffff); 183 bus_space_write_4(sc->sc_iot, sc->sc_ioh, FIQ_ENABLE_CLEAR, 0xffffffff); 184 185 /* bus_space_write_4(sc->sc_iot, sc->sc_ioh, 0x18, 0x40000000);*/ 186 187 /* Install a generic handler to catch a load of system interrupts */ 188 sc->sc_serr_ih = intr_claim(IRQ_SERR, IPL_NONE, 189 "serr", footbridge_intr, sc); 190 sc->sc_sdram_par_ih = intr_claim(IRQ_SDRAM_PARITY, IPL_NONE, 191 "sdram parity", footbridge_intr, sc); 192 sc->sc_data_par_ih = intr_claim(IRQ_DATA_PARITY, IPL_NONE, 193 "data parity", footbridge_intr, sc); 194 sc->sc_master_abt_ih = intr_claim(IRQ_MASTER_ABORT, IPL_NONE, 195 "mast abt", footbridge_intr, sc); 196 sc->sc_target_abt_ih = intr_claim(IRQ_TARGET_ABORT, IPL_NONE, 197 "targ abt", footbridge_intr, sc); 198 sc->sc_parity_ih = intr_claim(IRQ_PARITY, IPL_NONE, 199 "parity", footbridge_intr, sc); 200 201 /* Set up the PCI bus tags */ 202 footbridge_create_io_bs_tag(&footbridge_pci_io_bs_tag, 203 (void *)DC21285_PCI_IO_VBASE); 204 footbridge_create_mem_bs_tag(&footbridge_pci_mem_bs_tag, 205 (void *)DC21285_PCI_MEM_BASE); 206 207 /* Attach the PCI bus */ 208 fba.fba_pba.pba_busname = "pci"; 209 fba.fba_pba.pba_pc = &footbridge_pci_chipset; 210 fba.fba_pba.pba_iot = &footbridge_pci_io_bs_tag; 211 fba.fba_pba.pba_memt = &footbridge_pci_mem_bs_tag; 212 fba.fba_pba.pba_dmat = &footbridge_pci_bus_dma_tag; 213 fba.fba_pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED; 214 fba.fba_pba.pba_bus = 0; 215 config_found(self, &fba.fba_pba, footbridge_print); 216 217 /* Attach a time-of-day clock device */ 218 fba.fba_tca.ta_name = "todclock"; 219 fba.fba_tca.ta_rtc_arg = NULL; 220 fba.fba_tca.ta_rtc_write = NULL; 221 fba.fba_tca.ta_rtc_read = NULL; 222 fba.fba_tca.ta_flags = TODCLOCK_FLAG_FAKE; 223 config_found(self, &fba.fba_tca, footbridge_print); 224 225 /* Attach uart device */ 226 fba.fba_fca.fca_name = "fcom"; 227 fba.fba_fca.fca_iot = sc->sc_iot; 228 fba.fba_fca.fca_ioh = sc->sc_ioh; 229 fba.fba_fca.fca_rx_irq = IRQ_SERIAL_RX; 230 fba.fba_fca.fca_tx_irq = IRQ_SERIAL_TX; 231 config_found(self, &fba.fba_fca, footbridge_print); 232 233 /* Setup fast SA110 cache clean area */ 234 #ifdef CPU_SA110 235 if (cputype == CPU_ID_SA110) 236 footbridge_sa110_cc_setup(); 237 #endif /* CPU_SA110 */ 238 239 } 240 241 /* Generic footbridge interrupt handler */ 242 243 int 244 footbridge_intr(arg) 245 void *arg; 246 { 247 struct footbridge_softc *sc = arg; 248 u_int ctrl, intr; 249 250 /* 251 * Read the footbridge control register and check for 252 * SERR and parity errors 253 */ 254 ctrl = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SA_CONTROL); 255 intr = ctrl & (RECEIVED_SERR | SA_SDRAM_PARITY_ERROR | 256 PCI_SDRAM_PARITY_ERROR | DMA_SDRAM_PARITY_ERROR); 257 if (intr) { 258 /* Report the interrupt if reporting is enabled */ 259 if (footbridge_intr_report) 260 printf("footbridge_intr: ctrl=%08x\n", intr); 261 /* Clear the interrupt state */ 262 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SA_CONTROL, 263 ctrl | intr); 264 } 265 /* 266 * Read the PCI status register and check for errors 267 */ 268 ctrl = bus_space_read_4(sc->sc_iot, sc->sc_ioh, PCI_COMMAND_STATUS_REG); 269 intr = ctrl & (PCI_STATUS_PARITY_ERROR | PCI_STATUS_MASTER_TARGET_ABORT 270 | PCI_STATUS_MASTER_ABORT | PCI_STATUS_SPECIAL_ERROR 271 | PCI_STATUS_PARITY_DETECT); 272 if (intr) { 273 /* Report the interrupt if reporting is enabled */ 274 if (footbridge_intr_report) 275 printf("footbridge_intr: pcistat=%08x\n", intr); 276 /* Clear the interrupt state */ 277 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 278 PCI_COMMAND_STATUS_REG, ctrl | intr); 279 } 280 return(0); 281 } 282 283 /* End of footbridge.c */ 284
Indexes created Tue Sep 30 06:09:59 GMT 2025