gemini_gmac.c revision 1.14
1 /* $NetBSD: gemini_gmac.c,v 1.14 2018/04/26 19:33:02 maxv Exp $ */ 2 /*- 3 * Copyright (c) 2008 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Matt Thomas <matt (at) 3am-software.com> 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 19 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 20 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 21 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include "locators.h" 32 #include <sys/param.h> 33 #include <sys/device.h> 34 #include <sys/kmem.h> 35 #include <sys/mbuf.h> 36 37 #include <net/if.h> 38 #include <net/if_ether.h> 39 40 #include <sys/bus.h> 41 42 #include <arm/gemini/gemini_reg.h> 43 #include <arm/gemini/gemini_obiovar.h> 44 #include <arm/gemini/gemini_gmacvar.h> 45 #include <arm/gemini/gemini_gpiovar.h> 46 47 #include <dev/mii/mii.h> 48 #include <dev/mii/mii_bitbang.h> 49 50 #include <sys/gpio.h> 51 52 __KERNEL_RCSID(0, "$NetBSD: gemini_gmac.c,v 1.14 2018/04/26 19:33:02 maxv Exp $"); 53 54 #define SWFREEQ_DESCS 256 /* one page worth */ 55 #define HWFREEQ_DESCS 256 /* one page worth */ 56 57 static int geminigmac_match(device_t, cfdata_t, void *); 58 static void geminigmac_attach(device_t, device_t, void *); 59 static int geminigmac_find(device_t, cfdata_t, const int *, void *); 60 static int geminigmac_print(void *aux, const char *name); 61 62 static int geminigmac_mii_readreg(device_t, int, int); 63 static void geminigmac_mii_writereg(device_t, int, int, int); 64 65 #define GPIO_MDIO 21 66 #define GPIO_MDCLK 22 67 68 #define MDIN __BIT(3) 69 #define MDOUT __BIT(2) 70 #define MDCLK __BIT(1) 71 #define MDTOPHY __BIT(0) 72 73 CFATTACH_DECL_NEW(geminigmac, sizeof(struct gmac_softc), 74 geminigmac_match, geminigmac_attach, NULL, NULL); 75 76 extern struct cfdriver geminigmac_cd; 77 extern struct cfdriver geminigpio_cd; 78 79 void 80 gmac_swfree_min_update(struct gmac_softc *sc) 81 { 82 uint32_t v; 83 84 if (sc->sc_swfreeq != NULL 85 && sc->sc_swfree_min > sc->sc_swfreeq->hwq_size - 1) 86 sc->sc_swfree_min = sc->sc_swfreeq->hwq_size - 1; 87 88 v = bus_space_read_4(sc->sc_iot, sc->sc_ioh, GMAC_QFE_THRESHOLD); 89 v &= ~QFE_SWFQ_THRESHOLD_MASK; 90 v |= QFE_SWFQ_THRESHOLD(sc->sc_swfree_min); 91 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GMAC_QFE_THRESHOLD, v); 92 } 93 94 void 95 gmac_intr_update(struct gmac_softc *sc) 96 { 97 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GMAC_INT0_MASK, 98 ~sc->sc_int_enabled[0]); 99 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GMAC_INT1_MASK, 100 ~sc->sc_int_enabled[1]); 101 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GMAC_INT2_MASK, 102 ~sc->sc_int_enabled[2]); 103 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GMAC_INT3_MASK, 104 ~sc->sc_int_enabled[3]); 105 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GMAC_INT4_MASK, 106 ~sc->sc_int_enabled[4]); 107 } 108 109 static void 110 gmac_init(struct gmac_softc *sc) 111 { 112 gmac_hwqmem_t *hqm; 113 114 /* 115 * This shouldn't be needed. 116 */ 117 for (bus_size_t i = 0; i < GMAC_TOE_QH_SIZE; i += 4) { 118 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 119 GMAC_TOE_QH_OFFSET + i, 0); 120 } 121 #if 0 122 { 123 bus_space_handle_t global_ioh; 124 int error; 125 126 error = bus_space_map(sc->sc_iot, GEMINI_GLOBAL_BASE, 4, 0, 127 &global_ioh); 128 KASSERT(error == 0); 129 aprint_normal_dev(sc->sc_dev, "gmac_init: global_ioh=%#zx\n", global_ioh); 130 bus_space_write_4(sc->sc_iot, global_ioh, GEMINI_GLOBAL_RESET_CTL, 131 GLOBAL_RESET_GMAC0|GLOBAL_RESET_GMAC1); 132 do { 133 v = bus_space_read_4(sc->sc_iot, global_ioh, 134 GEMINI_GLOBAL_RESET_CTL); 135 } while (v & (GLOBAL_RESET_GMAC0|GLOBAL_RESET_GMAC1)); 136 bus_space_unmap(sc->sc_iot, global_ioh, 4); 137 DELAY(1000); 138 } 139 #endif 140 141 sc->sc_swfree_min = 4; /* MIN_RXMAPS; */ 142 143 gmac_swfree_min_update(sc); 144 145 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GMAC_SKBSIZE, 146 SKB_SIZE_SET(PAGE_SIZE, MCLBYTES)); 147 148 sc->sc_int_select[0] = INT0_GMAC1; 149 sc->sc_int_select[1] = INT1_GMAC1; 150 sc->sc_int_select[2] = INT2_GMAC1; 151 sc->sc_int_select[3] = INT3_GMAC1; 152 sc->sc_int_select[4] = INT4_GMAC1; 153 154 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GMAC_INT0_SELECT, INT0_GMAC1); 155 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GMAC_INT1_SELECT, INT1_GMAC1); 156 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GMAC_INT2_SELECT, INT2_GMAC1); 157 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GMAC_INT3_SELECT, INT3_GMAC1); 158 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GMAC_INT4_SELECT, INT4_GMAC1); 159 160 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GMAC_INT0_STATUS, ~0); 161 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GMAC_INT1_STATUS, ~0); 162 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GMAC_INT2_STATUS, ~0); 163 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GMAC_INT3_STATUS, ~0); 164 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GMAC_INT4_STATUS, ~0); 165 166 gmac_intr_update(sc); 167 168 aprint_debug_dev(sc->sc_dev, "gmac_init: sts=%#x/%#x/%#x/%#x/%#x\n", 169 bus_space_read_4(sc->sc_iot, sc->sc_ioh, GMAC_INT0_STATUS), 170 bus_space_read_4(sc->sc_iot, sc->sc_ioh, GMAC_INT1_STATUS), 171 bus_space_read_4(sc->sc_iot, sc->sc_ioh, GMAC_INT2_STATUS), 172 bus_space_read_4(sc->sc_iot, sc->sc_ioh, GMAC_INT3_STATUS), 173 bus_space_read_4(sc->sc_iot, sc->sc_ioh, GMAC_INT4_STATUS)); 174 175 aprint_debug_dev(sc->sc_dev, "gmac_init: mask=%#x/%#x/%#x/%#x/%#x\n", 176 bus_space_read_4(sc->sc_iot, sc->sc_ioh, GMAC_INT0_MASK), 177 bus_space_read_4(sc->sc_iot, sc->sc_ioh, GMAC_INT1_MASK), 178 bus_space_read_4(sc->sc_iot, sc->sc_ioh, GMAC_INT2_MASK), 179 bus_space_read_4(sc->sc_iot, sc->sc_ioh, GMAC_INT3_MASK), 180 bus_space_read_4(sc->sc_iot, sc->sc_ioh, GMAC_INT4_MASK)); 181 182 aprint_debug_dev(sc->sc_dev, "gmac_init: select=%#x/%#x/%#x/%#x/%#x\n", 183 bus_space_read_4(sc->sc_iot, sc->sc_ioh, GMAC_INT0_SELECT), 184 bus_space_read_4(sc->sc_iot, sc->sc_ioh, GMAC_INT1_SELECT), 185 bus_space_read_4(sc->sc_iot, sc->sc_ioh, GMAC_INT2_SELECT), 186 bus_space_read_4(sc->sc_iot, sc->sc_ioh, GMAC_INT3_SELECT), 187 bus_space_read_4(sc->sc_iot, sc->sc_ioh, GMAC_INT4_SELECT)); 188 189 aprint_debug_dev(sc->sc_dev, "gmac_init: create rx dmamap cache\n"); 190 /* 191 * Allocate the cache for receive dmamaps. 192 */ 193 sc->sc_rxmaps = gmac_mapcache_create(sc->sc_dmat, MAX_RXMAPS, 194 MCLBYTES, 1); 195 KASSERT(sc->sc_rxmaps != NULL); 196 197 aprint_debug_dev(sc->sc_dev, "gmac_init: create tx dmamap cache\n"); 198 /* 199 * Allocate the cache for transmit dmamaps. 200 */ 201 sc->sc_txmaps = gmac_mapcache_create(sc->sc_dmat, MAX_TXMAPS, 202 ETHERMTU_JUMBO + ETHER_HDR_LEN, 16); 203 KASSERT(sc->sc_txmaps != NULL); 204 205 aprint_debug_dev(sc->sc_dev, "gmac_init: create sw freeq\n"); 206 /* 207 * Allocate the memory for sw (receive) free queue 208 */ 209 hqm = gmac_hwqmem_create(sc->sc_rxmaps, 32 /*SWFREEQ_DESCS*/, 1, 210 HQM_PRODUCER|HQM_RX); 211 sc->sc_swfreeq = gmac_hwqueue_create(hqm, sc->sc_iot, sc->sc_ioh, 212 GMAC_SWFREEQ_RWPTR, GMAC_SWFREEQ_BASE, 0); 213 KASSERT(sc->sc_swfreeq != NULL); 214 215 aprint_debug_dev(sc->sc_dev, "gmac_init: create hw freeq\n"); 216 /* 217 * Allocate the memory for hw (receive) free queue 218 */ 219 hqm = gmac_hwqmem_create(sc->sc_rxmaps, HWFREEQ_DESCS, 1, 220 HQM_PRODUCER|HQM_RX); 221 sc->sc_hwfreeq = gmac_hwqueue_create(hqm, sc->sc_iot, sc->sc_ioh, 222 GMAC_HWFREEQ_RWPTR, GMAC_HWFREEQ_BASE, 0); 223 KASSERT(sc->sc_hwfreeq != NULL); 224 225 aprint_debug_dev(sc->sc_dev, "gmac_init: done\n"); 226 } 227 228 int 229 geminigmac_match(device_t parent, cfdata_t cf, void *aux) 230 { 231 struct obio_attach_args *obio = aux; 232 233 if (obio->obio_addr != GEMINI_GMAC_BASE) 234 return 0; 235 236 return 1; 237 } 238 239 void 240 geminigmac_attach(device_t parent, device_t self, void *aux) 241 { 242 struct gmac_softc *sc = device_private(self); 243 struct obio_attach_args *obio = aux; 244 struct gmac_attach_args gma; 245 cfdata_t cf; 246 uint32_t v; 247 int error; 248 249 sc->sc_dev = self; 250 sc->sc_iot = obio->obio_iot; 251 sc->sc_dmat = obio->obio_dmat; 252 sc->sc_gpio_dev = geminigpio_cd.cd_devs[0]; 253 sc->sc_gpio_mdclk = GPIO_MDCLK; 254 sc->sc_gpio_mdout = GPIO_MDIO; 255 sc->sc_gpio_mdin = GPIO_MDIO; 256 KASSERT(sc->sc_gpio_dev != NULL); 257 258 error = bus_space_map(sc->sc_iot, obio->obio_addr, obio->obio_size, 0, 259 &sc->sc_ioh); 260 if (error) { 261 aprint_error(": error mapping registers: %d", error); 262 return; 263 } 264 265 v = bus_space_read_4(sc->sc_iot, sc->sc_ioh, 0); 266 aprint_normal(": devid %d rev %d\n", GMAC_TOE_DEVID(v), 267 GMAC_TOE_REVID(v)); 268 aprint_naive("\n"); 269 270 mutex_init(&sc->sc_mdiolock, MUTEX_DEFAULT, IPL_NET); 271 272 /* 273 * Initialize the GPIO pins 274 */ 275 geminigpio_pin_ctl(sc->sc_gpio_dev, sc->sc_gpio_mdclk, GPIO_PIN_OUTPUT); 276 geminigpio_pin_ctl(sc->sc_gpio_dev, sc->sc_gpio_mdout, GPIO_PIN_OUTPUT); 277 if (sc->sc_gpio_mdout != sc->sc_gpio_mdin) 278 geminigpio_pin_ctl(sc->sc_gpio_dev, sc->sc_gpio_mdin, 279 GPIO_PIN_INPUT); 280 281 /* 282 * Set the MDIO GPIO pins to a known state. 283 */ 284 geminigpio_pin_write(sc->sc_gpio_dev, sc->sc_gpio_mdclk, 0); 285 geminigpio_pin_write(sc->sc_gpio_dev, sc->sc_gpio_mdout, 0); 286 sc->sc_mdiobits = MDCLK; 287 288 gmac_init(sc); 289 290 gma.gma_iot = sc->sc_iot; 291 gma.gma_ioh = sc->sc_ioh; 292 gma.gma_dmat = sc->sc_dmat; 293 294 gma.gma_mii_readreg = geminigmac_mii_readreg; 295 gma.gma_mii_writereg = geminigmac_mii_writereg; 296 297 gma.gma_port = 0; 298 gma.gma_phy = -1; 299 gma.gma_intr = 1; 300 301 cf = config_search_ia(geminigmac_find, sc->sc_dev, 302 geminigmac_cd.cd_name, &gma); 303 if (cf != NULL) 304 config_attach(sc->sc_dev, cf, &gma, geminigmac_print); 305 306 gma.gma_port = 1; 307 gma.gma_phy = -1; 308 gma.gma_intr = 2; 309 310 cf = config_search_ia(geminigmac_find, sc->sc_dev, 311 geminigmac_cd.cd_name, &gma); 312 if (cf != NULL) 313 config_attach(sc->sc_dev, cf, &gma, geminigmac_print); 314 } 315 316 static int 317 geminigmac_find(device_t parent, cfdata_t cf, const int *ldesc, void *aux) 318 { 319 struct gmac_attach_args * const gma = aux; 320 321 if (gma->gma_port != cf->cf_loc[GEMINIGMACCF_PORT]) 322 return 0; 323 if (gma->gma_intr != cf->cf_loc[GEMINIGMACCF_INTR]) 324 return 0; 325 326 gma->gma_phy = cf->cf_loc[GEMINIGMACCF_PHY]; 327 gma->gma_intr = cf->cf_loc[GEMINIGMACCF_INTR]; 328 329 return config_match(parent, cf, gma); 330 } 331 332 static int 333 geminigmac_print(void *aux, const char *name) 334 { 335 struct gmac_attach_args * const gma = aux; 336 337 aprint_normal(" port %d", gma->gma_port); 338 aprint_normal(" phy %d", gma->gma_phy); 339 aprint_normal(" intr %d", gma->gma_intr); 340 341 return UNCONF; 342 } 343 344 static uint32_t 345 gemini_gmac_gpio_read(device_t dv) 346 { 347 struct gmac_softc * const sc = device_private(dv); 348 int value = geminigpio_pin_read(sc->sc_gpio_dev, GPIO_MDIO); 349 350 KASSERT((sc->sc_mdiobits & MDTOPHY) == 0); 351 352 return value ? MDIN : 0; 353 } 354 355 static void 356 gemini_gmac_gpio_write(device_t dv, uint32_t bits) 357 { 358 struct gmac_softc * const sc = device_private(dv); 359 360 if ((sc->sc_mdiobits ^ bits) & MDTOPHY) { 361 int flags = (bits & MDTOPHY) ? GPIO_PIN_OUTPUT : GPIO_PIN_INPUT; 362 geminigpio_pin_ctl(sc->sc_gpio_dev, GPIO_MDIO, flags); 363 } 364 365 if ((sc->sc_mdiobits ^ bits) & MDOUT) { 366 int flags = ((bits & MDOUT) != 0); 367 geminigpio_pin_write(sc->sc_gpio_dev, GPIO_MDIO, flags); 368 } 369 370 if ((sc->sc_mdiobits ^ bits) & MDCLK) { 371 int flags = ((bits & MDCLK) != 0); 372 geminigpio_pin_write(sc->sc_gpio_dev, GPIO_MDCLK, flags); 373 } 374 375 sc->sc_mdiobits = bits; 376 } 377 378 static const struct mii_bitbang_ops geminigmac_mii_bitbang_ops = { 379 .mbo_read = gemini_gmac_gpio_read, 380 .mbo_write = gemini_gmac_gpio_write, 381 .mbo_bits[MII_BIT_MDO] = MDOUT, 382 .mbo_bits[MII_BIT_MDI] = MDIN, 383 .mbo_bits[MII_BIT_MDC] = MDCLK, 384 .mbo_bits[MII_BIT_DIR_HOST_PHY] = MDTOPHY, 385 }; 386 387 int 388 geminigmac_mii_readreg(device_t dv, int phy, int reg) 389 { 390 device_t parent = device_parent(dv); 391 struct gmac_softc * const sc = device_private(parent); 392 int rv; 393 394 mutex_enter(&sc->sc_mdiolock); 395 rv = mii_bitbang_readreg(parent, &geminigmac_mii_bitbang_ops, phy, reg); 396 mutex_exit(&sc->sc_mdiolock); 397 398 //aprint_debug_dev(dv, "mii_readreg(%d, %d): %#x\n", phy, reg, rv); 399 400 return rv; 401 } 402 403 void 404 geminigmac_mii_writereg(device_t dv, int phy, int reg, int val) 405 { 406 device_t parent = device_parent(dv); 407 struct gmac_softc * const sc = device_private(parent); 408 409 //aprint_debug_dev(dv, "mii_writereg(%d, %d, %#x)\n", phy, reg, val); 410 411 mutex_enter(&sc->sc_mdiolock); 412 mii_bitbang_writereg(parent, &geminigmac_mii_bitbang_ops, phy, reg, val); 413 mutex_exit(&sc->sc_mdiolock); 414 } 415 416 417 gmac_mapcache_t * 418 gmac_mapcache_create(bus_dma_tag_t dmat, size_t maxmaps, bus_size_t mapsize, 419 int nsegs) 420 { 421 gmac_mapcache_t *mc; 422 423 mc = kmem_zalloc(offsetof(gmac_mapcache_t, mc_maps[maxmaps]), 424 KM_SLEEP); 425 if (mc == NULL) 426 return NULL; 427 428 mc->mc_max = maxmaps; 429 mc->mc_dmat = dmat; 430 mc->mc_mapsize = mapsize; 431 mc->mc_nsegs = nsegs; 432 return mc; 433 } 434 435 void 436 gmac_mapcache_destroy(gmac_mapcache_t **mc_p) 437 { 438 gmac_mapcache_t *mc = *mc_p; 439 440 if (mc == NULL) 441 return; 442 443 KASSERT(mc->mc_used == 0); 444 while (mc->mc_free-- > 0) { 445 KASSERT(mc->mc_maps[mc->mc_free] != NULL); 446 bus_dmamap_destroy(mc->mc_dmat, mc->mc_maps[mc->mc_free]); 447 mc->mc_maps[mc->mc_free] = NULL; 448 } 449 450 kmem_free(mc, offsetof(gmac_mapcache_t, mc_maps[mc->mc_max])); 451 *mc_p = NULL; 452 } 453 454 int 455 gmac_mapcache_fill(gmac_mapcache_t *mc, size_t limit) 456 { 457 int error; 458 459 KASSERT(limit <= mc->mc_max); 460 aprint_debug("gmac_mapcache_fill(%p): limit=%zu used=%zu free=%zu\n", 461 mc, limit, mc->mc_used, mc->mc_free); 462 463 for (error = 0; mc->mc_free + mc->mc_used < limit; mc->mc_free++) { 464 KASSERT(mc->mc_maps[mc->mc_free] == NULL); 465 error = bus_dmamap_create(mc->mc_dmat, mc->mc_mapsize, 466 mc->mc_nsegs, mc->mc_mapsize, 0, 467 BUS_DMA_ALLOCNOW|BUS_DMA_WAITOK, 468 &mc->mc_maps[mc->mc_free]); 469 if (error) 470 break; 471 } 472 aprint_debug("gmac_mapcache_fill(%p): limit=%zu used=%zu free=%zu\n", 473 mc, limit, mc->mc_used, mc->mc_free); 474 475 return error; 476 } 477 478 bus_dmamap_t 479 gmac_mapcache_get(gmac_mapcache_t *mc) 480 { 481 bus_dmamap_t map; 482 483 KASSERT(mc != NULL); 484 485 if (mc->mc_free == 0) { 486 int error; 487 if (mc->mc_used == mc->mc_max) 488 return NULL; 489 error = bus_dmamap_create(mc->mc_dmat, mc->mc_mapsize, 490 mc->mc_nsegs, mc->mc_mapsize, 0, 491 BUS_DMA_ALLOCNOW|BUS_DMA_NOWAIT, 492 &map); 493 if (error) 494 return NULL; 495 KASSERT(mc->mc_maps[mc->mc_free] == NULL); 496 } else { 497 KASSERT(mc->mc_free <= mc->mc_max); 498 map = mc->mc_maps[--mc->mc_free]; 499 mc->mc_maps[mc->mc_free] = NULL; 500 } 501 mc->mc_used++; 502 KASSERT(map != NULL); 503 504 return map; 505 } 506 507 void 508 gmac_mapcache_put(gmac_mapcache_t *mc, bus_dmamap_t map) 509 { 510 KASSERT(mc->mc_free + mc->mc_used < mc->mc_max); 511 KASSERT(mc->mc_maps[mc->mc_free] == NULL); 512 513 mc->mc_maps[mc->mc_free++] = map; 514 mc->mc_used--; 515 } 516 517 gmac_desc_t * 518 gmac_hwqueue_desc(gmac_hwqueue_t *hwq, size_t i) 519 { 520 i += hwq->hwq_wptr; 521 if (i >= hwq->hwq_size) 522 i -= hwq->hwq_size; 523 return hwq->hwq_base + i; 524 } 525 526 static void 527 gmac_hwqueue_txconsume(gmac_hwqueue_t *hwq, const gmac_desc_t *d) 528 { 529 gmac_hwqmem_t * const hqm = hwq->hwq_hqm; 530 struct ifnet *ifp; 531 bus_dmamap_t map; 532 struct mbuf *m; 533 534 IF_DEQUEUE(&hwq->hwq_ifq, m); 535 KASSERT(m != NULL); 536 map = M_GETCTX(m, bus_dmamap_t); 537 538 bus_dmamap_sync(hqm->hqm_dmat, map, 0, map->dm_mapsize, 539 BUS_DMASYNC_POSTWRITE); 540 bus_dmamap_unload(hqm->hqm_dmat, map); 541 M_SETCTX(m, NULL); 542 gmac_mapcache_put(hqm->hqm_mc, map); 543 544 ifp = hwq->hwq_ifp; 545 ifp->if_opackets++; 546 ifp->if_obytes += m->m_pkthdr.len; 547 548 aprint_debug("gmac_hwqueue_txconsume(%p): %zu@%p: %s m=%p\n", 549 hwq, d - hwq->hwq_base, d, ifp->if_xname, m); 550 551 bpf_mtap(ifp, m); 552 m_freem(m); 553 } 554 555 void 556 gmac_hwqueue_sync(gmac_hwqueue_t *hwq) 557 { 558 gmac_hwqmem_t * const hqm = hwq->hwq_hqm; 559 uint32_t v; 560 uint16_t old_rptr; 561 size_t rptr; 562 563 KASSERT(hqm->hqm_flags & HQM_PRODUCER); 564 565 old_rptr = hwq->hwq_rptr; 566 v = bus_space_read_4(hwq->hwq_iot, hwq->hwq_qrwptr_ioh, 0); 567 hwq->hwq_rptr = (v >> 0) & 0xffff; 568 hwq->hwq_wptr = (v >> 16) & 0xffff; 569 570 if (old_rptr == hwq->hwq_rptr) 571 return; 572 573 aprint_debug("gmac_hwqueue_sync(%p): entry rptr old=%u new=%u free=%u(%u)\n", 574 hwq, old_rptr, hwq->hwq_rptr, hwq->hwq_free, 575 hwq->hwq_size - hwq->hwq_free - 1); 576 577 hwq->hwq_free += (hwq->hwq_rptr - old_rptr) & (hwq->hwq_size - 1); 578 for (rptr = old_rptr; 579 rptr != hwq->hwq_rptr; 580 rptr = (rptr + 1) & (hwq->hwq_size - 1)) { 581 gmac_desc_t * const d = hwq->hwq_base + rptr; 582 if (hqm->hqm_flags & HQM_TX) { 583 bus_dmamap_sync(hqm->hqm_dmat, hqm->hqm_dmamap, 584 sizeof(gmac_desc_t [hwq->hwq_qoff + rptr]), 585 sizeof(gmac_desc_t), 586 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 587 if (d->d_desc3 & htole32(DESC3_EOF)) 588 gmac_hwqueue_txconsume(hwq, d); 589 } else { 590 bus_dmamap_sync(hqm->hqm_dmat, hqm->hqm_dmamap, 591 sizeof(gmac_desc_t [hwq->hwq_qoff + rptr]), 592 sizeof(gmac_desc_t), 593 BUS_DMASYNC_POSTWRITE); 594 595 aprint_debug("gmac_hwqueue_sync(%p): %zu@%p=%#x/%#x/%#x/%#x\n", 596 hwq, rptr, d, d->d_desc0, d->d_desc1, 597 d->d_bufaddr, d->d_desc3); 598 bus_dmamap_sync(hqm->hqm_dmat, hqm->hqm_dmamap, 599 sizeof(gmac_desc_t [hwq->hwq_qoff + rptr]), 600 sizeof(gmac_desc_t), 601 BUS_DMASYNC_PREWRITE); 602 } 603 } 604 605 aprint_debug("gmac_hwqueue_sync(%p): exit rptr old=%u new=%u free=%u(%u)\n", 606 hwq, old_rptr, hwq->hwq_rptr, hwq->hwq_free, 607 hwq->hwq_size - hwq->hwq_free - 1); 608 } 609 610 void 611 gmac_hwqueue_produce(gmac_hwqueue_t *hwq, size_t count) 612 { 613 gmac_hwqmem_t * const hqm = hwq->hwq_hqm; 614 uint16_t wptr; 615 uint16_t rptr = bus_space_read_4(hwq->hwq_iot, hwq->hwq_qrwptr_ioh, 0); 616 617 KASSERT(count < hwq->hwq_free); 618 KASSERT(hqm->hqm_flags & HQM_PRODUCER); 619 KASSERT(hwq->hwq_wptr == bus_space_read_4(hwq->hwq_iot, hwq->hwq_qrwptr_ioh, 0) >> 16); 620 621 aprint_debug("gmac_hwqueue_produce(%p, %zu): rptr=%u(%u) wptr old=%u", 622 hwq, count, hwq->hwq_rptr, rptr, hwq->hwq_wptr); 623 624 hwq->hwq_free -= count; 625 #if 1 626 for (wptr = hwq->hwq_wptr; 627 count > 0; 628 count--, wptr = (wptr + 1) & (hwq->hwq_size - 1)) { 629 KASSERT(((wptr + 1) & (hwq->hwq_size - 1)) != hwq->hwq_rptr); 630 bus_dmamap_sync(hqm->hqm_dmat, hqm->hqm_dmamap, 631 sizeof(gmac_desc_t [hwq->hwq_qoff + wptr]), 632 sizeof(gmac_desc_t), 633 BUS_DMASYNC_PREWRITE); 634 } 635 KASSERT(count == 0); 636 hwq->hwq_wptr = wptr; 637 #else 638 if (hwq->hwq_wptr + count >= hwq->hwq_size) { 639 bus_dmamap_sync(hqm->hqm_dmat, hqm->hqm_dmamap, 640 sizeof(gmac_desc_t [hwq->hwq_qoff + hwq->hwq_wptr]), 641 sizeof(gmac_desc_t [hwq->hwq_size - hwq->hwq_wptr]), 642 BUS_DMASYNC_PREWRITE); 643 count -= hwq->hwq_size - hwq->hwq_wptr; 644 hwq->hwq_wptr = 0; 645 } 646 if (count > 0) { 647 bus_dmamap_sync(hqm->hqm_dmat, hqm->hqm_dmamap, 648 sizeof(gmac_desc_t [hwq->hwq_qoff + hwq->hwq_wptr]), 649 sizeof(gmac_desc_t [count]), 650 BUS_DMASYNC_PREWRITE); 651 hwq->hwq_wptr += count; 652 hwq->hwq_wptr &= (hwq->hwq_size - 1); 653 } 654 #endif 655 656 /* 657 * Tell the h/w we've produced a few more descriptors. 658 * (don't bother writing the rptr since it's RO). 659 */ 660 bus_space_write_4(hwq->hwq_iot, hwq->hwq_qrwptr_ioh, 0, 661 hwq->hwq_wptr << 16); 662 663 aprint_debug(" new=%u\n", hwq->hwq_wptr); 664 } 665 666 size_t 667 gmac_rxproduce(gmac_hwqueue_t *hwq, size_t free_min) 668 { 669 gmac_hwqmem_t * const hqm = hwq->hwq_hqm; 670 size_t i; 671 672 aprint_debug("gmac_rxproduce(%p): entry free=%u(%u) free_min=%zu ifq_len=%d\n", 673 hwq, hwq->hwq_free, hwq->hwq_size - hwq->hwq_free - 1, 674 free_min, hwq->hwq_ifq.ifq_len); 675 676 gmac_hwqueue_sync(hwq); 677 678 aprint_debug("gmac_rxproduce(%p): postsync free=%u(%u)\n", 679 hwq, hwq->hwq_free, hwq->hwq_size - hwq->hwq_free - 1); 680 681 for (i = 0; hwq->hwq_free > 0 && hwq->hwq_size - hwq->hwq_free - 1 < free_min; i++) { 682 bus_dmamap_t map; 683 gmac_desc_t * const d = gmac_hwqueue_desc(hwq, 0); 684 struct mbuf *m, *m0; 685 int error; 686 687 if (d->d_bufaddr && (le32toh(d->d_bufaddr) >> 16) != 0xdead) { 688 gmac_hwqueue_produce(hwq, 1); 689 continue; 690 } 691 692 map = gmac_mapcache_get(hqm->hqm_mc); 693 if (map == NULL) 694 break; 695 696 KASSERT(map->dm_mapsize == 0); 697 698 m = m_gethdr(M_DONTWAIT, MT_DATA); 699 if (m == NULL) { 700 gmac_mapcache_put(hqm->hqm_mc, map); 701 break; 702 } 703 704 MCLGET(m, M_DONTWAIT); 705 if ((m->m_flags & M_EXT) == 0) { 706 m_free(m); 707 gmac_mapcache_put(hqm->hqm_mc, map); 708 break; 709 } 710 error = bus_dmamap_load(hqm->hqm_dmat, map, m->m_data, 711 MCLBYTES, NULL, BUS_DMA_READ|BUS_DMA_NOWAIT); 712 if (error) { 713 m_free(m); 714 gmac_mapcache_put(hqm->hqm_mc, map); 715 aprint_error("gmac0: " 716 "map %p(%zu): can't map rx mbuf(%p) wptr=%u: %d\n", 717 map, map->_dm_size, m, hwq->hwq_wptr, error); 718 Debugger(); 719 break; 720 } 721 bus_dmamap_sync(hqm->hqm_dmat, map, 0, map->dm_mapsize, 722 BUS_DMASYNC_PREREAD); 723 m->m_pkthdr.len = 0; 724 M_SETCTX(m, map); 725 #if 0 726 d->d_desc0 = htole32(map->dm_segs->ds_len); 727 #endif 728 d->d_bufaddr = htole32(map->dm_segs->ds_addr); 729 for (m0 = hwq->hwq_ifq.ifq_head; m0 != NULL; m0 = m0->m_nextpkt) 730 KASSERT(m0 != m); 731 m->m_len = d - hwq->hwq_base; 732 IF_ENQUEUE(&hwq->hwq_ifq, m); 733 aprint_debug( 734 "gmac_rxproduce(%p): m=%p %zu@%p=%#x/%#x/%#x/%#x\n", hwq, 735 m, d - hwq->hwq_base, d, d->d_desc0, d->d_desc1, 736 d->d_bufaddr, d->d_desc3); 737 gmac_hwqueue_produce(hwq, 1); 738 } 739 740 aprint_debug("gmac_rxproduce(%p): exit free=%u(%u) free_min=%zu ifq_len=%d\n", 741 hwq, hwq->hwq_free, hwq->hwq_size - hwq->hwq_free - 1, 742 free_min, hwq->hwq_ifq.ifq_len); 743 744 return i; 745 } 746 747 static bool 748 gmac_hwqueue_rxconsume(gmac_hwqueue_t *hwq, const gmac_desc_t *d) 749 { 750 gmac_hwqmem_t * const hqm = hwq->hwq_hqm; 751 struct ifnet * const ifp = hwq->hwq_ifp; 752 size_t buflen = d->d_desc1 & 0xffff; 753 bus_dmamap_t map; 754 struct mbuf *m, *last_m, **mp; 755 size_t depth; 756 757 KASSERT(ifp != NULL); 758 759 aprint_debug("gmac_hwqueue_rxconsume(%p): entry\n", hwq); 760 761 aprint_debug("gmac_hwqueue_rxconsume(%p): ifp=%p(%s): %#x/%#x/%#x/%#x\n", 762 hwq, hwq->hwq_ifp, hwq->hwq_ifp->if_xname, 763 d->d_desc0, d->d_desc1, d->d_bufaddr, d->d_desc3); 764 765 if (d->d_bufaddr == 0 || d->d_bufaddr == 0xdeadbeef) 766 return false; 767 768 /* 769 * First we have to find this mbuf in the software free queue 770 * (the producer of the mbufs) and remove it. 771 */ 772 KASSERT(hwq->hwq_producer->hwq_free != hwq->hwq_producer->hwq_size - 1); 773 for (mp = &hwq->hwq_producer->hwq_ifq.ifq_head, last_m = NULL, depth=0; 774 (m = *mp) != NULL; 775 last_m = m, mp = &m->m_nextpkt, depth++) { 776 map = M_GETCTX(m, bus_dmamap_t); 777 KASSERT(map != NULL); 778 KASSERT(map->dm_nsegs == 1); 779 aprint_debug("gmac_hwqueue_rxconsume(%p): ifq[%zu]=%p(@%#zx) %d@swfq\n", 780 hwq, depth, m, map->dm_segs->ds_addr, m->m_len); 781 if (le32toh(d->d_bufaddr) == map->dm_segs->ds_addr) { 782 *mp = m->m_nextpkt; 783 if (hwq->hwq_producer->hwq_ifq.ifq_tail == m) 784 hwq->hwq_producer->hwq_ifq.ifq_tail = last_m; 785 hwq->hwq_producer->hwq_ifq.ifq_len--; 786 break; 787 } 788 } 789 aprint_debug("gmac_hwqueue_rxconsume(%p): ifp=%p(%s) m=%p@%zu", 790 hwq, hwq->hwq_ifp, hwq->hwq_ifp->if_xname, m, depth); 791 if (m) 792 aprint_debug(" swfq[%d]=%#x\n", m->m_len, 793 hwq->hwq_producer->hwq_base[m->m_len].d_bufaddr); 794 aprint_debug("\n"); 795 KASSERT(m != NULL); 796 797 { 798 struct mbuf *m0; 799 for (m0 = hwq->hwq_producer->hwq_ifq.ifq_head; m0 != NULL; m0 = m0->m_nextpkt) 800 KASSERT(m0 != m); 801 } 802 803 KASSERT(hwq->hwq_producer->hwq_base[m->m_len].d_bufaddr == d->d_bufaddr); 804 hwq->hwq_producer->hwq_base[m->m_len].d_bufaddr = htole32(0xdead0000 | m->m_len); 805 806 m->m_len = buflen; 807 if (d->d_desc3 & DESC3_SOF) { 808 KASSERT(hwq->hwq_rxmbuf == NULL); 809 m->m_pkthdr.len = buflen; 810 buflen += 2; /* account for the pad */ 811 /* only modify m->m_data after we know mbuf is good. */ 812 } else { 813 KASSERT(hwq->hwq_rxmbuf != NULL); 814 hwq->hwq_rxmbuf->m_pkthdr.len += buflen; 815 } 816 817 map = M_GETCTX(m, bus_dmamap_t); 818 819 /* 820 * Sync the buffer contents, unload the dmamap, and save it away. 821 */ 822 bus_dmamap_sync(hqm->hqm_dmat, map, 0, buflen, BUS_DMASYNC_POSTREAD); 823 bus_dmamap_unload(hqm->hqm_dmat, map); 824 M_SETCTX(m, NULL); 825 gmac_mapcache_put(hqm->hqm_mc, map); 826 827 /* 828 * Now we build our new packet chain by tacking this on the end. 829 */ 830 *hwq->hwq_mp = m; 831 if ((d->d_desc3 & DESC3_EOF) == 0) { 832 /* 833 * Not last frame, so make sure the next gets appended right. 834 */ 835 hwq->hwq_mp = &m->m_next; 836 return true; 837 } 838 839 #if 0 840 /* 841 * We have a complete frame, let's try to deliver it. 842 */ 843 m->m_len -= ETHER_CRC_LEN; /* remove the CRC from the end */ 844 #endif 845 846 /* 847 * Now get the whole chain. 848 */ 849 m = hwq->hwq_rxmbuf; 850 m_set_rcvif(m, ifp); /* set receive interface */ 851 ifp->if_ibytes += m->m_pkthdr.len; 852 switch (DESC0_RXSTS_GET(d->d_desc0)) { 853 case DESC0_RXSTS_GOOD: 854 case DESC0_RXSTS_LONG: 855 m->m_data += 2; 856 KASSERT(m_length(m) == m->m_pkthdr.len); 857 if_percpuq_enqueue(ifp->if_percpuq, m); 858 break; 859 default: 860 ifp->if_ierrors++; 861 m_freem(m); 862 break; 863 } 864 hwq->hwq_rxmbuf = NULL; 865 hwq->hwq_mp = &hwq->hwq_rxmbuf; 866 867 return true; 868 } 869 870 size_t 871 gmac_hwqueue_consume(gmac_hwqueue_t *hwq, size_t free_min) 872 { 873 gmac_hwqmem_t * const hqm = hwq->hwq_hqm; 874 gmac_desc_t d; 875 uint32_t v; 876 uint16_t rptr; 877 size_t i; 878 879 KASSERT((hqm->hqm_flags & HQM_PRODUCER) == 0); 880 881 aprint_debug("gmac_hwqueue_consume(%p): entry\n", hwq); 882 883 884 v = bus_space_read_4(hwq->hwq_iot, hwq->hwq_qrwptr_ioh, 0); 885 rptr = (v >> 0) & 0xffff; 886 hwq->hwq_wptr = (v >> 16) & 0xffff; 887 KASSERT(rptr == hwq->hwq_rptr); 888 if (rptr == hwq->hwq_wptr) 889 return 0; 890 891 i = 0; 892 for (; rptr != hwq->hwq_wptr; rptr = (rptr + 1) & (hwq->hwq_size - 1)) { 893 bus_dmamap_sync(hqm->hqm_dmat, hqm->hqm_dmamap, 894 sizeof(gmac_desc_t [hwq->hwq_qoff + rptr]), 895 sizeof(gmac_desc_t), 896 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 897 d.d_desc0 = le32toh(hwq->hwq_base[rptr].d_desc0); 898 d.d_desc1 = le32toh(hwq->hwq_base[rptr].d_desc1); 899 d.d_bufaddr = le32toh(hwq->hwq_base[rptr].d_bufaddr); 900 d.d_desc3 = le32toh(hwq->hwq_base[rptr].d_desc3); 901 hwq->hwq_base[rptr].d_desc0 = 0; 902 hwq->hwq_base[rptr].d_desc1 = 0; 903 hwq->hwq_base[rptr].d_bufaddr = 0xdeadbeef; 904 hwq->hwq_base[rptr].d_desc3 = 0; 905 bus_dmamap_sync(hqm->hqm_dmat, hqm->hqm_dmamap, 906 sizeof(gmac_desc_t [hwq->hwq_qoff + rptr]), 907 sizeof(gmac_desc_t), 908 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 909 910 aprint_debug("gmac_hwqueue_consume(%p): rptr=%u\n", 911 hwq, rptr); 912 if (!gmac_hwqueue_rxconsume(hwq, &d)) { 913 rptr = (rptr + 1) & (hwq->hwq_size - 1); 914 i += gmac_rxproduce(hwq->hwq_producer, free_min); 915 break; 916 } 917 } 918 919 /* 920 * Update hardware's copy of rptr. (wptr is RO). 921 */ 922 aprint_debug("gmac_hwqueue_consume(%p): rptr old=%u new=%u wptr=%u\n", 923 hwq, hwq->hwq_rptr, rptr, hwq->hwq_wptr); 924 bus_space_write_4(hwq->hwq_iot, hwq->hwq_qrwptr_ioh, 0, rptr); 925 hwq->hwq_rptr = rptr; 926 927 aprint_debug("gmac_hwqueue_consume(%p): exit\n", hwq); 928 929 return i; 930 } 931 932 void 933 gmac_hwqmem_destroy(gmac_hwqmem_t *hqm) 934 { 935 if (hqm->hqm_nsegs) { 936 if (hqm->hqm_base) { 937 if (hqm->hqm_dmamap) { 938 if (hqm->hqm_dmamap->dm_mapsize) { 939 bus_dmamap_unload(hqm->hqm_dmat, 940 hqm->hqm_dmamap); 941 } 942 bus_dmamap_destroy(hqm->hqm_dmat, 943 hqm->hqm_dmamap); 944 } 945 bus_dmamem_unmap(hqm->hqm_dmat, hqm->hqm_base, 946 hqm->hqm_memsize); 947 } 948 bus_dmamem_free(hqm->hqm_dmat, hqm->hqm_segs, hqm->hqm_nsegs); 949 } 950 951 kmem_free(hqm, sizeof(*hqm)); 952 } 953 954 gmac_hwqmem_t * 955 gmac_hwqmem_create(gmac_mapcache_t *mc, size_t ndesc, size_t nqueue, int flags) 956 { 957 gmac_hwqmem_t *hqm; 958 int error; 959 960 KASSERT(ndesc > 0 && ndesc <= 2048); 961 KASSERT((ndesc & (ndesc - 1)) == 0); 962 963 hqm = kmem_zalloc(sizeof(*hqm), KM_SLEEP); 964 hqm->hqm_memsize = nqueue * sizeof(gmac_desc_t [ndesc]); 965 hqm->hqm_mc = mc; 966 hqm->hqm_dmat = mc->mc_dmat; 967 hqm->hqm_ndesc = ndesc; 968 hqm->hqm_nqueue = nqueue; 969 hqm->hqm_flags = flags; 970 971 error = bus_dmamem_alloc(hqm->hqm_dmat, hqm->hqm_memsize, 0, 0, 972 hqm->hqm_segs, 1, &hqm->hqm_nsegs, BUS_DMA_WAITOK); 973 if (error) { 974 KASSERT(error == 0); 975 goto failed; 976 } 977 KASSERT(hqm->hqm_nsegs == 1); 978 error = bus_dmamem_map(hqm->hqm_dmat, hqm->hqm_segs, hqm->hqm_nsegs, 979 hqm->hqm_memsize, (void **)&hqm->hqm_base, BUS_DMA_WAITOK); 980 if (error) { 981 KASSERT(error == 0); 982 goto failed; 983 } 984 error = bus_dmamap_create(hqm->hqm_dmat, hqm->hqm_memsize, 985 hqm->hqm_nsegs, hqm->hqm_memsize, 0, 986 BUS_DMA_WAITOK|BUS_DMA_ALLOCNOW, &hqm->hqm_dmamap); 987 if (error) { 988 KASSERT(error == 0); 989 goto failed; 990 } 991 error = bus_dmamap_load(hqm->hqm_dmat, hqm->hqm_dmamap, hqm->hqm_base, 992 hqm->hqm_memsize, NULL, 993 BUS_DMA_WAITOK|BUS_DMA_WRITE|BUS_DMA_READ|BUS_DMA_COHERENT); 994 if (error) { 995 aprint_debug("gmac_hwqmem_create: ds_addr=%zu ds_len=%zu\n", 996 hqm->hqm_segs->ds_addr, hqm->hqm_segs->ds_len); 997 aprint_debug("gmac_hwqmem_create: bus_dmamap_load: %d\n", error); 998 KASSERT(error == 0); 999 goto failed; 1000 } 1001 1002 memset(hqm->hqm_base, 0, hqm->hqm_memsize); 1003 if ((flags & HQM_PRODUCER) == 0) 1004 bus_dmamap_sync(hqm->hqm_dmat, hqm->hqm_dmamap, 0, 1005 hqm->hqm_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1006 1007 return hqm; 1008 1009 failed: 1010 gmac_hwqmem_destroy(hqm); 1011 return NULL; 1012 } 1013 1014 void 1015 gmac_hwqueue_destroy(gmac_hwqueue_t *hwq) 1016 { 1017 gmac_hwqmem_t * const hqm = hwq->hwq_hqm; 1018 KASSERT(hqm->hqm_refs & hwq->hwq_ref); 1019 hqm->hqm_refs &= ~hwq->hwq_ref; 1020 for (;;) { 1021 struct mbuf *m; 1022 bus_dmamap_t map; 1023 IF_DEQUEUE(&hwq->hwq_ifq, m); 1024 if (m == NULL) 1025 break; 1026 map = M_GETCTX(m, bus_dmamap_t); 1027 bus_dmamap_unload(hqm->hqm_dmat, map); 1028 gmac_mapcache_put(hqm->hqm_mc, map); 1029 m_freem(m); 1030 } 1031 kmem_free(hwq, sizeof(*hwq)); 1032 } 1033 1034 gmac_hwqueue_t * 1035 gmac_hwqueue_create(gmac_hwqmem_t *hqm, 1036 bus_space_tag_t iot, bus_space_handle_t ioh, 1037 bus_size_t qrwptr, bus_size_t qbase, 1038 size_t qno) 1039 { 1040 const size_t log2_memsize = ffs(hqm->hqm_ndesc) - 1; 1041 gmac_hwqueue_t *hwq; 1042 uint32_t v; 1043 1044 KASSERT(qno < hqm->hqm_nqueue); 1045 KASSERT((hqm->hqm_refs & (1 << qno)) == 0); 1046 1047 hwq = kmem_zalloc(sizeof(*hwq), KM_SLEEP); 1048 hwq->hwq_size = hqm->hqm_ndesc; 1049 hwq->hwq_iot = iot; 1050 bus_space_subregion(iot, ioh, qrwptr, sizeof(uint32_t), 1051 &hwq->hwq_qrwptr_ioh); 1052 1053 hwq->hwq_hqm = hqm; 1054 hwq->hwq_ref = 1 << qno; 1055 hqm->hqm_refs |= hwq->hwq_ref; 1056 hwq->hwq_qoff = hqm->hqm_ndesc * qno; 1057 hwq->hwq_base = hqm->hqm_base + hwq->hwq_qoff; 1058 1059 if (qno == 0) { 1060 bus_space_write_4(hwq->hwq_iot, ioh, qbase, 1061 hqm->hqm_dmamap->dm_segs[0].ds_addr | (log2_memsize)); 1062 } 1063 1064 v = bus_space_read_4(hwq->hwq_iot, hwq->hwq_qrwptr_ioh, 0); 1065 hwq->hwq_rptr = (v >> 0) & 0xffff; 1066 hwq->hwq_wptr = (v >> 16) & 0xffff; 1067 1068 aprint_debug("gmac_hwqueue_create: %p: qrwptr=%zu(%#zx) wptr=%u rptr=%u" 1069 " base=%p@%#zx(%#x) qno=%zu\n", 1070 hwq, qrwptr, hwq->hwq_qrwptr_ioh, hwq->hwq_wptr, hwq->hwq_rptr, 1071 hwq->hwq_base, 1072 hqm->hqm_segs->ds_addr + sizeof(gmac_desc_t [hwq->hwq_qoff]), 1073 bus_space_read_4(hwq->hwq_iot, ioh, qbase), qno); 1074 1075 hwq->hwq_free = hwq->hwq_size - 1; 1076 hwq->hwq_ifq.ifq_maxlen = hwq->hwq_free; 1077 hwq->hwq_mp = &hwq->hwq_rxmbuf; 1078 1079 return hwq; 1080 } 1081
Indexes created Tue Sep 23 20:09:58 GMT 2025