gemini_gmac.c revision 1.19
1 /* $NetBSD: gemini_gmac.c,v 1.19 2020/02/04 07:35:34 skrll Exp $ */ 2 /*- 3 * Copyright (c) 2008 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Matt Thomas <matt (at) 3am-software.com> 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 19 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 20 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 21 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include "locators.h" 32 #include <sys/param.h> 33 #include <sys/device.h> 34 #include <sys/kmem.h> 35 #include <sys/mbuf.h> 36 37 #include <net/if.h> 38 #include <net/if_ether.h> 39 40 #include <sys/bus.h> 41 42 #include <arm/gemini/gemini_reg.h> 43 #include <arm/gemini/gemini_obiovar.h> 44 #include <arm/gemini/gemini_gmacvar.h> 45 #include <arm/gemini/gemini_gpiovar.h> 46 47 #include <dev/mii/mii.h> 48 #include <dev/mii/mii_bitbang.h> 49 50 #include <sys/gpio.h> 51 52 __KERNEL_RCSID(0, "$NetBSD: gemini_gmac.c,v 1.19 2020/02/04 07:35:34 skrll Exp $"); 53 54 #define SWFREEQ_DESCS 256 /* one page worth */ 55 #define HWFREEQ_DESCS 256 /* one page worth */ 56 57 static int geminigmac_match(device_t, cfdata_t, void *); 58 static void geminigmac_attach(device_t, device_t, void *); 59 static int geminigmac_find(device_t, cfdata_t, const int *, void *); 60 static int geminigmac_print(void *aux, const char *name); 61 62 static int geminigmac_mii_readreg(device_t, int, int, uint16_t *); 63 static int geminigmac_mii_writereg(device_t, int, int, uint16_t); 64 65 #define GPIO_MDIO 21 66 #define GPIO_MDCLK 22 67 68 #define MDIN __BIT(3) 69 #define MDOUT __BIT(2) 70 #define MDCLK __BIT(1) 71 #define MDTOPHY __BIT(0) 72 73 CFATTACH_DECL_NEW(geminigmac, sizeof(struct gmac_softc), 74 geminigmac_match, geminigmac_attach, NULL, NULL); 75 76 extern struct cfdriver geminigmac_cd; 77 extern struct cfdriver geminigpio_cd; 78 79 void 80 gmac_swfree_min_update(struct gmac_softc *sc) 81 { 82 uint32_t v; 83 84 if (sc->sc_swfreeq != NULL 85 && sc->sc_swfree_min > sc->sc_swfreeq->hwq_size - 1) 86 sc->sc_swfree_min = sc->sc_swfreeq->hwq_size - 1; 87 88 v = bus_space_read_4(sc->sc_iot, sc->sc_ioh, GMAC_QFE_THRESHOLD); 89 v &= ~QFE_SWFQ_THRESHOLD_MASK; 90 v |= QFE_SWFQ_THRESHOLD(sc->sc_swfree_min); 91 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GMAC_QFE_THRESHOLD, v); 92 } 93 94 void 95 gmac_intr_update(struct gmac_softc *sc) 96 { 97 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GMAC_INT0_MASK, 98 ~sc->sc_int_enabled[0]); 99 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GMAC_INT1_MASK, 100 ~sc->sc_int_enabled[1]); 101 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GMAC_INT2_MASK, 102 ~sc->sc_int_enabled[2]); 103 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GMAC_INT3_MASK, 104 ~sc->sc_int_enabled[3]); 105 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GMAC_INT4_MASK, 106 ~sc->sc_int_enabled[4]); 107 } 108 109 static void 110 gmac_init(struct gmac_softc *sc) 111 { 112 gmac_hwqmem_t *hqm; 113 114 /* 115 * This shouldn't be needed. 116 */ 117 for (bus_size_t i = 0; i < GMAC_TOE_QH_SIZE; i += 4) { 118 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 119 GMAC_TOE_QH_OFFSET + i, 0); 120 } 121 #if 0 122 { 123 bus_space_handle_t global_ioh; 124 int error; 125 126 error = bus_space_map(sc->sc_iot, GEMINI_GLOBAL_BASE, 4, 0, 127 &global_ioh); 128 KASSERT(error == 0); 129 aprint_normal_dev(sc->sc_dev, "gmac_init: global_ioh=%#zx\n", global_ioh); 130 bus_space_write_4(sc->sc_iot, global_ioh, GEMINI_GLOBAL_RESET_CTL, 131 GLOBAL_RESET_GMAC0|GLOBAL_RESET_GMAC1); 132 do { 133 v = bus_space_read_4(sc->sc_iot, global_ioh, 134 GEMINI_GLOBAL_RESET_CTL); 135 } while (v & (GLOBAL_RESET_GMAC0|GLOBAL_RESET_GMAC1)); 136 bus_space_unmap(sc->sc_iot, global_ioh, 4); 137 DELAY(1000); 138 } 139 #endif 140 141 sc->sc_swfree_min = 4; /* MIN_RXMAPS; */ 142 143 gmac_swfree_min_update(sc); 144 145 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GMAC_SKBSIZE, 146 SKB_SIZE_SET(PAGE_SIZE, MCLBYTES)); 147 148 sc->sc_int_select[0] = INT0_GMAC1; 149 sc->sc_int_select[1] = INT1_GMAC1; 150 sc->sc_int_select[2] = INT2_GMAC1; 151 sc->sc_int_select[3] = INT3_GMAC1; 152 sc->sc_int_select[4] = INT4_GMAC1; 153 154 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GMAC_INT0_SELECT, INT0_GMAC1); 155 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GMAC_INT1_SELECT, INT1_GMAC1); 156 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GMAC_INT2_SELECT, INT2_GMAC1); 157 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GMAC_INT3_SELECT, INT3_GMAC1); 158 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GMAC_INT4_SELECT, INT4_GMAC1); 159 160 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GMAC_INT0_STATUS, ~0); 161 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GMAC_INT1_STATUS, ~0); 162 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GMAC_INT2_STATUS, ~0); 163 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GMAC_INT3_STATUS, ~0); 164 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GMAC_INT4_STATUS, ~0); 165 166 gmac_intr_update(sc); 167 168 aprint_debug_dev(sc->sc_dev, "gmac_init: sts=%#x/%#x/%#x/%#x/%#x\n", 169 bus_space_read_4(sc->sc_iot, sc->sc_ioh, GMAC_INT0_STATUS), 170 bus_space_read_4(sc->sc_iot, sc->sc_ioh, GMAC_INT1_STATUS), 171 bus_space_read_4(sc->sc_iot, sc->sc_ioh, GMAC_INT2_STATUS), 172 bus_space_read_4(sc->sc_iot, sc->sc_ioh, GMAC_INT3_STATUS), 173 bus_space_read_4(sc->sc_iot, sc->sc_ioh, GMAC_INT4_STATUS)); 174 175 aprint_debug_dev(sc->sc_dev, "gmac_init: mask=%#x/%#x/%#x/%#x/%#x\n", 176 bus_space_read_4(sc->sc_iot, sc->sc_ioh, GMAC_INT0_MASK), 177 bus_space_read_4(sc->sc_iot, sc->sc_ioh, GMAC_INT1_MASK), 178 bus_space_read_4(sc->sc_iot, sc->sc_ioh, GMAC_INT2_MASK), 179 bus_space_read_4(sc->sc_iot, sc->sc_ioh, GMAC_INT3_MASK), 180 bus_space_read_4(sc->sc_iot, sc->sc_ioh, GMAC_INT4_MASK)); 181 182 aprint_debug_dev(sc->sc_dev, "gmac_init: select=%#x/%#x/%#x/%#x/%#x\n", 183 bus_space_read_4(sc->sc_iot, sc->sc_ioh, GMAC_INT0_SELECT), 184 bus_space_read_4(sc->sc_iot, sc->sc_ioh, GMAC_INT1_SELECT), 185 bus_space_read_4(sc->sc_iot, sc->sc_ioh, GMAC_INT2_SELECT), 186 bus_space_read_4(sc->sc_iot, sc->sc_ioh, GMAC_INT3_SELECT), 187 bus_space_read_4(sc->sc_iot, sc->sc_ioh, GMAC_INT4_SELECT)); 188 189 aprint_debug_dev(sc->sc_dev, "gmac_init: create rx dmamap cache\n"); 190 /* 191 * Allocate the cache for receive dmamaps. 192 */ 193 sc->sc_rxmaps = gmac_mapcache_create(sc->sc_dmat, MAX_RXMAPS, 194 MCLBYTES, 1); 195 KASSERT(sc->sc_rxmaps != NULL); 196 197 aprint_debug_dev(sc->sc_dev, "gmac_init: create tx dmamap cache\n"); 198 /* 199 * Allocate the cache for transmit dmamaps. 200 */ 201 sc->sc_txmaps = gmac_mapcache_create(sc->sc_dmat, MAX_TXMAPS, 202 ETHERMTU_JUMBO + ETHER_HDR_LEN, 16); 203 KASSERT(sc->sc_txmaps != NULL); 204 205 aprint_debug_dev(sc->sc_dev, "gmac_init: create sw freeq\n"); 206 /* 207 * Allocate the memory for sw (receive) free queue 208 */ 209 hqm = gmac_hwqmem_create(sc->sc_rxmaps, 32 /*SWFREEQ_DESCS*/, 1, 210 HQM_PRODUCER|HQM_RX); 211 sc->sc_swfreeq = gmac_hwqueue_create(hqm, sc->sc_iot, sc->sc_ioh, 212 GMAC_SWFREEQ_RWPTR, GMAC_SWFREEQ_BASE, 0); 213 KASSERT(sc->sc_swfreeq != NULL); 214 215 aprint_debug_dev(sc->sc_dev, "gmac_init: create hw freeq\n"); 216 /* 217 * Allocate the memory for hw (receive) free queue 218 */ 219 hqm = gmac_hwqmem_create(sc->sc_rxmaps, HWFREEQ_DESCS, 1, 220 HQM_PRODUCER|HQM_RX); 221 sc->sc_hwfreeq = gmac_hwqueue_create(hqm, sc->sc_iot, sc->sc_ioh, 222 GMAC_HWFREEQ_RWPTR, GMAC_HWFREEQ_BASE, 0); 223 KASSERT(sc->sc_hwfreeq != NULL); 224 225 aprint_debug_dev(sc->sc_dev, "gmac_init: done\n"); 226 } 227 228 int 229 geminigmac_match(device_t parent, cfdata_t cf, void *aux) 230 { 231 struct obio_attach_args *obio = aux; 232 233 if (obio->obio_addr != GEMINI_GMAC_BASE) 234 return 0; 235 236 return 1; 237 } 238 239 void 240 geminigmac_attach(device_t parent, device_t self, void *aux) 241 { 242 struct gmac_softc *sc = device_private(self); 243 struct obio_attach_args *obio = aux; 244 struct gmac_attach_args gma; 245 cfdata_t cf; 246 uint32_t v; 247 int error; 248 249 sc->sc_dev = self; 250 sc->sc_iot = obio->obio_iot; 251 sc->sc_dmat = obio->obio_dmat; 252 sc->sc_gpio_dev = geminigpio_cd.cd_devs[0]; 253 sc->sc_gpio_mdclk = GPIO_MDCLK; 254 sc->sc_gpio_mdout = GPIO_MDIO; 255 sc->sc_gpio_mdin = GPIO_MDIO; 256 KASSERT(sc->sc_gpio_dev != NULL); 257 258 error = bus_space_map(sc->sc_iot, obio->obio_addr, obio->obio_size, 0, 259 &sc->sc_ioh); 260 if (error) { 261 aprint_error(": error mapping registers: %d", error); 262 return; 263 } 264 265 v = bus_space_read_4(sc->sc_iot, sc->sc_ioh, 0); 266 aprint_normal(": devid %d rev %d\n", GMAC_TOE_DEVID(v), 267 GMAC_TOE_REVID(v)); 268 aprint_naive("\n"); 269 270 mutex_init(&sc->sc_mdiolock, MUTEX_DEFAULT, IPL_NET); 271 272 /* 273 * Initialize the GPIO pins 274 */ 275 geminigpio_pin_ctl(sc->sc_gpio_dev, sc->sc_gpio_mdclk, GPIO_PIN_OUTPUT); 276 geminigpio_pin_ctl(sc->sc_gpio_dev, sc->sc_gpio_mdout, GPIO_PIN_OUTPUT); 277 if (sc->sc_gpio_mdout != sc->sc_gpio_mdin) 278 geminigpio_pin_ctl(sc->sc_gpio_dev, sc->sc_gpio_mdin, 279 GPIO_PIN_INPUT); 280 281 /* 282 * Set the MDIO GPIO pins to a known state. 283 */ 284 geminigpio_pin_write(sc->sc_gpio_dev, sc->sc_gpio_mdclk, 0); 285 geminigpio_pin_write(sc->sc_gpio_dev, sc->sc_gpio_mdout, 0); 286 sc->sc_mdiobits = MDCLK; 287 288 gmac_init(sc); 289 290 gma.gma_iot = sc->sc_iot; 291 gma.gma_ioh = sc->sc_ioh; 292 gma.gma_dmat = sc->sc_dmat; 293 294 gma.gma_mii_readreg = geminigmac_mii_readreg; 295 gma.gma_mii_writereg = geminigmac_mii_writereg; 296 297 gma.gma_port = 0; 298 gma.gma_phy = -1; 299 gma.gma_intr = 1; 300 301 cf = config_search_ia(geminigmac_find, sc->sc_dev, 302 geminigmac_cd.cd_name, &gma); 303 if (cf != NULL) 304 config_attach(sc->sc_dev, cf, &gma, geminigmac_print); 305 306 gma.gma_port = 1; 307 gma.gma_phy = -1; 308 gma.gma_intr = 2; 309 310 cf = config_search_ia(geminigmac_find, sc->sc_dev, 311 geminigmac_cd.cd_name, &gma); 312 if (cf != NULL) 313 config_attach(sc->sc_dev, cf, &gma, geminigmac_print); 314 } 315 316 static int 317 geminigmac_find(device_t parent, cfdata_t cf, const int *ldesc, void *aux) 318 { 319 struct gmac_attach_args * const gma = aux; 320 321 if (gma->gma_port != cf->cf_loc[GEMINIGMACCF_PORT]) 322 return 0; 323 if (gma->gma_intr != cf->cf_loc[GEMINIGMACCF_INTR]) 324 return 0; 325 326 gma->gma_phy = cf->cf_loc[GEMINIGMACCF_PHY]; 327 gma->gma_intr = cf->cf_loc[GEMINIGMACCF_INTR]; 328 329 return config_match(parent, cf, gma); 330 } 331 332 static int 333 geminigmac_print(void *aux, const char *name) 334 { 335 struct gmac_attach_args * const gma = aux; 336 337 aprint_normal(" port %d", gma->gma_port); 338 aprint_normal(" phy %d", gma->gma_phy); 339 aprint_normal(" intr %d", gma->gma_intr); 340 341 return UNCONF; 342 } 343 344 static uint32_t 345 gemini_gmac_gpio_read(device_t dv) 346 { 347 struct gmac_softc * const sc = device_private(dv); 348 int value = geminigpio_pin_read(sc->sc_gpio_dev, GPIO_MDIO); 349 350 KASSERT((sc->sc_mdiobits & MDTOPHY) == 0); 351 352 return value ? MDIN : 0; 353 } 354 355 static void 356 gemini_gmac_gpio_write(device_t dv, uint32_t bits) 357 { 358 struct gmac_softc * const sc = device_private(dv); 359 360 if ((sc->sc_mdiobits ^ bits) & MDTOPHY) { 361 int flags = (bits & MDTOPHY) ? GPIO_PIN_OUTPUT : GPIO_PIN_INPUT; 362 geminigpio_pin_ctl(sc->sc_gpio_dev, GPIO_MDIO, flags); 363 } 364 365 if ((sc->sc_mdiobits ^ bits) & MDOUT) { 366 int flags = ((bits & MDOUT) != 0); 367 geminigpio_pin_write(sc->sc_gpio_dev, GPIO_MDIO, flags); 368 } 369 370 if ((sc->sc_mdiobits ^ bits) & MDCLK) { 371 int flags = ((bits & MDCLK) != 0); 372 geminigpio_pin_write(sc->sc_gpio_dev, GPIO_MDCLK, flags); 373 } 374 375 sc->sc_mdiobits = bits; 376 } 377 378 static const struct mii_bitbang_ops geminigmac_mii_bitbang_ops = { 379 .mbo_read = gemini_gmac_gpio_read, 380 .mbo_write = gemini_gmac_gpio_write, 381 .mbo_bits[MII_BIT_MDO] = MDOUT, 382 .mbo_bits[MII_BIT_MDI] = MDIN, 383 .mbo_bits[MII_BIT_MDC] = MDCLK, 384 .mbo_bits[MII_BIT_DIR_HOST_PHY] = MDTOPHY, 385 }; 386 387 int 388 geminigmac_mii_readreg(device_t dv, int phy, int reg, uint16_t *val) 389 { 390 device_t parent = device_parent(dv); 391 struct gmac_softc * const sc = device_private(parent); 392 int rv; 393 394 mutex_enter(&sc->sc_mdiolock); 395 rv = mii_bitbang_readreg(parent, &geminigmac_mii_bitbang_ops, phy, 396 reg, val); 397 mutex_exit(&sc->sc_mdiolock); 398 399 //aprint_debug_dev(dv, "mii_readreg(%d, %d): %#x\n", phy, reg, rv); 400 401 return rv; 402 } 403 404 int 405 geminigmac_mii_writereg(device_t dv, int phy, int reg, uint16_t val) 406 { 407 device_t parent = device_parent(dv); 408 struct gmac_softc * const sc = device_private(parent); 409 410 //aprint_debug_dev(dv, "mii_writereg(%d, %d, %#x)\n", phy, reg, val); 411 412 mutex_enter(&sc->sc_mdiolock); 413 rv = mii_bitbang_writereg(parent, &geminigmac_mii_bitbang_ops, phy, 414 reg, val); 415 mutex_exit(&sc->sc_mdiolock); 416 417 return rv; 418 } 419 420 421 gmac_mapcache_t * 422 gmac_mapcache_create(bus_dma_tag_t dmat, size_t maxmaps, bus_size_t mapsize, 423 int nsegs) 424 { 425 gmac_mapcache_t *mc; 426 427 mc = kmem_zalloc(offsetof(gmac_mapcache_t, mc_maps[maxmaps]), 428 KM_SLEEP); 429 if (mc == NULL) 430 return NULL; 431 432 mc->mc_max = maxmaps; 433 mc->mc_dmat = dmat; 434 mc->mc_mapsize = mapsize; 435 mc->mc_nsegs = nsegs; 436 return mc; 437 } 438 439 void 440 gmac_mapcache_destroy(gmac_mapcache_t **mc_p) 441 { 442 gmac_mapcache_t *mc = *mc_p; 443 444 if (mc == NULL) 445 return; 446 447 KASSERT(mc->mc_used == 0); 448 while (mc->mc_free-- > 0) { 449 KASSERT(mc->mc_maps[mc->mc_free] != NULL); 450 bus_dmamap_destroy(mc->mc_dmat, mc->mc_maps[mc->mc_free]); 451 mc->mc_maps[mc->mc_free] = NULL; 452 } 453 454 kmem_free(mc, offsetof(gmac_mapcache_t, mc_maps[mc->mc_max])); 455 *mc_p = NULL; 456 } 457 458 int 459 gmac_mapcache_fill(gmac_mapcache_t *mc, size_t limit) 460 { 461 int error; 462 463 KASSERT(limit <= mc->mc_max); 464 aprint_debug("gmac_mapcache_fill(%p): limit=%zu used=%zu free=%zu\n", 465 mc, limit, mc->mc_used, mc->mc_free); 466 467 for (error = 0; mc->mc_free + mc->mc_used < limit; mc->mc_free++) { 468 KASSERT(mc->mc_maps[mc->mc_free] == NULL); 469 error = bus_dmamap_create(mc->mc_dmat, mc->mc_mapsize, 470 mc->mc_nsegs, mc->mc_mapsize, 0, 471 BUS_DMA_ALLOCNOW|BUS_DMA_WAITOK, 472 &mc->mc_maps[mc->mc_free]); 473 if (error) 474 break; 475 } 476 aprint_debug("gmac_mapcache_fill(%p): limit=%zu used=%zu free=%zu\n", 477 mc, limit, mc->mc_used, mc->mc_free); 478 479 return error; 480 } 481 482 bus_dmamap_t 483 gmac_mapcache_get(gmac_mapcache_t *mc) 484 { 485 bus_dmamap_t map; 486 487 KASSERT(mc != NULL); 488 489 if (mc->mc_free == 0) { 490 int error; 491 if (mc->mc_used == mc->mc_max) 492 return NULL; 493 error = bus_dmamap_create(mc->mc_dmat, mc->mc_mapsize, 494 mc->mc_nsegs, mc->mc_mapsize, 0, 495 BUS_DMA_ALLOCNOW|BUS_DMA_NOWAIT, 496 &map); 497 if (error) 498 return NULL; 499 KASSERT(mc->mc_maps[mc->mc_free] == NULL); 500 } else { 501 KASSERT(mc->mc_free <= mc->mc_max); 502 map = mc->mc_maps[--mc->mc_free]; 503 mc->mc_maps[mc->mc_free] = NULL; 504 } 505 mc->mc_used++; 506 KASSERT(map != NULL); 507 508 return map; 509 } 510 511 void 512 gmac_mapcache_put(gmac_mapcache_t *mc, bus_dmamap_t map) 513 { 514 KASSERT(mc->mc_free + mc->mc_used < mc->mc_max); 515 KASSERT(mc->mc_maps[mc->mc_free] == NULL); 516 517 mc->mc_maps[mc->mc_free++] = map; 518 mc->mc_used--; 519 } 520 521 gmac_desc_t * 522 gmac_hwqueue_desc(gmac_hwqueue_t *hwq, size_t i) 523 { 524 i += hwq->hwq_wptr; 525 if (i >= hwq->hwq_size) 526 i -= hwq->hwq_size; 527 return hwq->hwq_base + i; 528 } 529 530 static void 531 gmac_hwqueue_txconsume(gmac_hwqueue_t *hwq, const gmac_desc_t *d) 532 { 533 gmac_hwqmem_t * const hqm = hwq->hwq_hqm; 534 struct ifnet *ifp; 535 bus_dmamap_t map; 536 struct mbuf *m; 537 538 IF_DEQUEUE(&hwq->hwq_ifq, m); 539 KASSERT(m != NULL); 540 map = M_GETCTX(m, bus_dmamap_t); 541 542 bus_dmamap_sync(hqm->hqm_dmat, map, 0, map->dm_mapsize, 543 BUS_DMASYNC_POSTWRITE); 544 bus_dmamap_unload(hqm->hqm_dmat, map); 545 M_SETCTX(m, NULL); 546 gmac_mapcache_put(hqm->hqm_mc, map); 547 548 ifp = hwq->hwq_ifp; 549 if_statinc(ifp, if_opackets); 550 if_statiadd(ifp, if_obytes, m->m_pkthdr.len); 551 552 aprint_debug("gmac_hwqueue_txconsume(%p): %zu@%p: %s m=%p\n", 553 hwq, d - hwq->hwq_base, d, ifp->if_xname, m); 554 555 bpf_mtap(ifp, m, BPF_D_OUT); 556 m_freem(m); 557 } 558 559 void 560 gmac_hwqueue_sync(gmac_hwqueue_t *hwq) 561 { 562 gmac_hwqmem_t * const hqm = hwq->hwq_hqm; 563 uint32_t v; 564 uint16_t old_rptr; 565 size_t rptr; 566 567 KASSERT(hqm->hqm_flags & HQM_PRODUCER); 568 569 old_rptr = hwq->hwq_rptr; 570 v = bus_space_read_4(hwq->hwq_iot, hwq->hwq_qrwptr_ioh, 0); 571 hwq->hwq_rptr = (v >> 0) & 0xffff; 572 hwq->hwq_wptr = (v >> 16) & 0xffff; 573 574 if (old_rptr == hwq->hwq_rptr) 575 return; 576 577 aprint_debug("gmac_hwqueue_sync(%p): entry rptr old=%u new=%u free=%u(%u)\n", 578 hwq, old_rptr, hwq->hwq_rptr, hwq->hwq_free, 579 hwq->hwq_size - hwq->hwq_free - 1); 580 581 hwq->hwq_free += (hwq->hwq_rptr - old_rptr) & (hwq->hwq_size - 1); 582 for (rptr = old_rptr; 583 rptr != hwq->hwq_rptr; 584 rptr = (rptr + 1) & (hwq->hwq_size - 1)) { 585 gmac_desc_t * const d = hwq->hwq_base + rptr; 586 if (hqm->hqm_flags & HQM_TX) { 587 bus_dmamap_sync(hqm->hqm_dmat, hqm->hqm_dmamap, 588 sizeof(gmac_desc_t [hwq->hwq_qoff + rptr]), 589 sizeof(gmac_desc_t), 590 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 591 if (d->d_desc3 & htole32(DESC3_EOF)) 592 gmac_hwqueue_txconsume(hwq, d); 593 } else { 594 bus_dmamap_sync(hqm->hqm_dmat, hqm->hqm_dmamap, 595 sizeof(gmac_desc_t [hwq->hwq_qoff + rptr]), 596 sizeof(gmac_desc_t), 597 BUS_DMASYNC_POSTWRITE); 598 599 aprint_debug("gmac_hwqueue_sync(%p): %zu@%p=%#x/%#x/%#x/%#x\n", 600 hwq, rptr, d, d->d_desc0, d->d_desc1, 601 d->d_bufaddr, d->d_desc3); 602 bus_dmamap_sync(hqm->hqm_dmat, hqm->hqm_dmamap, 603 sizeof(gmac_desc_t [hwq->hwq_qoff + rptr]), 604 sizeof(gmac_desc_t), 605 BUS_DMASYNC_PREWRITE); 606 } 607 } 608 609 aprint_debug("gmac_hwqueue_sync(%p): exit rptr old=%u new=%u free=%u(%u)\n", 610 hwq, old_rptr, hwq->hwq_rptr, hwq->hwq_free, 611 hwq->hwq_size - hwq->hwq_free - 1); 612 } 613 614 void 615 gmac_hwqueue_produce(gmac_hwqueue_t *hwq, size_t count) 616 { 617 gmac_hwqmem_t * const hqm = hwq->hwq_hqm; 618 uint16_t wptr; 619 uint16_t rptr = bus_space_read_4(hwq->hwq_iot, hwq->hwq_qrwptr_ioh, 0); 620 621 KASSERT(count < hwq->hwq_free); 622 KASSERT(hqm->hqm_flags & HQM_PRODUCER); 623 KASSERT(hwq->hwq_wptr == bus_space_read_4(hwq->hwq_iot, hwq->hwq_qrwptr_ioh, 0) >> 16); 624 625 aprint_debug("gmac_hwqueue_produce(%p, %zu): rptr=%u(%u) wptr old=%u", 626 hwq, count, hwq->hwq_rptr, rptr, hwq->hwq_wptr); 627 628 hwq->hwq_free -= count; 629 #if 1 630 for (wptr = hwq->hwq_wptr; 631 count > 0; 632 count--, wptr = (wptr + 1) & (hwq->hwq_size - 1)) { 633 KASSERT(((wptr + 1) & (hwq->hwq_size - 1)) != hwq->hwq_rptr); 634 bus_dmamap_sync(hqm->hqm_dmat, hqm->hqm_dmamap, 635 sizeof(gmac_desc_t [hwq->hwq_qoff + wptr]), 636 sizeof(gmac_desc_t), 637 BUS_DMASYNC_PREWRITE); 638 } 639 KASSERT(count == 0); 640 hwq->hwq_wptr = wptr; 641 #else 642 if (hwq->hwq_wptr + count >= hwq->hwq_size) { 643 bus_dmamap_sync(hqm->hqm_dmat, hqm->hqm_dmamap, 644 sizeof(gmac_desc_t [hwq->hwq_qoff + hwq->hwq_wptr]), 645 sizeof(gmac_desc_t [hwq->hwq_size - hwq->hwq_wptr]), 646 BUS_DMASYNC_PREWRITE); 647 count -= hwq->hwq_size - hwq->hwq_wptr; 648 hwq->hwq_wptr = 0; 649 } 650 if (count > 0) { 651 bus_dmamap_sync(hqm->hqm_dmat, hqm->hqm_dmamap, 652 sizeof(gmac_desc_t [hwq->hwq_qoff + hwq->hwq_wptr]), 653 sizeof(gmac_desc_t [count]), 654 BUS_DMASYNC_PREWRITE); 655 hwq->hwq_wptr += count; 656 hwq->hwq_wptr &= (hwq->hwq_size - 1); 657 } 658 #endif 659 660 /* 661 * Tell the h/w we've produced a few more descriptors. 662 * (don't bother writing the rptr since it's RO). 663 */ 664 bus_space_write_4(hwq->hwq_iot, hwq->hwq_qrwptr_ioh, 0, 665 hwq->hwq_wptr << 16); 666 667 aprint_debug(" new=%u\n", hwq->hwq_wptr); 668 } 669 670 size_t 671 gmac_rxproduce(gmac_hwqueue_t *hwq, size_t free_min) 672 { 673 gmac_hwqmem_t * const hqm = hwq->hwq_hqm; 674 size_t i; 675 676 aprint_debug("gmac_rxproduce(%p): entry free=%u(%u) free_min=%zu ifq_len=%d\n", 677 hwq, hwq->hwq_free, hwq->hwq_size - hwq->hwq_free - 1, 678 free_min, hwq->hwq_ifq.ifq_len); 679 680 gmac_hwqueue_sync(hwq); 681 682 aprint_debug("gmac_rxproduce(%p): postsync free=%u(%u)\n", 683 hwq, hwq->hwq_free, hwq->hwq_size - hwq->hwq_free - 1); 684 685 for (i = 0; hwq->hwq_free > 0 && hwq->hwq_size - hwq->hwq_free - 1 < free_min; i++) { 686 bus_dmamap_t map; 687 gmac_desc_t * const d = gmac_hwqueue_desc(hwq, 0); 688 struct mbuf *m, *m0; 689 int error; 690 691 if (d->d_bufaddr && (le32toh(d->d_bufaddr) >> 16) != 0xdead) { 692 gmac_hwqueue_produce(hwq, 1); 693 continue; 694 } 695 696 map = gmac_mapcache_get(hqm->hqm_mc); 697 if (map == NULL) 698 break; 699 700 KASSERT(map->dm_mapsize == 0); 701 702 m = m_gethdr(M_DONTWAIT, MT_DATA); 703 if (m == NULL) { 704 gmac_mapcache_put(hqm->hqm_mc, map); 705 break; 706 } 707 708 MCLGET(m, M_DONTWAIT); 709 if ((m->m_flags & M_EXT) == 0) { 710 m_free(m); 711 gmac_mapcache_put(hqm->hqm_mc, map); 712 break; 713 } 714 error = bus_dmamap_load(hqm->hqm_dmat, map, m->m_data, 715 MCLBYTES, NULL, BUS_DMA_READ|BUS_DMA_NOWAIT); 716 if (error) { 717 m_free(m); 718 gmac_mapcache_put(hqm->hqm_mc, map); 719 aprint_error("gmac0: " 720 "map %p(%zu): can't map rx mbuf(%p) wptr=%u: %d\n", 721 map, map->_dm_size, m, hwq->hwq_wptr, error); 722 Debugger(); 723 break; 724 } 725 bus_dmamap_sync(hqm->hqm_dmat, map, 0, map->dm_mapsize, 726 BUS_DMASYNC_PREREAD); 727 m->m_pkthdr.len = 0; 728 M_SETCTX(m, map); 729 #if 0 730 d->d_desc0 = htole32(map->dm_segs->ds_len); 731 #endif 732 d->d_bufaddr = htole32(map->dm_segs->ds_addr); 733 for (m0 = hwq->hwq_ifq.ifq_head; m0 != NULL; m0 = m0->m_nextpkt) 734 KASSERT(m0 != m); 735 m->m_len = d - hwq->hwq_base; 736 IF_ENQUEUE(&hwq->hwq_ifq, m); 737 aprint_debug( 738 "gmac_rxproduce(%p): m=%p %zu@%p=%#x/%#x/%#x/%#x\n", hwq, 739 m, d - hwq->hwq_base, d, d->d_desc0, d->d_desc1, 740 d->d_bufaddr, d->d_desc3); 741 gmac_hwqueue_produce(hwq, 1); 742 } 743 744 aprint_debug("gmac_rxproduce(%p): exit free=%u(%u) free_min=%zu ifq_len=%d\n", 745 hwq, hwq->hwq_free, hwq->hwq_size - hwq->hwq_free - 1, 746 free_min, hwq->hwq_ifq.ifq_len); 747 748 return i; 749 } 750 751 static bool 752 gmac_hwqueue_rxconsume(gmac_hwqueue_t *hwq, const gmac_desc_t *d) 753 { 754 gmac_hwqmem_t * const hqm = hwq->hwq_hqm; 755 struct ifnet * const ifp = hwq->hwq_ifp; 756 size_t buflen = d->d_desc1 & 0xffff; 757 bus_dmamap_t map; 758 struct mbuf *m, *last_m, **mp; 759 size_t depth; 760 761 KASSERT(ifp != NULL); 762 763 aprint_debug("gmac_hwqueue_rxconsume(%p): entry\n", hwq); 764 765 aprint_debug("gmac_hwqueue_rxconsume(%p): ifp=%p(%s): %#x/%#x/%#x/%#x\n", 766 hwq, hwq->hwq_ifp, hwq->hwq_ifp->if_xname, 767 d->d_desc0, d->d_desc1, d->d_bufaddr, d->d_desc3); 768 769 if (d->d_bufaddr == 0 || d->d_bufaddr == 0xdeadbeef) 770 return false; 771 772 /* 773 * First we have to find this mbuf in the software free queue 774 * (the producer of the mbufs) and remove it. 775 */ 776 KASSERT(hwq->hwq_producer->hwq_free != hwq->hwq_producer->hwq_size - 1); 777 for (mp = &hwq->hwq_producer->hwq_ifq.ifq_head, last_m = NULL, depth=0; 778 (m = *mp) != NULL; 779 last_m = m, mp = &m->m_nextpkt, depth++) { 780 map = M_GETCTX(m, bus_dmamap_t); 781 KASSERT(map != NULL); 782 KASSERT(map->dm_nsegs == 1); 783 aprint_debug("gmac_hwqueue_rxconsume(%p): ifq[%zu]=%p(@%#zx) %d@swfq\n", 784 hwq, depth, m, map->dm_segs->ds_addr, m->m_len); 785 if (le32toh(d->d_bufaddr) == map->dm_segs->ds_addr) { 786 *mp = m->m_nextpkt; 787 if (hwq->hwq_producer->hwq_ifq.ifq_tail == m) 788 hwq->hwq_producer->hwq_ifq.ifq_tail = last_m; 789 hwq->hwq_producer->hwq_ifq.ifq_len--; 790 break; 791 } 792 } 793 aprint_debug("gmac_hwqueue_rxconsume(%p): ifp=%p(%s) m=%p@%zu", 794 hwq, hwq->hwq_ifp, hwq->hwq_ifp->if_xname, m, depth); 795 if (m) 796 aprint_debug(" swfq[%d]=%#x\n", m->m_len, 797 hwq->hwq_producer->hwq_base[m->m_len].d_bufaddr); 798 aprint_debug("\n"); 799 KASSERT(m != NULL); 800 801 { 802 struct mbuf *m0; 803 for (m0 = hwq->hwq_producer->hwq_ifq.ifq_head; m0 != NULL; m0 = m0->m_nextpkt) 804 KASSERT(m0 != m); 805 } 806 807 KASSERT(hwq->hwq_producer->hwq_base[m->m_len].d_bufaddr == d->d_bufaddr); 808 hwq->hwq_producer->hwq_base[m->m_len].d_bufaddr = htole32(0xdead0000 | m->m_len); 809 810 m->m_len = buflen; 811 if (d->d_desc3 & DESC3_SOF) { 812 KASSERT(hwq->hwq_rxmbuf == NULL); 813 m->m_pkthdr.len = buflen; 814 buflen += 2; /* account for the pad */ 815 /* only modify m->m_data after we know mbuf is good. */ 816 } else { 817 KASSERT(hwq->hwq_rxmbuf != NULL); 818 hwq->hwq_rxmbuf->m_pkthdr.len += buflen; 819 } 820 821 map = M_GETCTX(m, bus_dmamap_t); 822 823 /* 824 * Sync the buffer contents, unload the dmamap, and save it away. 825 */ 826 bus_dmamap_sync(hqm->hqm_dmat, map, 0, buflen, BUS_DMASYNC_POSTREAD); 827 bus_dmamap_unload(hqm->hqm_dmat, map); 828 M_SETCTX(m, NULL); 829 gmac_mapcache_put(hqm->hqm_mc, map); 830 831 /* 832 * Now we build our new packet chain by tacking this on the end. 833 */ 834 *hwq->hwq_mp = m; 835 if ((d->d_desc3 & DESC3_EOF) == 0) { 836 /* 837 * Not last frame, so make sure the next gets appended right. 838 */ 839 hwq->hwq_mp = &m->m_next; 840 return true; 841 } 842 843 #if 0 844 /* 845 * We have a complete frame, let's try to deliver it. 846 */ 847 m->m_len -= ETHER_CRC_LEN; /* remove the CRC from the end */ 848 #endif 849 850 /* 851 * Now get the whole chain. 852 */ 853 m = hwq->hwq_rxmbuf; 854 m_set_rcvif(m, ifp); /* set receive interface */ 855 switch (DESC0_RXSTS_GET(d->d_desc0)) { 856 case DESC0_RXSTS_GOOD: 857 case DESC0_RXSTS_LONG: 858 m->m_data += 2; 859 if_percpuq_enqueue(ifp->if_percpuq, m); 860 break; 861 default: 862 if_statinc(ifp, if_ierrors); 863 m_freem(m); 864 break; 865 } 866 hwq->hwq_rxmbuf = NULL; 867 hwq->hwq_mp = &hwq->hwq_rxmbuf; 868 869 return true; 870 } 871 872 size_t 873 gmac_hwqueue_consume(gmac_hwqueue_t *hwq, size_t free_min) 874 { 875 gmac_hwqmem_t * const hqm = hwq->hwq_hqm; 876 gmac_desc_t d; 877 uint32_t v; 878 uint16_t rptr; 879 size_t i; 880 881 KASSERT((hqm->hqm_flags & HQM_PRODUCER) == 0); 882 883 aprint_debug("gmac_hwqueue_consume(%p): entry\n", hwq); 884 885 886 v = bus_space_read_4(hwq->hwq_iot, hwq->hwq_qrwptr_ioh, 0); 887 rptr = (v >> 0) & 0xffff; 888 hwq->hwq_wptr = (v >> 16) & 0xffff; 889 KASSERT(rptr == hwq->hwq_rptr); 890 if (rptr == hwq->hwq_wptr) 891 return 0; 892 893 i = 0; 894 for (; rptr != hwq->hwq_wptr; rptr = (rptr + 1) & (hwq->hwq_size - 1)) { 895 bus_dmamap_sync(hqm->hqm_dmat, hqm->hqm_dmamap, 896 sizeof(gmac_desc_t [hwq->hwq_qoff + rptr]), 897 sizeof(gmac_desc_t), 898 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 899 d.d_desc0 = le32toh(hwq->hwq_base[rptr].d_desc0); 900 d.d_desc1 = le32toh(hwq->hwq_base[rptr].d_desc1); 901 d.d_bufaddr = le32toh(hwq->hwq_base[rptr].d_bufaddr); 902 d.d_desc3 = le32toh(hwq->hwq_base[rptr].d_desc3); 903 hwq->hwq_base[rptr].d_desc0 = 0; 904 hwq->hwq_base[rptr].d_desc1 = 0; 905 hwq->hwq_base[rptr].d_bufaddr = 0xdeadbeef; 906 hwq->hwq_base[rptr].d_desc3 = 0; 907 bus_dmamap_sync(hqm->hqm_dmat, hqm->hqm_dmamap, 908 sizeof(gmac_desc_t [hwq->hwq_qoff + rptr]), 909 sizeof(gmac_desc_t), 910 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 911 912 aprint_debug("gmac_hwqueue_consume(%p): rptr=%u\n", 913 hwq, rptr); 914 if (!gmac_hwqueue_rxconsume(hwq, &d)) { 915 rptr = (rptr + 1) & (hwq->hwq_size - 1); 916 i += gmac_rxproduce(hwq->hwq_producer, free_min); 917 break; 918 } 919 } 920 921 /* 922 * Update hardware's copy of rptr. (wptr is RO). 923 */ 924 aprint_debug("gmac_hwqueue_consume(%p): rptr old=%u new=%u wptr=%u\n", 925 hwq, hwq->hwq_rptr, rptr, hwq->hwq_wptr); 926 bus_space_write_4(hwq->hwq_iot, hwq->hwq_qrwptr_ioh, 0, rptr); 927 hwq->hwq_rptr = rptr; 928 929 aprint_debug("gmac_hwqueue_consume(%p): exit\n", hwq); 930 931 return i; 932 } 933 934 void 935 gmac_hwqmem_destroy(gmac_hwqmem_t *hqm) 936 { 937 if (hqm->hqm_nsegs) { 938 if (hqm->hqm_base) { 939 if (hqm->hqm_dmamap) { 940 if (hqm->hqm_dmamap->dm_mapsize) { 941 bus_dmamap_unload(hqm->hqm_dmat, 942 hqm->hqm_dmamap); 943 } 944 bus_dmamap_destroy(hqm->hqm_dmat, 945 hqm->hqm_dmamap); 946 } 947 bus_dmamem_unmap(hqm->hqm_dmat, hqm->hqm_base, 948 hqm->hqm_memsize); 949 } 950 bus_dmamem_free(hqm->hqm_dmat, hqm->hqm_segs, hqm->hqm_nsegs); 951 } 952 953 kmem_free(hqm, sizeof(*hqm)); 954 } 955 956 gmac_hwqmem_t * 957 gmac_hwqmem_create(gmac_mapcache_t *mc, size_t ndesc, size_t nqueue, int flags) 958 { 959 gmac_hwqmem_t *hqm; 960 int error; 961 962 KASSERT(ndesc > 0 && ndesc <= 2048); 963 KASSERT((ndesc & (ndesc - 1)) == 0); 964 965 hqm = kmem_zalloc(sizeof(*hqm), KM_SLEEP); 966 hqm->hqm_memsize = nqueue * sizeof(gmac_desc_t [ndesc]); 967 hqm->hqm_mc = mc; 968 hqm->hqm_dmat = mc->mc_dmat; 969 hqm->hqm_ndesc = ndesc; 970 hqm->hqm_nqueue = nqueue; 971 hqm->hqm_flags = flags; 972 973 error = bus_dmamem_alloc(hqm->hqm_dmat, hqm->hqm_memsize, 0, 0, 974 hqm->hqm_segs, 1, &hqm->hqm_nsegs, BUS_DMA_WAITOK); 975 if (error) { 976 KASSERT(error == 0); 977 goto failed; 978 } 979 KASSERT(hqm->hqm_nsegs == 1); 980 error = bus_dmamem_map(hqm->hqm_dmat, hqm->hqm_segs, hqm->hqm_nsegs, 981 hqm->hqm_memsize, (void **)&hqm->hqm_base, BUS_DMA_WAITOK); 982 if (error) { 983 KASSERT(error == 0); 984 goto failed; 985 } 986 error = bus_dmamap_create(hqm->hqm_dmat, hqm->hqm_memsize, 987 hqm->hqm_nsegs, hqm->hqm_memsize, 0, 988 BUS_DMA_WAITOK|BUS_DMA_ALLOCNOW, &hqm->hqm_dmamap); 989 if (error) { 990 KASSERT(error == 0); 991 goto failed; 992 } 993 error = bus_dmamap_load(hqm->hqm_dmat, hqm->hqm_dmamap, hqm->hqm_base, 994 hqm->hqm_memsize, NULL, 995 BUS_DMA_WAITOK|BUS_DMA_WRITE|BUS_DMA_READ|BUS_DMA_COHERENT); 996 if (error) { 997 aprint_debug("gmac_hwqmem_create: ds_addr=%zu ds_len=%zu\n", 998 hqm->hqm_segs->ds_addr, hqm->hqm_segs->ds_len); 999 aprint_debug("gmac_hwqmem_create: bus_dmamap_load: %d\n", error); 1000 KASSERT(error == 0); 1001 goto failed; 1002 } 1003 1004 memset(hqm->hqm_base, 0, hqm->hqm_memsize); 1005 if ((flags & HQM_PRODUCER) == 0) 1006 bus_dmamap_sync(hqm->hqm_dmat, hqm->hqm_dmamap, 0, 1007 hqm->hqm_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1008 1009 return hqm; 1010 1011 failed: 1012 gmac_hwqmem_destroy(hqm); 1013 return NULL; 1014 } 1015 1016 void 1017 gmac_hwqueue_destroy(gmac_hwqueue_t *hwq) 1018 { 1019 gmac_hwqmem_t * const hqm = hwq->hwq_hqm; 1020 KASSERT(hqm->hqm_refs & hwq->hwq_ref); 1021 hqm->hqm_refs &= ~hwq->hwq_ref; 1022 for (;;) { 1023 struct mbuf *m; 1024 bus_dmamap_t map; 1025 IF_DEQUEUE(&hwq->hwq_ifq, m); 1026 if (m == NULL) 1027 break; 1028 map = M_GETCTX(m, bus_dmamap_t); 1029 bus_dmamap_unload(hqm->hqm_dmat, map); 1030 gmac_mapcache_put(hqm->hqm_mc, map); 1031 m_freem(m); 1032 } 1033 kmem_free(hwq, sizeof(*hwq)); 1034 } 1035 1036 gmac_hwqueue_t * 1037 gmac_hwqueue_create(gmac_hwqmem_t *hqm, 1038 bus_space_tag_t iot, bus_space_handle_t ioh, 1039 bus_size_t qrwptr, bus_size_t qbase, 1040 size_t qno) 1041 { 1042 const size_t log2_memsize = ffs(hqm->hqm_ndesc) - 1; 1043 gmac_hwqueue_t *hwq; 1044 uint32_t v; 1045 1046 KASSERT(qno < hqm->hqm_nqueue); 1047 KASSERT((hqm->hqm_refs & (1 << qno)) == 0); 1048 1049 hwq = kmem_zalloc(sizeof(*hwq), KM_SLEEP); 1050 hwq->hwq_size = hqm->hqm_ndesc; 1051 hwq->hwq_iot = iot; 1052 bus_space_subregion(iot, ioh, qrwptr, sizeof(uint32_t), 1053 &hwq->hwq_qrwptr_ioh); 1054 1055 hwq->hwq_hqm = hqm; 1056 hwq->hwq_ref = 1 << qno; 1057 hqm->hqm_refs |= hwq->hwq_ref; 1058 hwq->hwq_qoff = hqm->hqm_ndesc * qno; 1059 hwq->hwq_base = hqm->hqm_base + hwq->hwq_qoff; 1060 1061 if (qno == 0) { 1062 bus_space_write_4(hwq->hwq_iot, ioh, qbase, 1063 hqm->hqm_dmamap->dm_segs[0].ds_addr | (log2_memsize)); 1064 } 1065 1066 v = bus_space_read_4(hwq->hwq_iot, hwq->hwq_qrwptr_ioh, 0); 1067 hwq->hwq_rptr = (v >> 0) & 0xffff; 1068 hwq->hwq_wptr = (v >> 16) & 0xffff; 1069 1070 aprint_debug("gmac_hwqueue_create: %p: qrwptr=%zu(%#zx) wptr=%u rptr=%u" 1071 " base=%p@%#zx(%#x) qno=%zu\n", 1072 hwq, qrwptr, hwq->hwq_qrwptr_ioh, hwq->hwq_wptr, hwq->hwq_rptr, 1073 hwq->hwq_base, 1074 hqm->hqm_segs->ds_addr + sizeof(gmac_desc_t [hwq->hwq_qoff]), 1075 bus_space_read_4(hwq->hwq_iot, ioh, qbase), qno); 1076 1077 hwq->hwq_free = hwq->hwq_size - 1; 1078 hwq->hwq_ifq.ifq_maxlen = hwq->hwq_free; 1079 hwq->hwq_mp = &hwq->hwq_rxmbuf; 1080 1081 return hwq; 1082 } 1083
Indexes created Wed Sep 24 15:09:51 GMT 2025