gemini_gmac.c revision 1.21
1 /* $NetBSD: gemini_gmac.c,v 1.21 2021/04/24 23:36:27 thorpej Exp $ */ 2 /*- 3 * Copyright (c) 2008 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Matt Thomas <matt (at) 3am-software.com> 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 19 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 20 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 21 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include "locators.h" 32 #include <sys/param.h> 33 #include <sys/device.h> 34 #include <sys/kmem.h> 35 #include <sys/mbuf.h> 36 37 #include <net/if.h> 38 #include <net/if_ether.h> 39 40 #include <sys/bus.h> 41 42 #include <arm/gemini/gemini_reg.h> 43 #include <arm/gemini/gemini_obiovar.h> 44 #include <arm/gemini/gemini_gmacvar.h> 45 #include <arm/gemini/gemini_gpiovar.h> 46 47 #include <dev/mii/mii.h> 48 #include <dev/mii/mii_bitbang.h> 49 50 #include <sys/gpio.h> 51 52 __KERNEL_RCSID(0, "$NetBSD: gemini_gmac.c,v 1.21 2021/04/24 23:36:27 thorpej Exp $"); 53 54 #define SWFREEQ_DESCS 256 /* one page worth */ 55 #define HWFREEQ_DESCS 256 /* one page worth */ 56 57 static int geminigmac_match(device_t, cfdata_t, void *); 58 static void geminigmac_attach(device_t, device_t, void *); 59 static int geminigmac_find(device_t, cfdata_t, const int *, void *); 60 static int geminigmac_print(void *aux, const char *name); 61 62 static int geminigmac_mii_readreg(device_t, int, int, uint16_t *); 63 static int geminigmac_mii_writereg(device_t, int, int, uint16_t); 64 65 #define GPIO_MDIO 21 66 #define GPIO_MDCLK 22 67 68 #define MDIN __BIT(3) 69 #define MDOUT __BIT(2) 70 #define MDCLK __BIT(1) 71 #define MDTOPHY __BIT(0) 72 73 CFATTACH_DECL_NEW(geminigmac, sizeof(struct gmac_softc), 74 geminigmac_match, geminigmac_attach, NULL, NULL); 75 76 extern struct cfdriver geminigmac_cd; 77 extern struct cfdriver geminigpio_cd; 78 79 void 80 gmac_swfree_min_update(struct gmac_softc *sc) 81 { 82 uint32_t v; 83 84 if (sc->sc_swfreeq != NULL 85 && sc->sc_swfree_min > sc->sc_swfreeq->hwq_size - 1) 86 sc->sc_swfree_min = sc->sc_swfreeq->hwq_size - 1; 87 88 v = bus_space_read_4(sc->sc_iot, sc->sc_ioh, GMAC_QFE_THRESHOLD); 89 v &= ~QFE_SWFQ_THRESHOLD_MASK; 90 v |= QFE_SWFQ_THRESHOLD(sc->sc_swfree_min); 91 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GMAC_QFE_THRESHOLD, v); 92 } 93 94 void 95 gmac_intr_update(struct gmac_softc *sc) 96 { 97 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GMAC_INT0_MASK, 98 ~sc->sc_int_enabled[0]); 99 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GMAC_INT1_MASK, 100 ~sc->sc_int_enabled[1]); 101 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GMAC_INT2_MASK, 102 ~sc->sc_int_enabled[2]); 103 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GMAC_INT3_MASK, 104 ~sc->sc_int_enabled[3]); 105 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GMAC_INT4_MASK, 106 ~sc->sc_int_enabled[4]); 107 } 108 109 static void 110 gmac_init(struct gmac_softc *sc) 111 { 112 gmac_hwqmem_t *hqm; 113 114 /* 115 * This shouldn't be needed. 116 */ 117 for (bus_size_t i = 0; i < GMAC_TOE_QH_SIZE; i += 4) { 118 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 119 GMAC_TOE_QH_OFFSET + i, 0); 120 } 121 #if 0 122 { 123 bus_space_handle_t global_ioh; 124 int error; 125 126 error = bus_space_map(sc->sc_iot, GEMINI_GLOBAL_BASE, 4, 0, 127 &global_ioh); 128 KASSERT(error == 0); 129 aprint_normal_dev(sc->sc_dev, "gmac_init: global_ioh=%#zx\n", global_ioh); 130 bus_space_write_4(sc->sc_iot, global_ioh, GEMINI_GLOBAL_RESET_CTL, 131 GLOBAL_RESET_GMAC0|GLOBAL_RESET_GMAC1); 132 do { 133 v = bus_space_read_4(sc->sc_iot, global_ioh, 134 GEMINI_GLOBAL_RESET_CTL); 135 } while (v & (GLOBAL_RESET_GMAC0|GLOBAL_RESET_GMAC1)); 136 bus_space_unmap(sc->sc_iot, global_ioh, 4); 137 DELAY(1000); 138 } 139 #endif 140 141 sc->sc_swfree_min = 4; /* MIN_RXMAPS; */ 142 143 gmac_swfree_min_update(sc); 144 145 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GMAC_SKBSIZE, 146 SKB_SIZE_SET(PAGE_SIZE, MCLBYTES)); 147 148 sc->sc_int_select[0] = INT0_GMAC1; 149 sc->sc_int_select[1] = INT1_GMAC1; 150 sc->sc_int_select[2] = INT2_GMAC1; 151 sc->sc_int_select[3] = INT3_GMAC1; 152 sc->sc_int_select[4] = INT4_GMAC1; 153 154 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GMAC_INT0_SELECT, INT0_GMAC1); 155 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GMAC_INT1_SELECT, INT1_GMAC1); 156 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GMAC_INT2_SELECT, INT2_GMAC1); 157 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GMAC_INT3_SELECT, INT3_GMAC1); 158 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GMAC_INT4_SELECT, INT4_GMAC1); 159 160 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GMAC_INT0_STATUS, ~0); 161 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GMAC_INT1_STATUS, ~0); 162 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GMAC_INT2_STATUS, ~0); 163 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GMAC_INT3_STATUS, ~0); 164 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GMAC_INT4_STATUS, ~0); 165 166 gmac_intr_update(sc); 167 168 aprint_debug_dev(sc->sc_dev, "gmac_init: sts=%#x/%#x/%#x/%#x/%#x\n", 169 bus_space_read_4(sc->sc_iot, sc->sc_ioh, GMAC_INT0_STATUS), 170 bus_space_read_4(sc->sc_iot, sc->sc_ioh, GMAC_INT1_STATUS), 171 bus_space_read_4(sc->sc_iot, sc->sc_ioh, GMAC_INT2_STATUS), 172 bus_space_read_4(sc->sc_iot, sc->sc_ioh, GMAC_INT3_STATUS), 173 bus_space_read_4(sc->sc_iot, sc->sc_ioh, GMAC_INT4_STATUS)); 174 175 aprint_debug_dev(sc->sc_dev, "gmac_init: mask=%#x/%#x/%#x/%#x/%#x\n", 176 bus_space_read_4(sc->sc_iot, sc->sc_ioh, GMAC_INT0_MASK), 177 bus_space_read_4(sc->sc_iot, sc->sc_ioh, GMAC_INT1_MASK), 178 bus_space_read_4(sc->sc_iot, sc->sc_ioh, GMAC_INT2_MASK), 179 bus_space_read_4(sc->sc_iot, sc->sc_ioh, GMAC_INT3_MASK), 180 bus_space_read_4(sc->sc_iot, sc->sc_ioh, GMAC_INT4_MASK)); 181 182 aprint_debug_dev(sc->sc_dev, "gmac_init: select=%#x/%#x/%#x/%#x/%#x\n", 183 bus_space_read_4(sc->sc_iot, sc->sc_ioh, GMAC_INT0_SELECT), 184 bus_space_read_4(sc->sc_iot, sc->sc_ioh, GMAC_INT1_SELECT), 185 bus_space_read_4(sc->sc_iot, sc->sc_ioh, GMAC_INT2_SELECT), 186 bus_space_read_4(sc->sc_iot, sc->sc_ioh, GMAC_INT3_SELECT), 187 bus_space_read_4(sc->sc_iot, sc->sc_ioh, GMAC_INT4_SELECT)); 188 189 aprint_debug_dev(sc->sc_dev, "gmac_init: create rx dmamap cache\n"); 190 /* 191 * Allocate the cache for receive dmamaps. 192 */ 193 sc->sc_rxmaps = gmac_mapcache_create(sc->sc_dmat, MAX_RXMAPS, 194 MCLBYTES, 1); 195 KASSERT(sc->sc_rxmaps != NULL); 196 197 aprint_debug_dev(sc->sc_dev, "gmac_init: create tx dmamap cache\n"); 198 /* 199 * Allocate the cache for transmit dmamaps. 200 */ 201 sc->sc_txmaps = gmac_mapcache_create(sc->sc_dmat, MAX_TXMAPS, 202 ETHERMTU_JUMBO + ETHER_HDR_LEN, 16); 203 KASSERT(sc->sc_txmaps != NULL); 204 205 aprint_debug_dev(sc->sc_dev, "gmac_init: create sw freeq\n"); 206 /* 207 * Allocate the memory for sw (receive) free queue 208 */ 209 hqm = gmac_hwqmem_create(sc->sc_rxmaps, 32 /*SWFREEQ_DESCS*/, 1, 210 HQM_PRODUCER|HQM_RX); 211 sc->sc_swfreeq = gmac_hwqueue_create(hqm, sc->sc_iot, sc->sc_ioh, 212 GMAC_SWFREEQ_RWPTR, GMAC_SWFREEQ_BASE, 0); 213 KASSERT(sc->sc_swfreeq != NULL); 214 215 aprint_debug_dev(sc->sc_dev, "gmac_init: create hw freeq\n"); 216 /* 217 * Allocate the memory for hw (receive) free queue 218 */ 219 hqm = gmac_hwqmem_create(sc->sc_rxmaps, HWFREEQ_DESCS, 1, 220 HQM_PRODUCER|HQM_RX); 221 sc->sc_hwfreeq = gmac_hwqueue_create(hqm, sc->sc_iot, sc->sc_ioh, 222 GMAC_HWFREEQ_RWPTR, GMAC_HWFREEQ_BASE, 0); 223 KASSERT(sc->sc_hwfreeq != NULL); 224 225 aprint_debug_dev(sc->sc_dev, "gmac_init: done\n"); 226 } 227 228 int 229 geminigmac_match(device_t parent, cfdata_t cf, void *aux) 230 { 231 struct obio_attach_args *obio = aux; 232 233 if (obio->obio_addr != GEMINI_GMAC_BASE) 234 return 0; 235 236 return 1; 237 } 238 239 void 240 geminigmac_attach(device_t parent, device_t self, void *aux) 241 { 242 struct gmac_softc *sc = device_private(self); 243 struct obio_attach_args *obio = aux; 244 struct gmac_attach_args gma; 245 cfdata_t cf; 246 uint32_t v; 247 int error; 248 249 sc->sc_dev = self; 250 sc->sc_iot = obio->obio_iot; 251 sc->sc_dmat = obio->obio_dmat; 252 sc->sc_gpio_dev = geminigpio_cd.cd_devs[0]; 253 sc->sc_gpio_mdclk = GPIO_MDCLK; 254 sc->sc_gpio_mdout = GPIO_MDIO; 255 sc->sc_gpio_mdin = GPIO_MDIO; 256 KASSERT(sc->sc_gpio_dev != NULL); 257 258 error = bus_space_map(sc->sc_iot, obio->obio_addr, obio->obio_size, 0, 259 &sc->sc_ioh); 260 if (error) { 261 aprint_error(": error mapping registers: %d", error); 262 return; 263 } 264 265 v = bus_space_read_4(sc->sc_iot, sc->sc_ioh, 0); 266 aprint_normal(": devid %d rev %d\n", GMAC_TOE_DEVID(v), 267 GMAC_TOE_REVID(v)); 268 aprint_naive("\n"); 269 270 mutex_init(&sc->sc_mdiolock, MUTEX_DEFAULT, IPL_NET); 271 272 /* 273 * Initialize the GPIO pins 274 */ 275 geminigpio_pin_ctl(sc->sc_gpio_dev, sc->sc_gpio_mdclk, GPIO_PIN_OUTPUT); 276 geminigpio_pin_ctl(sc->sc_gpio_dev, sc->sc_gpio_mdout, GPIO_PIN_OUTPUT); 277 if (sc->sc_gpio_mdout != sc->sc_gpio_mdin) 278 geminigpio_pin_ctl(sc->sc_gpio_dev, sc->sc_gpio_mdin, 279 GPIO_PIN_INPUT); 280 281 /* 282 * Set the MDIO GPIO pins to a known state. 283 */ 284 geminigpio_pin_write(sc->sc_gpio_dev, sc->sc_gpio_mdclk, 0); 285 geminigpio_pin_write(sc->sc_gpio_dev, sc->sc_gpio_mdout, 0); 286 sc->sc_mdiobits = MDCLK; 287 288 gmac_init(sc); 289 290 gma.gma_iot = sc->sc_iot; 291 gma.gma_ioh = sc->sc_ioh; 292 gma.gma_dmat = sc->sc_dmat; 293 294 gma.gma_mii_readreg = geminigmac_mii_readreg; 295 gma.gma_mii_writereg = geminigmac_mii_writereg; 296 297 gma.gma_port = 0; 298 gma.gma_phy = -1; 299 gma.gma_intr = 1; 300 301 cf = config_search(sc->sc_dev, &gma, 302 CFARG_SUBMATCH, geminigmac_find, 303 CFARG_IATTR, geminigmac_cd.cd_name, 304 CFARG_EOL); 305 if (cf != NULL) 306 config_attach(sc->sc_dev, cf, &gma, geminigmac_print, 307 CFARG_EOL); 308 309 gma.gma_port = 1; 310 gma.gma_phy = -1; 311 gma.gma_intr = 2; 312 313 cf = config_search(sc->sc_dev, &gma, 314 CFARG_SUBMATCH, geminigmac_find, 315 CFARG_IATTR, geminigmac_cd.cd_name, 316 CFARG_EOL); 317 if (cf != NULL) 318 config_attach(sc->sc_dev, cf, &gma, geminigmac_print, 319 CFARG_EOL); 320 } 321 322 static int 323 geminigmac_find(device_t parent, cfdata_t cf, const int *ldesc, void *aux) 324 { 325 struct gmac_attach_args * const gma = aux; 326 327 if (gma->gma_port != cf->cf_loc[GEMINIGMACCF_PORT]) 328 return 0; 329 if (gma->gma_intr != cf->cf_loc[GEMINIGMACCF_INTR]) 330 return 0; 331 332 gma->gma_phy = cf->cf_loc[GEMINIGMACCF_PHY]; 333 gma->gma_intr = cf->cf_loc[GEMINIGMACCF_INTR]; 334 335 return config_match(parent, cf, gma); 336 } 337 338 static int 339 geminigmac_print(void *aux, const char *name) 340 { 341 struct gmac_attach_args * const gma = aux; 342 343 aprint_normal(" port %d", gma->gma_port); 344 aprint_normal(" phy %d", gma->gma_phy); 345 aprint_normal(" intr %d", gma->gma_intr); 346 347 return UNCONF; 348 } 349 350 static uint32_t 351 gemini_gmac_gpio_read(device_t dv) 352 { 353 struct gmac_softc * const sc = device_private(dv); 354 int value = geminigpio_pin_read(sc->sc_gpio_dev, GPIO_MDIO); 355 356 KASSERT((sc->sc_mdiobits & MDTOPHY) == 0); 357 358 return value ? MDIN : 0; 359 } 360 361 static void 362 gemini_gmac_gpio_write(device_t dv, uint32_t bits) 363 { 364 struct gmac_softc * const sc = device_private(dv); 365 366 if ((sc->sc_mdiobits ^ bits) & MDTOPHY) { 367 int flags = (bits & MDTOPHY) ? GPIO_PIN_OUTPUT : GPIO_PIN_INPUT; 368 geminigpio_pin_ctl(sc->sc_gpio_dev, GPIO_MDIO, flags); 369 } 370 371 if ((sc->sc_mdiobits ^ bits) & MDOUT) { 372 int flags = ((bits & MDOUT) != 0); 373 geminigpio_pin_write(sc->sc_gpio_dev, GPIO_MDIO, flags); 374 } 375 376 if ((sc->sc_mdiobits ^ bits) & MDCLK) { 377 int flags = ((bits & MDCLK) != 0); 378 geminigpio_pin_write(sc->sc_gpio_dev, GPIO_MDCLK, flags); 379 } 380 381 sc->sc_mdiobits = bits; 382 } 383 384 static const struct mii_bitbang_ops geminigmac_mii_bitbang_ops = { 385 .mbo_read = gemini_gmac_gpio_read, 386 .mbo_write = gemini_gmac_gpio_write, 387 .mbo_bits[MII_BIT_MDO] = MDOUT, 388 .mbo_bits[MII_BIT_MDI] = MDIN, 389 .mbo_bits[MII_BIT_MDC] = MDCLK, 390 .mbo_bits[MII_BIT_DIR_HOST_PHY] = MDTOPHY, 391 }; 392 393 int 394 geminigmac_mii_readreg(device_t dv, int phy, int reg, uint16_t *val) 395 { 396 device_t parent = device_parent(dv); 397 struct gmac_softc * const sc = device_private(parent); 398 int rv; 399 400 mutex_enter(&sc->sc_mdiolock); 401 rv = mii_bitbang_readreg(parent, &geminigmac_mii_bitbang_ops, phy, 402 reg, val); 403 mutex_exit(&sc->sc_mdiolock); 404 405 //aprint_debug_dev(dv, "mii_readreg(%d, %d): %#x\n", phy, reg, rv); 406 407 return rv; 408 } 409 410 int 411 geminigmac_mii_writereg(device_t dv, int phy, int reg, uint16_t val) 412 { 413 device_t parent = device_parent(dv); 414 struct gmac_softc * const sc = device_private(parent); 415 416 //aprint_debug_dev(dv, "mii_writereg(%d, %d, %#x)\n", phy, reg, val); 417 418 mutex_enter(&sc->sc_mdiolock); 419 rv = mii_bitbang_writereg(parent, &geminigmac_mii_bitbang_ops, phy, 420 reg, val); 421 mutex_exit(&sc->sc_mdiolock); 422 423 return rv; 424 } 425 426 427 gmac_mapcache_t * 428 gmac_mapcache_create(bus_dma_tag_t dmat, size_t maxmaps, bus_size_t mapsize, 429 int nsegs) 430 { 431 gmac_mapcache_t *mc; 432 433 mc = kmem_zalloc(offsetof(gmac_mapcache_t, mc_maps[maxmaps]), 434 KM_SLEEP); 435 if (mc == NULL) 436 return NULL; 437 438 mc->mc_max = maxmaps; 439 mc->mc_dmat = dmat; 440 mc->mc_mapsize = mapsize; 441 mc->mc_nsegs = nsegs; 442 return mc; 443 } 444 445 void 446 gmac_mapcache_destroy(gmac_mapcache_t **mc_p) 447 { 448 gmac_mapcache_t *mc = *mc_p; 449 450 if (mc == NULL) 451 return; 452 453 KASSERT(mc->mc_used == 0); 454 while (mc->mc_free-- > 0) { 455 KASSERT(mc->mc_maps[mc->mc_free] != NULL); 456 bus_dmamap_destroy(mc->mc_dmat, mc->mc_maps[mc->mc_free]); 457 mc->mc_maps[mc->mc_free] = NULL; 458 } 459 460 kmem_free(mc, offsetof(gmac_mapcache_t, mc_maps[mc->mc_max])); 461 *mc_p = NULL; 462 } 463 464 int 465 gmac_mapcache_fill(gmac_mapcache_t *mc, size_t limit) 466 { 467 int error; 468 469 KASSERT(limit <= mc->mc_max); 470 aprint_debug("gmac_mapcache_fill(%p): limit=%zu used=%zu free=%zu\n", 471 mc, limit, mc->mc_used, mc->mc_free); 472 473 for (error = 0; mc->mc_free + mc->mc_used < limit; mc->mc_free++) { 474 KASSERT(mc->mc_maps[mc->mc_free] == NULL); 475 error = bus_dmamap_create(mc->mc_dmat, mc->mc_mapsize, 476 mc->mc_nsegs, mc->mc_mapsize, 0, 477 BUS_DMA_ALLOCNOW|BUS_DMA_WAITOK, 478 &mc->mc_maps[mc->mc_free]); 479 if (error) 480 break; 481 } 482 aprint_debug("gmac_mapcache_fill(%p): limit=%zu used=%zu free=%zu\n", 483 mc, limit, mc->mc_used, mc->mc_free); 484 485 return error; 486 } 487 488 bus_dmamap_t 489 gmac_mapcache_get(gmac_mapcache_t *mc) 490 { 491 bus_dmamap_t map; 492 493 KASSERT(mc != NULL); 494 495 if (mc->mc_free == 0) { 496 int error; 497 if (mc->mc_used == mc->mc_max) 498 return NULL; 499 error = bus_dmamap_create(mc->mc_dmat, mc->mc_mapsize, 500 mc->mc_nsegs, mc->mc_mapsize, 0, 501 BUS_DMA_ALLOCNOW|BUS_DMA_NOWAIT, 502 &map); 503 if (error) 504 return NULL; 505 KASSERT(mc->mc_maps[mc->mc_free] == NULL); 506 } else { 507 KASSERT(mc->mc_free <= mc->mc_max); 508 map = mc->mc_maps[--mc->mc_free]; 509 mc->mc_maps[mc->mc_free] = NULL; 510 } 511 mc->mc_used++; 512 KASSERT(map != NULL); 513 514 return map; 515 } 516 517 void 518 gmac_mapcache_put(gmac_mapcache_t *mc, bus_dmamap_t map) 519 { 520 KASSERT(mc->mc_free + mc->mc_used < mc->mc_max); 521 KASSERT(mc->mc_maps[mc->mc_free] == NULL); 522 523 mc->mc_maps[mc->mc_free++] = map; 524 mc->mc_used--; 525 } 526 527 gmac_desc_t * 528 gmac_hwqueue_desc(gmac_hwqueue_t *hwq, size_t i) 529 { 530 i += hwq->hwq_wptr; 531 if (i >= hwq->hwq_size) 532 i -= hwq->hwq_size; 533 return hwq->hwq_base + i; 534 } 535 536 static void 537 gmac_hwqueue_txconsume(gmac_hwqueue_t *hwq, const gmac_desc_t *d) 538 { 539 gmac_hwqmem_t * const hqm = hwq->hwq_hqm; 540 struct ifnet *ifp; 541 bus_dmamap_t map; 542 struct mbuf *m; 543 544 IF_DEQUEUE(&hwq->hwq_ifq, m); 545 KASSERT(m != NULL); 546 map = M_GETCTX(m, bus_dmamap_t); 547 548 bus_dmamap_sync(hqm->hqm_dmat, map, 0, map->dm_mapsize, 549 BUS_DMASYNC_POSTWRITE); 550 bus_dmamap_unload(hqm->hqm_dmat, map); 551 M_SETCTX(m, NULL); 552 gmac_mapcache_put(hqm->hqm_mc, map); 553 554 ifp = hwq->hwq_ifp; 555 if_statinc(ifp, if_opackets); 556 if_statiadd(ifp, if_obytes, m->m_pkthdr.len); 557 558 aprint_debug("gmac_hwqueue_txconsume(%p): %zu@%p: %s m=%p\n", 559 hwq, d - hwq->hwq_base, d, ifp->if_xname, m); 560 561 bpf_mtap(ifp, m, BPF_D_OUT); 562 m_freem(m); 563 } 564 565 void 566 gmac_hwqueue_sync(gmac_hwqueue_t *hwq) 567 { 568 gmac_hwqmem_t * const hqm = hwq->hwq_hqm; 569 uint32_t v; 570 uint16_t old_rptr; 571 size_t rptr; 572 573 KASSERT(hqm->hqm_flags & HQM_PRODUCER); 574 575 old_rptr = hwq->hwq_rptr; 576 v = bus_space_read_4(hwq->hwq_iot, hwq->hwq_qrwptr_ioh, 0); 577 hwq->hwq_rptr = (v >> 0) & 0xffff; 578 hwq->hwq_wptr = (v >> 16) & 0xffff; 579 580 if (old_rptr == hwq->hwq_rptr) 581 return; 582 583 aprint_debug("gmac_hwqueue_sync(%p): entry rptr old=%u new=%u free=%u(%u)\n", 584 hwq, old_rptr, hwq->hwq_rptr, hwq->hwq_free, 585 hwq->hwq_size - hwq->hwq_free - 1); 586 587 hwq->hwq_free += (hwq->hwq_rptr - old_rptr) & (hwq->hwq_size - 1); 588 for (rptr = old_rptr; 589 rptr != hwq->hwq_rptr; 590 rptr = (rptr + 1) & (hwq->hwq_size - 1)) { 591 gmac_desc_t * const d = hwq->hwq_base + rptr; 592 if (hqm->hqm_flags & HQM_TX) { 593 bus_dmamap_sync(hqm->hqm_dmat, hqm->hqm_dmamap, 594 sizeof(gmac_desc_t [hwq->hwq_qoff + rptr]), 595 sizeof(gmac_desc_t), 596 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 597 if (d->d_desc3 & htole32(DESC3_EOF)) 598 gmac_hwqueue_txconsume(hwq, d); 599 } else { 600 bus_dmamap_sync(hqm->hqm_dmat, hqm->hqm_dmamap, 601 sizeof(gmac_desc_t [hwq->hwq_qoff + rptr]), 602 sizeof(gmac_desc_t), 603 BUS_DMASYNC_POSTWRITE); 604 605 aprint_debug("gmac_hwqueue_sync(%p): %zu@%p=%#x/%#x/%#x/%#x\n", 606 hwq, rptr, d, d->d_desc0, d->d_desc1, 607 d->d_bufaddr, d->d_desc3); 608 bus_dmamap_sync(hqm->hqm_dmat, hqm->hqm_dmamap, 609 sizeof(gmac_desc_t [hwq->hwq_qoff + rptr]), 610 sizeof(gmac_desc_t), 611 BUS_DMASYNC_PREWRITE); 612 } 613 } 614 615 aprint_debug("gmac_hwqueue_sync(%p): exit rptr old=%u new=%u free=%u(%u)\n", 616 hwq, old_rptr, hwq->hwq_rptr, hwq->hwq_free, 617 hwq->hwq_size - hwq->hwq_free - 1); 618 } 619 620 void 621 gmac_hwqueue_produce(gmac_hwqueue_t *hwq, size_t count) 622 { 623 gmac_hwqmem_t * const hqm = hwq->hwq_hqm; 624 uint16_t wptr; 625 uint16_t rptr = bus_space_read_4(hwq->hwq_iot, hwq->hwq_qrwptr_ioh, 0); 626 627 KASSERT(count < hwq->hwq_free); 628 KASSERT(hqm->hqm_flags & HQM_PRODUCER); 629 KASSERT(hwq->hwq_wptr == bus_space_read_4(hwq->hwq_iot, hwq->hwq_qrwptr_ioh, 0) >> 16); 630 631 aprint_debug("gmac_hwqueue_produce(%p, %zu): rptr=%u(%u) wptr old=%u", 632 hwq, count, hwq->hwq_rptr, rptr, hwq->hwq_wptr); 633 634 hwq->hwq_free -= count; 635 #if 1 636 for (wptr = hwq->hwq_wptr; 637 count > 0; 638 count--, wptr = (wptr + 1) & (hwq->hwq_size - 1)) { 639 KASSERT(((wptr + 1) & (hwq->hwq_size - 1)) != hwq->hwq_rptr); 640 bus_dmamap_sync(hqm->hqm_dmat, hqm->hqm_dmamap, 641 sizeof(gmac_desc_t [hwq->hwq_qoff + wptr]), 642 sizeof(gmac_desc_t), 643 BUS_DMASYNC_PREWRITE); 644 } 645 KASSERT(count == 0); 646 hwq->hwq_wptr = wptr; 647 #else 648 if (hwq->hwq_wptr + count >= hwq->hwq_size) { 649 bus_dmamap_sync(hqm->hqm_dmat, hqm->hqm_dmamap, 650 sizeof(gmac_desc_t [hwq->hwq_qoff + hwq->hwq_wptr]), 651 sizeof(gmac_desc_t [hwq->hwq_size - hwq->hwq_wptr]), 652 BUS_DMASYNC_PREWRITE); 653 count -= hwq->hwq_size - hwq->hwq_wptr; 654 hwq->hwq_wptr = 0; 655 } 656 if (count > 0) { 657 bus_dmamap_sync(hqm->hqm_dmat, hqm->hqm_dmamap, 658 sizeof(gmac_desc_t [hwq->hwq_qoff + hwq->hwq_wptr]), 659 sizeof(gmac_desc_t [count]), 660 BUS_DMASYNC_PREWRITE); 661 hwq->hwq_wptr += count; 662 hwq->hwq_wptr &= (hwq->hwq_size - 1); 663 } 664 #endif 665 666 /* 667 * Tell the h/w we've produced a few more descriptors. 668 * (don't bother writing the rptr since it's RO). 669 */ 670 bus_space_write_4(hwq->hwq_iot, hwq->hwq_qrwptr_ioh, 0, 671 hwq->hwq_wptr << 16); 672 673 aprint_debug(" new=%u\n", hwq->hwq_wptr); 674 } 675 676 size_t 677 gmac_rxproduce(gmac_hwqueue_t *hwq, size_t free_min) 678 { 679 gmac_hwqmem_t * const hqm = hwq->hwq_hqm; 680 size_t i; 681 682 aprint_debug("gmac_rxproduce(%p): entry free=%u(%u) free_min=%zu ifq_len=%d\n", 683 hwq, hwq->hwq_free, hwq->hwq_size - hwq->hwq_free - 1, 684 free_min, hwq->hwq_ifq.ifq_len); 685 686 gmac_hwqueue_sync(hwq); 687 688 aprint_debug("gmac_rxproduce(%p): postsync free=%u(%u)\n", 689 hwq, hwq->hwq_free, hwq->hwq_size - hwq->hwq_free - 1); 690 691 for (i = 0; hwq->hwq_free > 0 && hwq->hwq_size - hwq->hwq_free - 1 < free_min; i++) { 692 bus_dmamap_t map; 693 gmac_desc_t * const d = gmac_hwqueue_desc(hwq, 0); 694 struct mbuf *m, *m0; 695 int error; 696 697 if (d->d_bufaddr && (le32toh(d->d_bufaddr) >> 16) != 0xdead) { 698 gmac_hwqueue_produce(hwq, 1); 699 continue; 700 } 701 702 map = gmac_mapcache_get(hqm->hqm_mc); 703 if (map == NULL) 704 break; 705 706 KASSERT(map->dm_mapsize == 0); 707 708 m = m_gethdr(M_DONTWAIT, MT_DATA); 709 if (m == NULL) { 710 gmac_mapcache_put(hqm->hqm_mc, map); 711 break; 712 } 713 714 MCLGET(m, M_DONTWAIT); 715 if ((m->m_flags & M_EXT) == 0) { 716 m_free(m); 717 gmac_mapcache_put(hqm->hqm_mc, map); 718 break; 719 } 720 error = bus_dmamap_load(hqm->hqm_dmat, map, m->m_data, 721 MCLBYTES, NULL, BUS_DMA_READ|BUS_DMA_NOWAIT); 722 if (error) { 723 m_free(m); 724 gmac_mapcache_put(hqm->hqm_mc, map); 725 aprint_error("gmac0: " 726 "map %p(%zu): can't map rx mbuf(%p) wptr=%u: %d\n", 727 map, map->_dm_size, m, hwq->hwq_wptr, error); 728 Debugger(); 729 break; 730 } 731 bus_dmamap_sync(hqm->hqm_dmat, map, 0, map->dm_mapsize, 732 BUS_DMASYNC_PREREAD); 733 m->m_pkthdr.len = 0; 734 M_SETCTX(m, map); 735 #if 0 736 d->d_desc0 = htole32(map->dm_segs->ds_len); 737 #endif 738 d->d_bufaddr = htole32(map->dm_segs->ds_addr); 739 for (m0 = hwq->hwq_ifq.ifq_head; m0 != NULL; m0 = m0->m_nextpkt) 740 KASSERT(m0 != m); 741 m->m_len = d - hwq->hwq_base; 742 IF_ENQUEUE(&hwq->hwq_ifq, m); 743 aprint_debug( 744 "gmac_rxproduce(%p): m=%p %zu@%p=%#x/%#x/%#x/%#x\n", hwq, 745 m, d - hwq->hwq_base, d, d->d_desc0, d->d_desc1, 746 d->d_bufaddr, d->d_desc3); 747 gmac_hwqueue_produce(hwq, 1); 748 } 749 750 aprint_debug("gmac_rxproduce(%p): exit free=%u(%u) free_min=%zu ifq_len=%d\n", 751 hwq, hwq->hwq_free, hwq->hwq_size - hwq->hwq_free - 1, 752 free_min, hwq->hwq_ifq.ifq_len); 753 754 return i; 755 } 756 757 static bool 758 gmac_hwqueue_rxconsume(gmac_hwqueue_t *hwq, const gmac_desc_t *d) 759 { 760 gmac_hwqmem_t * const hqm = hwq->hwq_hqm; 761 struct ifnet * const ifp = hwq->hwq_ifp; 762 size_t buflen = d->d_desc1 & 0xffff; 763 bus_dmamap_t map; 764 struct mbuf *m, *last_m, **mp; 765 size_t depth; 766 767 KASSERT(ifp != NULL); 768 769 aprint_debug("gmac_hwqueue_rxconsume(%p): entry\n", hwq); 770 771 aprint_debug("gmac_hwqueue_rxconsume(%p): ifp=%p(%s): %#x/%#x/%#x/%#x\n", 772 hwq, hwq->hwq_ifp, hwq->hwq_ifp->if_xname, 773 d->d_desc0, d->d_desc1, d->d_bufaddr, d->d_desc3); 774 775 if (d->d_bufaddr == 0 || d->d_bufaddr == 0xdeadbeef) 776 return false; 777 778 /* 779 * First we have to find this mbuf in the software free queue 780 * (the producer of the mbufs) and remove it. 781 */ 782 KASSERT(hwq->hwq_producer->hwq_free != hwq->hwq_producer->hwq_size - 1); 783 for (mp = &hwq->hwq_producer->hwq_ifq.ifq_head, last_m = NULL, depth=0; 784 (m = *mp) != NULL; 785 last_m = m, mp = &m->m_nextpkt, depth++) { 786 map = M_GETCTX(m, bus_dmamap_t); 787 KASSERT(map != NULL); 788 KASSERT(map->dm_nsegs == 1); 789 aprint_debug("gmac_hwqueue_rxconsume(%p): ifq[%zu]=%p(@%#zx) %d@swfq\n", 790 hwq, depth, m, map->dm_segs->ds_addr, m->m_len); 791 if (le32toh(d->d_bufaddr) == map->dm_segs->ds_addr) { 792 *mp = m->m_nextpkt; 793 if (hwq->hwq_producer->hwq_ifq.ifq_tail == m) 794 hwq->hwq_producer->hwq_ifq.ifq_tail = last_m; 795 hwq->hwq_producer->hwq_ifq.ifq_len--; 796 break; 797 } 798 } 799 aprint_debug("gmac_hwqueue_rxconsume(%p): ifp=%p(%s) m=%p@%zu", 800 hwq, hwq->hwq_ifp, hwq->hwq_ifp->if_xname, m, depth); 801 if (m) 802 aprint_debug(" swfq[%d]=%#x\n", m->m_len, 803 hwq->hwq_producer->hwq_base[m->m_len].d_bufaddr); 804 aprint_debug("\n"); 805 KASSERT(m != NULL); 806 807 { 808 struct mbuf *m0; 809 for (m0 = hwq->hwq_producer->hwq_ifq.ifq_head; m0 != NULL; m0 = m0->m_nextpkt) 810 KASSERT(m0 != m); 811 } 812 813 KASSERT(hwq->hwq_producer->hwq_base[m->m_len].d_bufaddr == d->d_bufaddr); 814 hwq->hwq_producer->hwq_base[m->m_len].d_bufaddr = htole32(0xdead0000 | m->m_len); 815 816 m->m_len = buflen; 817 if (d->d_desc3 & DESC3_SOF) { 818 KASSERT(hwq->hwq_rxmbuf == NULL); 819 m->m_pkthdr.len = buflen; 820 buflen += 2; /* account for the pad */ 821 /* only modify m->m_data after we know mbuf is good. */ 822 } else { 823 KASSERT(hwq->hwq_rxmbuf != NULL); 824 hwq->hwq_rxmbuf->m_pkthdr.len += buflen; 825 } 826 827 map = M_GETCTX(m, bus_dmamap_t); 828 829 /* 830 * Sync the buffer contents, unload the dmamap, and save it away. 831 */ 832 bus_dmamap_sync(hqm->hqm_dmat, map, 0, buflen, BUS_DMASYNC_POSTREAD); 833 bus_dmamap_unload(hqm->hqm_dmat, map); 834 M_SETCTX(m, NULL); 835 gmac_mapcache_put(hqm->hqm_mc, map); 836 837 /* 838 * Now we build our new packet chain by tacking this on the end. 839 */ 840 *hwq->hwq_mp = m; 841 if ((d->d_desc3 & DESC3_EOF) == 0) { 842 /* 843 * Not last frame, so make sure the next gets appended right. 844 */ 845 hwq->hwq_mp = &m->m_next; 846 return true; 847 } 848 849 #if 0 850 /* 851 * We have a complete frame, let's try to deliver it. 852 */ 853 m->m_len -= ETHER_CRC_LEN; /* remove the CRC from the end */ 854 #endif 855 856 /* 857 * Now get the whole chain. 858 */ 859 m = hwq->hwq_rxmbuf; 860 m_set_rcvif(m, ifp); /* set receive interface */ 861 switch (DESC0_RXSTS_GET(d->d_desc0)) { 862 case DESC0_RXSTS_GOOD: 863 case DESC0_RXSTS_LONG: 864 m->m_data += 2; 865 if_percpuq_enqueue(ifp->if_percpuq, m); 866 break; 867 default: 868 if_statinc(ifp, if_ierrors); 869 m_freem(m); 870 break; 871 } 872 hwq->hwq_rxmbuf = NULL; 873 hwq->hwq_mp = &hwq->hwq_rxmbuf; 874 875 return true; 876 } 877 878 size_t 879 gmac_hwqueue_consume(gmac_hwqueue_t *hwq, size_t free_min) 880 { 881 gmac_hwqmem_t * const hqm = hwq->hwq_hqm; 882 gmac_desc_t d; 883 uint32_t v; 884 uint16_t rptr; 885 size_t i; 886 887 KASSERT((hqm->hqm_flags & HQM_PRODUCER) == 0); 888 889 aprint_debug("gmac_hwqueue_consume(%p): entry\n", hwq); 890 891 892 v = bus_space_read_4(hwq->hwq_iot, hwq->hwq_qrwptr_ioh, 0); 893 rptr = (v >> 0) & 0xffff; 894 hwq->hwq_wptr = (v >> 16) & 0xffff; 895 KASSERT(rptr == hwq->hwq_rptr); 896 if (rptr == hwq->hwq_wptr) 897 return 0; 898 899 i = 0; 900 for (; rptr != hwq->hwq_wptr; rptr = (rptr + 1) & (hwq->hwq_size - 1)) { 901 bus_dmamap_sync(hqm->hqm_dmat, hqm->hqm_dmamap, 902 sizeof(gmac_desc_t [hwq->hwq_qoff + rptr]), 903 sizeof(gmac_desc_t), 904 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 905 d.d_desc0 = le32toh(hwq->hwq_base[rptr].d_desc0); 906 d.d_desc1 = le32toh(hwq->hwq_base[rptr].d_desc1); 907 d.d_bufaddr = le32toh(hwq->hwq_base[rptr].d_bufaddr); 908 d.d_desc3 = le32toh(hwq->hwq_base[rptr].d_desc3); 909 hwq->hwq_base[rptr].d_desc0 = 0; 910 hwq->hwq_base[rptr].d_desc1 = 0; 911 hwq->hwq_base[rptr].d_bufaddr = 0xdeadbeef; 912 hwq->hwq_base[rptr].d_desc3 = 0; 913 bus_dmamap_sync(hqm->hqm_dmat, hqm->hqm_dmamap, 914 sizeof(gmac_desc_t [hwq->hwq_qoff + rptr]), 915 sizeof(gmac_desc_t), 916 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 917 918 aprint_debug("gmac_hwqueue_consume(%p): rptr=%u\n", 919 hwq, rptr); 920 if (!gmac_hwqueue_rxconsume(hwq, &d)) { 921 rptr = (rptr + 1) & (hwq->hwq_size - 1); 922 i += gmac_rxproduce(hwq->hwq_producer, free_min); 923 break; 924 } 925 } 926 927 /* 928 * Update hardware's copy of rptr. (wptr is RO). 929 */ 930 aprint_debug("gmac_hwqueue_consume(%p): rptr old=%u new=%u wptr=%u\n", 931 hwq, hwq->hwq_rptr, rptr, hwq->hwq_wptr); 932 bus_space_write_4(hwq->hwq_iot, hwq->hwq_qrwptr_ioh, 0, rptr); 933 hwq->hwq_rptr = rptr; 934 935 aprint_debug("gmac_hwqueue_consume(%p): exit\n", hwq); 936 937 return i; 938 } 939 940 void 941 gmac_hwqmem_destroy(gmac_hwqmem_t *hqm) 942 { 943 if (hqm->hqm_nsegs) { 944 if (hqm->hqm_base) { 945 if (hqm->hqm_dmamap) { 946 if (hqm->hqm_dmamap->dm_mapsize) { 947 bus_dmamap_unload(hqm->hqm_dmat, 948 hqm->hqm_dmamap); 949 } 950 bus_dmamap_destroy(hqm->hqm_dmat, 951 hqm->hqm_dmamap); 952 } 953 bus_dmamem_unmap(hqm->hqm_dmat, hqm->hqm_base, 954 hqm->hqm_memsize); 955 } 956 bus_dmamem_free(hqm->hqm_dmat, hqm->hqm_segs, hqm->hqm_nsegs); 957 } 958 959 kmem_free(hqm, sizeof(*hqm)); 960 } 961 962 gmac_hwqmem_t * 963 gmac_hwqmem_create(gmac_mapcache_t *mc, size_t ndesc, size_t nqueue, int flags) 964 { 965 gmac_hwqmem_t *hqm; 966 int error; 967 968 KASSERT(ndesc > 0 && ndesc <= 2048); 969 KASSERT((ndesc & (ndesc - 1)) == 0); 970 971 hqm = kmem_zalloc(sizeof(*hqm), KM_SLEEP); 972 hqm->hqm_memsize = nqueue * sizeof(gmac_desc_t [ndesc]); 973 hqm->hqm_mc = mc; 974 hqm->hqm_dmat = mc->mc_dmat; 975 hqm->hqm_ndesc = ndesc; 976 hqm->hqm_nqueue = nqueue; 977 hqm->hqm_flags = flags; 978 979 error = bus_dmamem_alloc(hqm->hqm_dmat, hqm->hqm_memsize, 0, 0, 980 hqm->hqm_segs, 1, &hqm->hqm_nsegs, BUS_DMA_WAITOK); 981 if (error) { 982 KASSERT(error == 0); 983 goto failed; 984 } 985 KASSERT(hqm->hqm_nsegs == 1); 986 error = bus_dmamem_map(hqm->hqm_dmat, hqm->hqm_segs, hqm->hqm_nsegs, 987 hqm->hqm_memsize, (void **)&hqm->hqm_base, BUS_DMA_WAITOK); 988 if (error) { 989 KASSERT(error == 0); 990 goto failed; 991 } 992 error = bus_dmamap_create(hqm->hqm_dmat, hqm->hqm_memsize, 993 hqm->hqm_nsegs, hqm->hqm_memsize, 0, 994 BUS_DMA_WAITOK|BUS_DMA_ALLOCNOW, &hqm->hqm_dmamap); 995 if (error) { 996 KASSERT(error == 0); 997 goto failed; 998 } 999 error = bus_dmamap_load(hqm->hqm_dmat, hqm->hqm_dmamap, hqm->hqm_base, 1000 hqm->hqm_memsize, NULL, 1001 BUS_DMA_WAITOK|BUS_DMA_WRITE|BUS_DMA_READ|BUS_DMA_COHERENT); 1002 if (error) { 1003 aprint_debug("gmac_hwqmem_create: ds_addr=%zu ds_len=%zu\n", 1004 hqm->hqm_segs->ds_addr, hqm->hqm_segs->ds_len); 1005 aprint_debug("gmac_hwqmem_create: bus_dmamap_load: %d\n", error); 1006 KASSERT(error == 0); 1007 goto failed; 1008 } 1009 1010 memset(hqm->hqm_base, 0, hqm->hqm_memsize); 1011 if ((flags & HQM_PRODUCER) == 0) 1012 bus_dmamap_sync(hqm->hqm_dmat, hqm->hqm_dmamap, 0, 1013 hqm->hqm_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1014 1015 return hqm; 1016 1017 failed: 1018 gmac_hwqmem_destroy(hqm); 1019 return NULL; 1020 } 1021 1022 void 1023 gmac_hwqueue_destroy(gmac_hwqueue_t *hwq) 1024 { 1025 gmac_hwqmem_t * const hqm = hwq->hwq_hqm; 1026 KASSERT(hqm->hqm_refs & hwq->hwq_ref); 1027 hqm->hqm_refs &= ~hwq->hwq_ref; 1028 for (;;) { 1029 struct mbuf *m; 1030 bus_dmamap_t map; 1031 IF_DEQUEUE(&hwq->hwq_ifq, m); 1032 if (m == NULL) 1033 break; 1034 map = M_GETCTX(m, bus_dmamap_t); 1035 bus_dmamap_unload(hqm->hqm_dmat, map); 1036 gmac_mapcache_put(hqm->hqm_mc, map); 1037 m_freem(m); 1038 } 1039 kmem_free(hwq, sizeof(*hwq)); 1040 } 1041 1042 gmac_hwqueue_t * 1043 gmac_hwqueue_create(gmac_hwqmem_t *hqm, 1044 bus_space_tag_t iot, bus_space_handle_t ioh, 1045 bus_size_t qrwptr, bus_size_t qbase, 1046 size_t qno) 1047 { 1048 const size_t log2_memsize = ffs(hqm->hqm_ndesc) - 1; 1049 gmac_hwqueue_t *hwq; 1050 uint32_t v; 1051 1052 KASSERT(qno < hqm->hqm_nqueue); 1053 KASSERT((hqm->hqm_refs & (1 << qno)) == 0); 1054 1055 hwq = kmem_zalloc(sizeof(*hwq), KM_SLEEP); 1056 hwq->hwq_size = hqm->hqm_ndesc; 1057 hwq->hwq_iot = iot; 1058 bus_space_subregion(iot, ioh, qrwptr, sizeof(uint32_t), 1059 &hwq->hwq_qrwptr_ioh); 1060 1061 hwq->hwq_hqm = hqm; 1062 hwq->hwq_ref = 1 << qno; 1063 hqm->hqm_refs |= hwq->hwq_ref; 1064 hwq->hwq_qoff = hqm->hqm_ndesc * qno; 1065 hwq->hwq_base = hqm->hqm_base + hwq->hwq_qoff; 1066 1067 if (qno == 0) { 1068 bus_space_write_4(hwq->hwq_iot, ioh, qbase, 1069 hqm->hqm_dmamap->dm_segs[0].ds_addr | (log2_memsize)); 1070 } 1071 1072 v = bus_space_read_4(hwq->hwq_iot, hwq->hwq_qrwptr_ioh, 0); 1073 hwq->hwq_rptr = (v >> 0) & 0xffff; 1074 hwq->hwq_wptr = (v >> 16) & 0xffff; 1075 1076 aprint_debug("gmac_hwqueue_create: %p: qrwptr=%zu(%#zx) wptr=%u rptr=%u" 1077 " base=%p@%#zx(%#x) qno=%zu\n", 1078 hwq, qrwptr, hwq->hwq_qrwptr_ioh, hwq->hwq_wptr, hwq->hwq_rptr, 1079 hwq->hwq_base, 1080 hqm->hqm_segs->ds_addr + sizeof(gmac_desc_t [hwq->hwq_qoff]), 1081 bus_space_read_4(hwq->hwq_iot, ioh, qbase), qno); 1082 1083 hwq->hwq_free = hwq->hwq_size - 1; 1084 hwq->hwq_ifq.ifq_maxlen = hwq->hwq_free; 1085 hwq->hwq_mp = &hwq->hwq_rxmbuf; 1086 1087 return hwq; 1088 } 1089
Indexes created Thu Sep 25 16:09:42 GMT 2025