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      1 /* $Id: imx23_rtcreg.h,v 1.2 2015/01/10 12:16:28 jmcneill Exp $ */
      2 
      3 /*
      4  * Copyright (c) 2012 The NetBSD Foundation, Inc.
      5  * All rights reserved.
      6  *
      7  * This code is derived from software contributed to The NetBSD Foundation
      8  * by Petri Laakso.
      9  *
     10  * Redistribution and use in source and binary forms, with or without
     11  * modification, are permitted provided that the following conditions
     12  * are met:
     13  * 1. Redistributions of source code must retain the above copyright
     14  *    notice, this list of conditions and the following disclaimer.
     15  * 2. Redistributions in binary form must reproduce the above copyright
     16  *    notice, this list of conditions and the following disclaimer in the
     17  *    documentation and/or other materials provided with the distribution.
     18  *
     19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     29  * POSSIBILITY OF SUCH DAMAGE.
     30  */
     31 
     32 #ifndef _ARM_IMX_IMX23_RTCREG_H_
     33 #define _ARM_IMX_IMX23_RTCREG_H_
     34 
     35 #include <sys/cdefs.h>
     36 
     37 #define HW_RTC_BASE 0x8005C000
     38 #define HW_RTC_BASE_SIZE 0x2000
     39 
     40 /*
     41  * Real-Time Clock Control Register.
     42  */
     43 #define HW_RTC_CTRL	0x000
     44 #define HW_RTC_CTRL_SET	0x004
     45 #define HW_RTC_CTRL_CLR	0x008
     46 #define HW_RTC_CTRL_TOG	0x00C
     47 
     48 #define HW_RTC_CTRL_SFTRST			__BIT(31)
     49 #define HW_RTC_CTRL_CLKGATE			__BIT(30)
     50 #define HW_RTC_CTRL_RSVD0			__BITS(29, 7)
     51 #define HW_RTC_CTRL_SUPPRESS_COPY2ANALOG	__BIT(6)
     52 #define HW_RTC_CTRL_FORCE_UPDATE		__BIT(5)
     53 #define HW_RTC_CTRL_WATCHDOGEN			__BIT(4)
     54 #define HW_RTC_CTRL_ONEMSEC_IRQ			__BIT(3)
     55 #define HW_RTC_CTRL_ALARM_IRQ			__BIT(2)
     56 #define HW_RTC_CTRL_ONEMSEC_IRQ_EN		__BIT(1)
     57 #define HW_RTC_CTRL_ALARM_IRQ_EN		__BIT(0)
     58 
     59 /*
     60  * Real-Time Clock Status Register.
     61  */
     62 #define HW_RTC_STAT	0x010
     63 #define HW_RTC_STAT_SET	0x014
     64 #define HW_RTC_STAT_CLR	0x018
     65 #define HW_RTC_STAT_TOG	0x01C
     66 
     67 #define HW_RTC_STAT_RTC_PRESENT		__BIT(31)
     68 #define HW_RTC_STAT_ALARM_PRESENT	__BIT(30)
     69 #define HW_RTC_STAT_WATCHDOG_PRESENT	__BIT(29)
     70 #define HW_RTC_STAT_XTAL32000_PRESENT	__BIT(28)
     71 #define HW_RTC_STAT_XTAL32768_PRESENT	__BIT(27)
     72 #define HW_RTC_STAT_RSVD1		__BITS(26, 24)
     73 #define HW_RTC_STAT_STALE_REGS		__BIT(23, 16)
     74 #define HW_RTC_STAT_NEW_REGS		__BIT(15, 8)
     75 #define HW_RTC_STAT_RSVD0		__BIT(7, 0)
     76 
     77 /*
     78  * Real-Time Clock Milliseconds Counter.
     79  */
     80 #define HW_RTC_MILLISECONDS	0x020
     81 #define HW_RTC_MILLISECONDS_SET	0x024
     82 #define HW_RTC_MILLISECONDS_CLR	0x028
     83 #define HW_RTC_MILLISECONDS_TOG	0x02C
     84 
     85 #define HW_RTC_MILLISECONDS_COUNT	__BITS(31, 0)
     86 
     87 /*
     88  * Real-Time Clock Seconds Counter.
     89  */
     90 #define HW_RTC_SECONDS		0x030
     91 #define HW_RTC_SECONDS_SET	0x034
     92 #define HW_RTC_SECONDS_CLR	0x038
     93 #define HW_RTC_SECONDS_TOG	0x03C
     94 
     95 #define HW_RTC_SECONDS_COUNT	__BITS(31, 0)
     96 
     97 /*
     98  * Real-Time Clock Alarm Register.
     99  */
    100 #define HW_RTC_ALARM		0x040
    101 #define HW_RTC_ALARM_SET	0x044
    102 #define HW_RTC_ALARM_CLR	0x048
    103 #define HW_RTC_ALARM_TOG	0x04C
    104 
    105 #define HW_RTC_ALARM_VALUE	__BITS(31, 0)
    106 
    107 /*
    108  * Watchdog Timer Register.
    109  */
    110 #define HW_RTC_WATCHDOG		0x050
    111 #define HW_RTC_WATCHDOG_SET	0x054
    112 #define HW_RTC_WATCHDOG_CLR	0x058
    113 #define HW_RTC_WATCHDOG_TOG	0x05C
    114 
    115 #define HW_RTC_WATCHDOG_COUNT	__BITS(31, 0)
    116 
    117 /*
    118  * Persistent State Register 0.
    119  */
    120 #define HW_RTC_PERSISTENT0	0x060
    121 #define HW_RTC_PERSISTENT0_SET	0x064
    122 #define HW_RTC_PERSISTENT0_CLR	0x068
    123 #define HW_RTC_PERSISTENT0_TOG	0x06C
    124 
    125 #define HW_RTC_PERSISTENT0_SPARE_ANALOG		__BITS(31, 18)
    126 #define HW_RTC_PERSISTENT0_AUTO_RESTART		__BIT(17)
    127 #define HW_RTC_PERSISTENT0_DISABLE_PSWITCH	__BIT(16)
    128 #define HW_RTC_PERSISTENT0_LOWERBIAS		__BITS(15, 14)
    129 #define HW_RTC_PERSISTENT0_DISABLE_XTALOK	__BIT(13)
    130 #define HW_RTC_PERSISTENT0_MSEC_RES		__BITS(12, 8)
    131 #define HW_RTC_PERSISTENT0_ALARM_WAKE		__BIT(7)
    132 #define HW_RTC_PERSISTENT0_XTAL32_FREQ		__BIT(6)
    133 #define HW_RTC_PERSISTENT0_XTAL32KHZ_PWRUP	__BIT(5)
    134 #define HW_RTC_PERSISTENT0_XTAL24MHZ_PWRUP	__BIT(4)
    135 #define HW_RTC_PERSISTENT0_LCK_SECS		__BIT(3)
    136 #define HW_RTC_PERSISTENT0_ALARM_EN		__BIT(2)
    137 #define HW_RTC_PERSISTENT0_ALARM_WAKE_EN	__BIT(1)
    138 #define HW_RTC_PERSISTENT0_CLOCKSOURCE		__BIT(0)
    139 
    140 /*
    141  * Persistent State Register 1.
    142  */
    143 #define HW_RTC_PERSISTENT1	0x070
    144 #define HW_RTC_PERSISTENT1_SET	0x074
    145 #define HW_RTC_PERSISTENT1_CLR	0x078
    146 #define HW_RTC_PERSISTENT1_TOG	0x07C
    147 
    148 #define HW_RTC_PERSISTENT1_GENERAL	__BITS(31, 0)
    149 
    150 /*
    151  * Persistent State Register 2.
    152  */
    153 #define HW_RTC_PERSISTENT2	0x080
    154 #define HW_RTC_PERSISTENT2_SET	0x084
    155 #define HW_RTC_PERSISTENT2_CLR	0x088
    156 #define HW_RTC_PERSISTENT2_TOG	0x08C
    157 
    158 #define HW_RTC_PERSISTENT2_GENERAL	__BITS(31, 0)
    159 
    160 /*
    161  * Persistent State Register 3.
    162  */
    163 #define HW_RTC_PERSISTENT3	0x090
    164 #define HW_RTC_PERSISTENT3_SET	0x094
    165 #define HW_RTC_PERSISTENT3_CLR	0x098
    166 #define HW_RTC_PERSISTENT3_TOG	0x09C
    167 
    168 #define HW_RTC_PERSISTENT3_GENERAL	__BITS(31, 0)
    169 
    170 /*
    171  * Persistent State Register 4.
    172  */
    173 #define HW_RTC_PERSISTENT4	0x0A0
    174 #define HW_RTC_PERSISTENT4_SET	0x0A4
    175 #define HW_RTC_PERSISTENT4_CLR	0x0A8
    176 #define HW_RTC_PERSISTENT4_TOG	0x0AC
    177 
    178 #define HW_RTC_PERSISTENT4_GENERAL	__BITS(31, 0)
    179 
    180 /*
    181  * Persistent State Register 5.
    182  */
    183 #define HW_RTC_PERSISTENT5	0x0B0
    184 #define HW_RTC_PERSISTENT5_SET	0x0B4
    185 #define HW_RTC_PERSISTENT5_CLR	0x0B8
    186 #define HW_RTC_PERSISTENT5_TOG	0x0BC
    187 
    188 #define HW_RTC_PERSISTENT5_GENERAL	__BITS(31, 0)
    189 
    190 /*
    191  * Real-Time Clock Debug Register.
    192  */
    193 #define HW_RTC_DEBUG		0x0C0
    194 #define HW_RTC_DEBUG_SET	0x0C4
    195 #define HW_RTC_DEBUG_CLR	0x0C8
    196 #define HW_RTC_DEBUG_TOG	0x0CC
    197 
    198 #define HW_RTC_DEBUG_RSVD0			__BITS(31, 2)
    199 #define HW_RTC_DEBUG_WATCHDOG_RESET_MASK	__BIT(1)
    200 #define HW_RTC_DEBUG_WATCHDOG_RESET		__BIT(0)
    201 
    202 /*
    203  * Real-Time Clock Version Register.
    204  */
    205 #define HW_RTC_VERSION	0x0D0
    206 
    207 #define HW_RTC_VERSION_MAJOR	__BITS(31, 24)
    208 #define HW_RTC_VERSION_MINOR	__BITS(23, 16)
    209 #define HW_RTC_VERSION_STEP	__BITS(15, 9)
    210 
    211 #endif /* !_ARM_IMX_IMX23_RTCREG_H_ */
    212