imx23_usbphy.c revision 1.1.10.2
1 1.1.10.2 tls /* $Id: imx23_usbphy.c,v 1.1.10.2 2014/08/20 00:02:46 tls Exp $ */ 2 1.1.10.2 tls 3 1.1.10.2 tls /* 4 1.1.10.2 tls * Copyright (c) 2013 The NetBSD Foundation, Inc. 5 1.1.10.2 tls * All rights reserved. 6 1.1.10.2 tls * 7 1.1.10.2 tls * This code is derived from software contributed to The NetBSD Foundation 8 1.1.10.2 tls * by Petri Laakso. 9 1.1.10.2 tls * 10 1.1.10.2 tls * Redistribution and use in source and binary forms, with or without 11 1.1.10.2 tls * modification, are permitted provided that the following conditions 12 1.1.10.2 tls * are met: 13 1.1.10.2 tls * 1. Redistributions of source code must retain the above copyright 14 1.1.10.2 tls * notice, this list of conditions and the following disclaimer. 15 1.1.10.2 tls * 2. Redistributions in binary form must reproduce the above copyright 16 1.1.10.2 tls * notice, this list of conditions and the following disclaimer in the 17 1.1.10.2 tls * documentation and/or other materials provided with the distribution. 18 1.1.10.2 tls * 19 1.1.10.2 tls * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 1.1.10.2 tls * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 1.1.10.2 tls * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 1.1.10.2 tls * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 1.1.10.2 tls * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 1.1.10.2 tls * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 1.1.10.2 tls * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 1.1.10.2 tls * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 1.1.10.2 tls * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 1.1.10.2 tls * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 1.1.10.2 tls * POSSIBILITY OF SUCH DAMAGE. 30 1.1.10.2 tls */ 31 1.1.10.2 tls 32 1.1.10.2 tls #include <sys/param.h> 33 1.1.10.2 tls #include <sys/types.h> 34 1.1.10.2 tls #include <sys/bus.h> 35 1.1.10.2 tls #include <sys/cdefs.h> 36 1.1.10.2 tls #include <sys/device.h> 37 1.1.10.2 tls #include <sys/errno.h> 38 1.1.10.2 tls 39 1.1.10.2 tls #include <arm/imx/imx23_usbphyreg.h> 40 1.1.10.2 tls #include <arm/imx/imx23var.h> 41 1.1.10.2 tls 42 1.1.10.2 tls typedef struct usbphy_softc { 43 1.1.10.2 tls device_t sc_dev; 44 1.1.10.2 tls bus_space_tag_t sc_iot; 45 1.1.10.2 tls bus_space_handle_t sc_hdl; 46 1.1.10.2 tls } *usbphy_softc_t; 47 1.1.10.2 tls 48 1.1.10.2 tls static int usbphy_match(device_t, cfdata_t, void *); 49 1.1.10.2 tls static void usbphy_attach(device_t, device_t, void *); 50 1.1.10.2 tls static int usbphy_activate(device_t, enum devact); 51 1.1.10.2 tls 52 1.1.10.2 tls static void usbphy_reset(struct usbphy_softc *); 53 1.1.10.2 tls static void usbphy_init(struct usbphy_softc *); 54 1.1.10.2 tls 55 1.1.10.2 tls CFATTACH_DECL3_NEW(usbphy, 56 1.1.10.2 tls sizeof(struct usbphy_softc), 57 1.1.10.2 tls usbphy_match, 58 1.1.10.2 tls usbphy_attach, 59 1.1.10.2 tls NULL, 60 1.1.10.2 tls usbphy_activate, 61 1.1.10.2 tls NULL, 62 1.1.10.2 tls NULL, 63 1.1.10.2 tls 0 64 1.1.10.2 tls ); 65 1.1.10.2 tls 66 1.1.10.2 tls #define PHY_RD(sc, reg) \ 67 1.1.10.2 tls bus_space_read_4(sc->sc_iot, sc->sc_hdl, (reg)) 68 1.1.10.2 tls #define PHY_WR(sc, reg, val) \ 69 1.1.10.2 tls bus_space_write_4(sc->sc_iot, sc->sc_hdl, (reg), (val)) 70 1.1.10.2 tls 71 1.1.10.2 tls #define USBPHY_SOFT_RST_LOOP 455 /* At least 1 us ... */ 72 1.1.10.2 tls 73 1.1.10.2 tls static int 74 1.1.10.2 tls usbphy_match(device_t parent, cfdata_t match, void *aux) 75 1.1.10.2 tls { 76 1.1.10.2 tls struct apb_attach_args *aa = aux; 77 1.1.10.2 tls 78 1.1.10.2 tls if ((aa->aa_addr == HW_USBPHY_BASE) && (aa->aa_size == HW_USBPHY_SIZE)) 79 1.1.10.2 tls return 1; 80 1.1.10.2 tls 81 1.1.10.2 tls return 0; 82 1.1.10.2 tls } 83 1.1.10.2 tls 84 1.1.10.2 tls static void 85 1.1.10.2 tls usbphy_attach(device_t parent, device_t self, void *aux) 86 1.1.10.2 tls { 87 1.1.10.2 tls struct usbphy_softc *sc = device_private(self); 88 1.1.10.2 tls struct apb_attach_args *aa = aux; 89 1.1.10.2 tls static int usbphy_attached = 0; 90 1.1.10.2 tls uint32_t phy_version; 91 1.1.10.2 tls 92 1.1.10.2 tls sc->sc_dev = self; 93 1.1.10.2 tls sc->sc_iot = aa->aa_iot; 94 1.1.10.2 tls 95 1.1.10.2 tls if (usbphy_attached) { 96 1.1.10.2 tls aprint_error_dev(sc->sc_dev, "already attached\n"); 97 1.1.10.2 tls return; 98 1.1.10.2 tls } 99 1.1.10.2 tls 100 1.1.10.2 tls if (bus_space_map(sc->sc_iot, aa->aa_addr, aa->aa_size, 0, 101 1.1.10.2 tls &sc->sc_hdl)) 102 1.1.10.2 tls { 103 1.1.10.2 tls aprint_error_dev(sc->sc_dev, "Unable to map bus space\n"); 104 1.1.10.2 tls return; 105 1.1.10.2 tls } 106 1.1.10.2 tls 107 1.1.10.2 tls usbphy_reset(sc); 108 1.1.10.2 tls usbphy_init(sc); 109 1.1.10.2 tls 110 1.1.10.2 tls phy_version = PHY_RD(sc, HW_USBPHY_VERSION); 111 1.1.10.2 tls aprint_normal(": USB PHY v%" __PRIuBIT ".%" __PRIuBIT "\n", 112 1.1.10.2 tls __SHIFTOUT(phy_version, HW_USBPHY_VERSION_MAJOR), 113 1.1.10.2 tls __SHIFTOUT(phy_version, HW_USBPHY_VERSION_MINOR)); 114 1.1.10.2 tls 115 1.1.10.2 tls usbphy_attached = 1; 116 1.1.10.2 tls 117 1.1.10.2 tls return; 118 1.1.10.2 tls } 119 1.1.10.2 tls 120 1.1.10.2 tls static int 121 1.1.10.2 tls usbphy_activate(device_t self, enum devact act) 122 1.1.10.2 tls { 123 1.1.10.2 tls 124 1.1.10.2 tls return EOPNOTSUPP; 125 1.1.10.2 tls } 126 1.1.10.2 tls 127 1.1.10.2 tls /* 128 1.1.10.2 tls * Reset the USB PHY. 129 1.1.10.2 tls * 130 1.1.10.2 tls * Inspired by i.MX23 RM "39.3.10 Correct Way to Soft Reset a Block" 131 1.1.10.2 tls */ 132 1.1.10.2 tls static void 133 1.1.10.2 tls usbphy_reset(struct usbphy_softc *sc) 134 1.1.10.2 tls { 135 1.1.10.2 tls unsigned int loop; 136 1.1.10.2 tls 137 1.1.10.2 tls /* Prepare for soft-reset by making sure that SFTRST is not currently 138 1.1.10.2 tls * asserted. Also clear CLKGATE so we can wait for its assertion below. 139 1.1.10.2 tls */ 140 1.1.10.2 tls PHY_WR(sc, HW_USBPHY_CTRL_CLR, HW_USBPHY_CTRL_SFTRST); 141 1.1.10.2 tls 142 1.1.10.2 tls /* Wait at least a microsecond for SFTRST to deassert. */ 143 1.1.10.2 tls loop = 0; 144 1.1.10.2 tls while ((PHY_RD(sc, HW_USBPHY_CTRL) & HW_USBPHY_CTRL_SFTRST) || 145 1.1.10.2 tls (loop < USBPHY_SOFT_RST_LOOP)) 146 1.1.10.2 tls loop++; 147 1.1.10.2 tls 148 1.1.10.2 tls /* Clear CLKGATE so we can wait for its assertion below. */ 149 1.1.10.2 tls PHY_WR(sc, HW_USBPHY_CTRL_CLR, HW_USBPHY_CTRL_CLKGATE); 150 1.1.10.2 tls 151 1.1.10.2 tls /* Soft-reset the block. */ 152 1.1.10.2 tls PHY_WR(sc, HW_USBPHY_CTRL_SET, HW_USBPHY_CTRL_SFTRST); 153 1.1.10.2 tls 154 1.1.10.2 tls /* Wait until clock is in the gated state. */ 155 1.1.10.2 tls while (!(PHY_RD(sc, HW_USBPHY_CTRL) & HW_USBPHY_CTRL_CLKGATE)); 156 1.1.10.2 tls 157 1.1.10.2 tls /* Bring block out of reset. */ 158 1.1.10.2 tls PHY_WR(sc, HW_USBPHY_CTRL_CLR, HW_USBPHY_CTRL_SFTRST); 159 1.1.10.2 tls 160 1.1.10.2 tls loop = 0; 161 1.1.10.2 tls while ((PHY_RD(sc, HW_USBPHY_CTRL) & HW_USBPHY_CTRL_SFTRST) || 162 1.1.10.2 tls (loop < USBPHY_SOFT_RST_LOOP)) 163 1.1.10.2 tls loop++; 164 1.1.10.2 tls 165 1.1.10.2 tls PHY_WR(sc, HW_USBPHY_CTRL_CLR, HW_USBPHY_CTRL_CLKGATE); 166 1.1.10.2 tls 167 1.1.10.2 tls /* Wait until clock is in the NON-gated state. */ 168 1.1.10.2 tls while (PHY_RD(sc, HW_USBPHY_CTRL) & HW_USBPHY_CTRL_CLKGATE); 169 1.1.10.2 tls 170 1.1.10.2 tls return; 171 1.1.10.2 tls } 172 1.1.10.2 tls 173 1.1.10.2 tls /* 174 1.1.10.2 tls * Enable USB PHY. 175 1.1.10.2 tls */ 176 1.1.10.2 tls static void 177 1.1.10.2 tls usbphy_init(struct usbphy_softc *sc) 178 1.1.10.2 tls { 179 1.1.10.2 tls /* Disable power down bits. */ 180 1.1.10.2 tls PHY_WR(sc, HW_USBPHY_PWD_CLR, 181 1.1.10.2 tls HW_USBPHY_PWD_RXPWDRX | 182 1.1.10.2 tls HW_USBPHY_PWD_RXPWDDIFF | 183 1.1.10.2 tls HW_USBPHY_PWD_RXPWD1PT1 | 184 1.1.10.2 tls HW_USBPHY_PWD_RXPWDENV | 185 1.1.10.2 tls HW_USBPHY_PWD_TXPWDV2I | 186 1.1.10.2 tls HW_USBPHY_PWD_TXPWDIBIAS | 187 1.1.10.2 tls HW_USBPHY_PWD_TXPWDFS 188 1.1.10.2 tls ); 189 1.1.10.2 tls 190 1.1.10.2 tls /* USB PLL Power on. */ 191 1.1.10.2 tls PHY_WR(sc, HW_USBPHY_IP_SET, 192 1.1.10.2 tls HW_USBPHY_IP_PLL_POWER); 193 1.1.10.2 tls 194 1.1.10.2 tls /* Wait PLL to lock to 480MHz. */ 195 1.1.10.2 tls delay(10); 196 1.1.10.2 tls 197 1.1.10.2 tls PHY_WR(sc, HW_USBPHY_IP_SET, HW_USBPHY_IP_PLL_LOCKED); 198 1.1.10.2 tls 199 1.1.10.2 tls /* Ungate PLL clock to USB PHY. */ 200 1.1.10.2 tls PHY_WR(sc, HW_USBPHY_IP_SET, HW_USBPHY_IP_EN_USB_CLKS); 201 1.1.10.2 tls 202 1.1.10.2 tls return; 203 1.1.10.2 tls } 204
Indexes created Tue Sep 30 20:09:53 GMT 2025