Home | History | Annotate | Line # | Download | only in imx 
      1 /* $NetBSD: imx31reg.h,v 1.5 2010/11/15 18:19:19 bsh Exp $ */
      2 /*-
      3  * Copyright (c) 2007 The NetBSD Foundation, Inc.
      4  * All rights reserved.
      5  *
      6  * This code is derived from software contributed to The NetBSD Foundation
      7  * by Matt Thomas.
      8  *
      9  * Redistribution and use in source and binary forms, with or without
     10  * modification, are permitted provided that the following conditions
     11  * are met:
     12  * 1. Redistributions of source code must retain the above copyright
     13  *    notice, this list of conditions and the following disclaimer.
     14  * 2. Redistributions in binary form must reproduce the above copyright
     15  *    notice, this list of conditions and the following disclaimer in the
     16  *    documentation and/or other materials provided with the distribution.
     17  *
     18  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     19  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     20  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     21  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     22  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     23  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     24  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     25  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     26  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     27  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     28  * POSSIBILITY OF SUCH DAMAGE.
     29  */
     30 
     31 #ifndef _ARM_IMX_IMX31REG_H_
     32 #define _ARM_IMX_IMX31REG_H_
     33 
     34 #define	I2C1_BASE	0x43f80000
     35 #define	I2C2_BASE	0x43f90000
     36 #define	I2C3_BASE	0x43f84000
     37 
     38 #define	I2C_IADR	0x0000	/* I2C Address */
     39 #define	I2C_IFDR	0x0004	/* I2C Frequency Divider */
     40 #define	I2C_I2CR	0x0008	/* I2C Control */
     41 #define	I2C_I2SR	0x000c	/* I2C Status */
     42 #define	I2C_I2DR	0x0010	/* I2C Data I/O */
     43 
     44 #define	ATA_BASE	0x43f8c000
     45 #define	ATA_DMA_BASE	0x50020000
     46 
     47 #define	UART1_BASE	0x43f90000
     48 #define	UART2_BASE	0x43f94000
     49 #define	UART3_BASE	0x5000c000
     50 #define	UART4_BASE	0x43fb0000
     51 #define	UART5_BASE	0x43fb4000
     52 
     53 #define	CSPI1_BASE	0x43fa4000
     54 #define	CSPI2_BASE	0x50010000
     55 
     56 #define	GPIO1_BASE	0x53fcc000
     57 #define	GPIO2_BASE	0x53fd0000
     58 #define	GPIO3_BASE	0x53fa4000
     59 /* register definitions in imxgpiore.h */
     60 
     61 #define	GPIO_NPINS		32
     62 #define	GPIO_NGROUPS		3
     63 
     64 #define	GPIO_NO_SCLK0		GPIO_NO(3, 2)
     65 
     66 
     67 /* EPIT */
     68 
     69 #define	EPIT1_BASE	0x53f94000
     70 #define	EPIT2_BASE	0x53f98000
     71 
     72 
     73 #define	INTC_BASE		0x68000000
     74 #define	INTC_SIZE		0x0400
     75 #define	IMX31_INTCNTL		0x0000	/* Interrupt Control (RW) */
     76 #define	IMX31_NIMASK		0x0004	/* Normal Interrupt Mask (RW) */
     77 #define	IMX31_INTENNUM		0x0008	/* Interrupt Enable Number (RW) */
     78 #define	IMX31_INTDISNUM		0x000c	/* Interrupt Disable Number (RW) */
     79 #define	IMX31_INTENABLEH	0x0010	/* Interrupt Enable High (RW) */
     80 #define	IMX31_INTENABLEL	0x0014	/* Interrupt Enable Low (RW) */
     81 #define	IMX31_INTTYPEH		0x0018	/* Interrupt Type High (RW) */
     82 #define	IMX31_INTTYPEL		0x001c	/* Interrupt Type Low (RW) */
     83 #define	IMX31_NIPRIORITY7	0x0020	/* Normal Intr Priority Level 7 (RW) */
     84 #define	IMX31_NIPRIORITY6	0x0024	/* Normal Intr Priority Level 6 (RW) */
     85 #define	IMX31_NIPRIORITY5	0x0028	/* Normal Intr Priority Level 5 (RW) */
     86 #define	IMX31_NIPRIORITY4	0x002c	/* Normal Intr Priority Level 4 (RW) */
     87 #define	IMX31_NIPRIORITY3	0x0030	/* Normal Intr Priority Level 3 (RW) */
     88 #define	IMX31_NIPRIORITY2	0x0034	/* Normal Intr Priority Level 2 (RW) */
     89 #define	IMX31_NIPRIORITY1	0x0038	/* Normal Intr Priority Level 1 (RW) */
     90 #define	IMX31_NIPRIORITY0	0x003c	/* Normal Intr Priority Level 0 (RW) */
     91 #define	IMX31_NIVECSR		0x0040	/* Normal Interrupt Vector Status (R) */
     92 #define	IMX31_FIVECSR		0x0044	/* Fast Interrupt Vector Status (R) */
     93 #define	IMX31_INTSRCH		0x0048	/* Interrupt Source High (R) */
     94 #define	IMX31_INTSRCL		0x004c	/* Interrupt Source Low (R) */
     95 #define	IMX31_INTFRCH		0x0050	/* Interrupt Force High (RW) */
     96 #define	IMX31_INTFRCL		0x0054	/* Interrupt Force Low (RW) */
     97 #define	IMX31_NIPNDH		0x0058	/* Normal Intr Pending High (R) */
     98 #define	IMX31_NIPNDL		0x005c	/* Normal Intr Pending Low (R) */
     99 #define	IMX31_FIPNDH		0x0060	/* Fast Intr Pending High (R) */
    100 #define	IMX31_FIPNDL		0x0064	/* Fast Intr Pending Low (R) */
    101 
    102 #define	IMX31_VECTOR(n)		(0x0100 + (n) * 4)	/* Vector [N] */
    103 
    104 #define	INTCNTL_ABFLAG	(1 << 25)	/* Core Arb. Priorty Risen (W1C) */
    105 #define	INTCNTL_ABFEN	(1 << 24)	/* ABFLAG Sticky Enable */
    106 #define	INTCNTL_NIDIS	(1 << 22)	/* Normal Intr. Disable */
    107 #define	INTCNTL_FIDIS	(1 << 21)	/* Fast Intr. Disable */
    108 #define	INTCNTL_NIAD	(1 << 20)	/* Normal Intr. Arbiter Rise ARM Lvl */
    109 #define	INTCNTL_FIAD	(1 << 19)	/* Fast Intr. Arbiter Rise ARM Level */
    110 #define	INTCNTL_NM	(1 << 18)	/* Normal Intr. Mode Control (1=AVIC) */
    111 
    112 #define	NIMASK_DIS_NONE		-1
    113 
    114 /*
    115  * INTTYPE (0 = IRQ, 1 = FIQ)
    116  */
    117 
    118 #endif /* _ARM_IMX_IMX31REG_H_ */
    119