Home | History | Annotate | Line # | Download | only in imx 
      1 /*	$NetBSD: imxpwmreg.h,v 1.2 2020/05/20 05:10:42 hkenken Exp $	*/
      2 
      3 /*
      4  * Copyright (c) 2014  Genetec Corporation.  All rights reserved.
      5  * Written by Hashimoto Kenichi for Genetec Corporation.
      6  *
      7  * Redistribution and use in source and binary forms, with or without
      8  * modification, are permitted provided that the following conditions
      9  * are met:
     10  * 1. Redistributions of source code must retain the above copyright
     11  *    notice, this list of conditions and the following disclaimer.
     12  * 2. Redistributions in binary form must reproduce the above copyright
     13  *    notice, this list of conditions and the following disclaimer in the
     14  *    documentation and/or other materials provided with the distribution.
     15  *
     16  * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
     17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     18  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     19  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL GENETEC CORPORATION
     20  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     21  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     22  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     23  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     24  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     25  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     26  * POSSIBILITY OF SUCH DAMAGE.
     27  */
     28 
     29 #ifndef	_ARM_IMX_IMXPWMREG_H_
     30 #define	_ARM_IMX_IMXPWMREG_H_
     31 
     32 #define PWM_CR			0x00	/* PWM Control Register */
     33 #define  PWM_CR_FWM		__BITS(27, 26)
     34 #define  PWM_CR_STOPEN		__BIT(25)
     35 #define  PWM_CR_DOZEN		__BIT(24)
     36 #define  PWM_CR_WAITEN		__BIT(23)
     37 #define  PWM_CR_DBGEN		__BIT(22)
     38 #define  PWM_CR_BCTR		__BIT(21)
     39 #define  PWM_CR_HCTR		__BIT(20)
     40 #define  PWM_CR_POUTC		__BITS(19, 18)
     41 #define  PWM_CR_CLKSRC		__BITS(17, 16)
     42 #define   CLKSRC_IPG_CLK		1
     43 #define   CLKSRC_IPG_CLK_HIGHFREQ	2
     44 #define   CLKSRC_IPG_CLK_32K		3
     45 #define  PWM_CR_PRESCALER	__BITS(15, 4)
     46 #define  PWM_CR_SWR		__BIT(3)
     47 #define  PWM_CR_REPEAT		__BITS(2, 1)
     48 #define  PWM_CR_EN		__BIT(0)
     49 #define PWM_SR			0x04	/* PWM Status Register */
     50 #define  PWM_SR_FWE		__BIT(6)
     51 #define  PWM_SR_CMP		__BIT(5)
     52 #define  PWM_SR_ROV		__BIT(4)
     53 #define  PWM_SR_FE		__BIT(3)
     54 #define  PWM_SR_FIFOAV		__BITS(2, 0)
     55 #define PWM_IR			0x08	/* PWM Interrupt Register */
     56 #define  PWM_IR_CIE		__BIT(2)
     57 #define  PWM_IR_RIE		__BIT(1)
     58 #define  PWM_IR_FIE		__BIT(0)
     59 #define PWM_SAR			0x0C	/* PWM Sample Register */
     60 #define  PWM_SAR_SAMPLE		__BITS(15, 0)
     61 #define PWM_PR			0x10	/* PWM Period Register */
     62 #define  PWM_PR_PERIOD		__BITS(15, 0)
     63 #define PWM_CNR			0x14	/* PWM Counter Register */
     64 #define  PWM_CNR_COUNT		__BITS(15, 0)
     65 
     66 #endif	/* _ARM_IMX_IMXPWMREG_H_ */
     67