1 /* $NetBSD: imxsnvs.c,v 1.3 2025/09/07 21:45:11 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2014 Ryo Shimizu 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 24 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 25 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * i.MX6,7 Secure Non-Volatile Storage 31 */ 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: imxsnvs.c,v 1.3 2025/09/07 21:45:11 thorpej Exp $"); 34 35 #include "locators.h" 36 #include <sys/bus.h> 37 #include <sys/device.h> 38 #include <sys/param.h> 39 #include <dev/clock_subr.h> 40 41 #include <arm/imx/imxsnvsreg.h> 42 #include <arm/imx/imxsnvsvar.h> 43 44 struct imxsnvs_softc { 45 device_t sc_dev; 46 bus_space_tag_t sc_iot; 47 bus_space_handle_t sc_ioh; 48 struct todr_chip_handle sc_todr; 49 }; 50 51 #define SNVS_READ(sc, reg) \ 52 bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, reg) 53 54 #define SNVS_WRITE(sc, reg, val) \ 55 bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, reg, val) 56 57 static int imxsnvs_rtc_enable(struct imxsnvs_softc *); 58 static int imxsnvs_rtc_disable(struct imxsnvs_softc *); 59 static int imxsnvs_gettime(todr_chip_handle_t, struct timeval *); 60 static int imxsnvs_settime(todr_chip_handle_t, struct timeval *); 61 62 63 CFATTACH_DECL_NEW(imxsnvs, sizeof(struct imxsnvs_softc), 64 imxsnvs_match, imxsnvs_attach, NULL, NULL); 65 66 /* ARGSUSED */ 67 int 68 imxsnvs_attach_common(device_t parent __unused, device_t self, 69 bus_space_tag_t iot, paddr_t iobase, size_t size, 70 int intr __unused, int flags __unused) 71 { 72 struct imxsnvs_softc *sc; 73 uint32_t v1, v2; 74 75 sc = device_private(self); 76 sc->sc_dev = self; 77 sc->sc_iot = iot; 78 79 aprint_naive("\n"); 80 aprint_normal(": Secure Non-Volatile Storage\n"); 81 if (bus_space_map(sc->sc_iot, iobase, size, 0, 82 &sc->sc_ioh)) { 83 aprint_error_dev(self, "Cannot map registers\n"); 84 return 1; 85 } 86 87 v1 = SNVS_READ(sc, SNVS_HPVIDR1); 88 v2 = SNVS_READ(sc, SNVS_HPVIDR2); 89 aprint_verbose_dev(self, "id=0x%llx, ver=%lld.%lld, ip_era=0x%llx, " 90 "intg_opt=0x%llx, eco_rev=0x%llx, config_opt=0x%llx\n", 91 __SHIFTOUT(v1, SNVS_HPVIDR1_IP_ID), 92 __SHIFTOUT(v1, SNVS_HPVIDR1_MAJOR_REV), 93 __SHIFTOUT(v1, SNVS_HPVIDR1_MINOR_REV), 94 __SHIFTOUT(v2, SNVS_HPVIDR2_IP_ERA), 95 __SHIFTOUT(v2, SNVS_HPVIDR2_INTG_OPT), 96 __SHIFTOUT(v2, SNVS_HPVIDR2_ECO_REV), 97 __SHIFTOUT(v2, SNVS_HPVIDR2_CONFIG_OPT)); 98 99 if (imxsnvs_rtc_enable(sc) != 0) { 100 aprint_error_dev(self, "cannot enable RTC\n"); 101 return 1; 102 } 103 104 sc->sc_todr.todr_gettime = imxsnvs_gettime; 105 sc->sc_todr.todr_settime = imxsnvs_settime; 106 sc->sc_todr.todr_dev = self; 107 todr_attach(&sc->sc_todr); 108 109 return 0; 110 } 111 112 static int 113 imxsnvs_rtc_enable(struct imxsnvs_softc *sc) 114 { 115 uint32_t v; 116 int timeout; 117 118 /* enable SRTC */ 119 v = SNVS_READ(sc, SNVS_LPCR); 120 SNVS_WRITE(sc, SNVS_LPCR, v | SNVS_LPCR_SRTC_ENV); 121 for (timeout = 10000; timeout > 0; timeout--) { 122 if (SNVS_READ(sc, SNVS_LPCR) & SNVS_LPCR_SRTC_ENV) 123 break; 124 } 125 if (timeout == 0) 126 return ETIMEDOUT; 127 128 return 0; 129 } 130 131 static int 132 imxsnvs_rtc_disable(struct imxsnvs_softc *sc) 133 { 134 uint32_t v; 135 int timeout; 136 137 /* disable SRTC */ 138 v = SNVS_READ(sc, SNVS_LPCR); 139 SNVS_WRITE(sc, SNVS_LPCR, v & ~SNVS_LPCR_SRTC_ENV); 140 for (timeout = 10000; timeout > 0; timeout--) { 141 if (!(SNVS_READ(sc, SNVS_LPCR) & SNVS_LPCR_SRTC_ENV)) 142 break; 143 } 144 if (timeout == 0) 145 return ETIMEDOUT; 146 147 return 0; 148 } 149 150 static int 151 imxsnvs_gettime(todr_chip_handle_t tch, struct timeval *tvp) 152 { 153 struct imxsnvs_softc *sc = device_private(tch->todr_dev); 154 uint64_t c1, c2; 155 156 c2 = ((uint64_t)SNVS_READ(sc, SNVS_LPSRTCMR) << 32) + 157 SNVS_READ(sc, SNVS_LPSRTCLR); 158 do { 159 c1 = c2; 160 c2 = ((uint64_t)SNVS_READ(sc, SNVS_LPSRTCMR) << 32) + 161 SNVS_READ(sc, SNVS_LPSRTCLR); 162 } while (c1 != c2); 163 164 tvp->tv_sec = c1 >> SVNS_COUNTER_SHIFT; 165 tvp->tv_usec = (c1 % SVNS_COUNTER_HZ) * 1000000 / SVNS_COUNTER_HZ; 166 167 return 0; 168 } 169 170 static int 171 imxsnvs_settime(todr_chip_handle_t tch, struct timeval *tvp) 172 { 173 struct imxsnvs_softc *sc = device_private(tch->todr_dev); 174 uint64_t c, h, l; 175 int rv; 176 177 c = (uint64_t)tvp->tv_sec * SVNS_COUNTER_HZ + 178 (uint64_t)tvp->tv_usec * SVNS_COUNTER_HZ / 1000000; 179 h = __SHIFTIN((c >> 32) & SNVS_LPSRTCMR_SRTC, SNVS_LPSRTCMR_SRTC); 180 l = c & 0xffffffff; 181 182 if ((rv = imxsnvs_rtc_disable(sc)) != 0) 183 return rv; 184 185 SNVS_WRITE(sc, SNVS_LPSRTCMR, h); 186 SNVS_WRITE(sc, SNVS_LPSRTCLR, l); 187 188 if ((rv = imxsnvs_rtc_enable(sc)) != 0) 189 return rv; 190 191 return 0; 192 } 193
Indexes created Sat Sep 20 22:09:52 GMT 2025