pmap.h revision 1.105
1 /* $NetBSD: pmap.h,v 1.105 2012/09/01 12:05:09 martin Exp $ */ 2 3 /* 4 * Copyright (c) 2002, 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe & Steve C. Woodford for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Copyright (c) 1994,1995 Mark Brinicombe. 40 * All rights reserved. 41 * 42 * Redistribution and use in source and binary forms, with or without 43 * modification, are permitted provided that the following conditions 44 * are met: 45 * 1. Redistributions of source code must retain the above copyright 46 * notice, this list of conditions and the following disclaimer. 47 * 2. Redistributions in binary form must reproduce the above copyright 48 * notice, this list of conditions and the following disclaimer in the 49 * documentation and/or other materials provided with the distribution. 50 * 3. All advertising materials mentioning features or use of this software 51 * must display the following acknowledgement: 52 * This product includes software developed by Mark Brinicombe 53 * 4. The name of the author may not be used to endorse or promote products 54 * derived from this software without specific prior written permission. 55 * 56 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 57 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 58 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 59 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 60 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 61 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 62 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 63 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 64 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 65 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 #ifndef _ARM32_PMAP_H_ 69 #define _ARM32_PMAP_H_ 70 71 #ifdef _KERNEL 72 73 #include <arm/cpuconf.h> 74 #include <arm/arm32/pte.h> 75 #include <arm/arm32/machdep.h> 76 #ifndef _LOCORE 77 #if defined(_KERNEL_OPT) 78 #include "opt_arm32_pmap.h" 79 #endif 80 #include <arm/cpufunc.h> 81 #include <uvm/uvm_object.h> 82 #endif 83 84 /* 85 * a pmap describes a processes' 4GB virtual address space. this 86 * virtual address space can be broken up into 4096 1MB regions which 87 * are described by L1 PTEs in the L1 table. 88 * 89 * There is a line drawn at KERNEL_BASE. Everything below that line 90 * changes when the VM context is switched. Everything above that line 91 * is the same no matter which VM context is running. This is achieved 92 * by making the L1 PTEs for those slots above KERNEL_BASE reference 93 * kernel L2 tables. 94 * 95 * The basic layout of the virtual address space thus looks like this: 96 * 97 * 0xffffffff 98 * . 99 * . 100 * . 101 * KERNEL_BASE 102 * -------------------- 103 * . 104 * . 105 * . 106 * 0x00000000 107 */ 108 109 /* 110 * The number of L2 descriptor tables which can be tracked by an l2_dtable. 111 * A bucket size of 16 provides for 16MB of contiguous virtual address 112 * space per l2_dtable. Most processes will, therefore, require only two or 113 * three of these to map their whole working set. 114 */ 115 #define L2_BUCKET_LOG2 4 116 #define L2_BUCKET_SIZE (1 << L2_BUCKET_LOG2) 117 118 /* 119 * Given the above "L2-descriptors-per-l2_dtable" constant, the number 120 * of l2_dtable structures required to track all possible page descriptors 121 * mappable by an L1 translation table is given by the following constants: 122 */ 123 #define L2_LOG2 ((32 - L1_S_SHIFT) - L2_BUCKET_LOG2) 124 #define L2_SIZE (1 << L2_LOG2) 125 126 /* 127 * tell MI code that the cache is virtually-indexed. 128 * ARMv6 is physically-tagged but all others are virtually-tagged. 129 */ 130 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 131 #define PMAP_CACHE_VIPT 132 #else 133 #define PMAP_CACHE_VIVT 134 #endif 135 136 #ifndef _LOCORE 137 138 struct l1_ttable; 139 struct l2_dtable; 140 141 /* 142 * Track cache/tlb occupancy using the following structure 143 */ 144 union pmap_cache_state { 145 struct { 146 union { 147 u_int8_t csu_cache_b[2]; 148 u_int16_t csu_cache; 149 } cs_cache_u; 150 151 union { 152 u_int8_t csu_tlb_b[2]; 153 u_int16_t csu_tlb; 154 } cs_tlb_u; 155 } cs_s; 156 u_int32_t cs_all; 157 }; 158 #define cs_cache_id cs_s.cs_cache_u.csu_cache_b[0] 159 #define cs_cache_d cs_s.cs_cache_u.csu_cache_b[1] 160 #define cs_cache cs_s.cs_cache_u.csu_cache 161 #define cs_tlb_id cs_s.cs_tlb_u.csu_tlb_b[0] 162 #define cs_tlb_d cs_s.cs_tlb_u.csu_tlb_b[1] 163 #define cs_tlb cs_s.cs_tlb_u.csu_tlb 164 165 /* 166 * Assigned to cs_all to force cacheops to work for a particular pmap 167 */ 168 #define PMAP_CACHE_STATE_ALL 0xffffffffu 169 170 /* 171 * This structure is used by machine-dependent code to describe 172 * static mappings of devices, created at bootstrap time. 173 */ 174 struct pmap_devmap { 175 vaddr_t pd_va; /* virtual address */ 176 paddr_t pd_pa; /* physical address */ 177 psize_t pd_size; /* size of region */ 178 vm_prot_t pd_prot; /* protection code */ 179 int pd_cache; /* cache attributes */ 180 }; 181 182 /* 183 * The pmap structure itself 184 */ 185 struct pmap { 186 u_int8_t pm_domain; 187 bool pm_remove_all; 188 bool pm_activated; 189 struct l1_ttable *pm_l1; 190 pd_entry_t *pm_pl1vec; 191 pd_entry_t pm_l1vec; 192 union pmap_cache_state pm_cstate; 193 struct uvm_object pm_obj; 194 kmutex_t pm_obj_lock; 195 #define pm_lock pm_obj.vmobjlock 196 struct l2_dtable *pm_l2[L2_SIZE]; 197 struct pmap_statistics pm_stats; 198 LIST_ENTRY(pmap) pm_list; 199 }; 200 201 extern pv_addrqh_t pmap_freeq; 202 extern pv_addr_t kernelstack; 203 extern pv_addr_t abtstack; 204 extern pv_addr_t fiqstack; 205 extern pv_addr_t irqstack; 206 extern pv_addr_t undstack; 207 extern pv_addr_t idlestack; 208 extern pv_addr_t systempage; 209 extern pv_addr_t kernel_l1pt; 210 211 /* 212 * Determine various modes for PTEs (user vs. kernel, cacheable 213 * vs. non-cacheable). 214 */ 215 #define PTE_KERNEL 0 216 #define PTE_USER 1 217 #define PTE_NOCACHE 0 218 #define PTE_CACHE 1 219 #define PTE_PAGETABLE 2 220 221 /* 222 * Flags that indicate attributes of pages or mappings of pages. 223 * 224 * The PVF_MOD and PVF_REF flags are stored in the mdpage for each 225 * page. PVF_WIRED, PVF_WRITE, and PVF_NC are kept in individual 226 * pv_entry's for each page. They live in the same "namespace" so 227 * that we can clear multiple attributes at a time. 228 * 229 * Note the "non-cacheable" flag generally means the page has 230 * multiple mappings in a given address space. 231 */ 232 #define PVF_MOD 0x01 /* page is modified */ 233 #define PVF_REF 0x02 /* page is referenced */ 234 #define PVF_WIRED 0x04 /* mapping is wired */ 235 #define PVF_WRITE 0x08 /* mapping is writable */ 236 #define PVF_EXEC 0x10 /* mapping is executable */ 237 #ifdef PMAP_CACHE_VIVT 238 #define PVF_UNC 0x20 /* mapping is 'user' non-cacheable */ 239 #define PVF_KNC 0x40 /* mapping is 'kernel' non-cacheable */ 240 #define PVF_NC (PVF_UNC|PVF_KNC) 241 #endif 242 #ifdef PMAP_CACHE_VIPT 243 #define PVF_NC 0x20 /* mapping is 'kernel' non-cacheable */ 244 #define PVF_MULTCLR 0x40 /* mapping is multi-colored */ 245 #endif 246 #define PVF_COLORED 0x80 /* page has or had a color */ 247 #define PVF_KENTRY 0x0100 /* page entered via pmap_kenter_pa */ 248 #define PVF_KMPAGE 0x0200 /* page is used for kmem */ 249 #define PVF_DIRTY 0x0400 /* page may have dirty cache lines */ 250 #define PVF_KMOD 0x0800 /* unmanaged page is modified */ 251 #define PVF_KWRITE (PVF_KENTRY|PVF_WRITE) 252 #define PVF_DMOD (PVF_MOD|PVF_KMOD|PVF_KMPAGE) 253 254 /* 255 * Commonly referenced structures 256 */ 257 extern int pmap_debug_level; /* Only exists if PMAP_DEBUG */ 258 259 /* 260 * Macros that we need to export 261 */ 262 #define pmap_resident_count(pmap) ((pmap)->pm_stats.resident_count) 263 #define pmap_wired_count(pmap) ((pmap)->pm_stats.wired_count) 264 265 #define pmap_is_modified(pg) \ 266 (((pg)->mdpage.pvh_attrs & PVF_MOD) != 0) 267 #define pmap_is_referenced(pg) \ 268 (((pg)->mdpage.pvh_attrs & PVF_REF) != 0) 269 #define pmap_is_page_colored_p(md) \ 270 (((md)->pvh_attrs & PVF_COLORED) != 0) 271 272 #define pmap_copy(dp, sp, da, l, sa) /* nothing */ 273 274 #define pmap_phys_address(ppn) (arm_ptob((ppn))) 275 u_int arm32_mmap_flags(paddr_t); 276 #define ARM32_MMAP_WRITECOMBINE 0x40000000 277 #define ARM32_MMAP_CACHEABLE 0x20000000 278 #define pmap_mmap_flags(ppn) arm32_mmap_flags(ppn) 279 280 /* 281 * Functions that we need to export 282 */ 283 void pmap_procwr(struct proc *, vaddr_t, int); 284 void pmap_remove_all(pmap_t); 285 bool pmap_extract(pmap_t, vaddr_t, paddr_t *); 286 287 #define PMAP_NEED_PROCWR 288 #define PMAP_GROWKERNEL /* turn on pmap_growkernel interface */ 289 #define PMAP_ENABLE_PMAP_KMPAGE /* enable the PMAP_KMPAGE flag */ 290 291 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 292 #define PMAP_PREFER(hint, vap, sz, td) pmap_prefer((hint), (vap), (td)) 293 void pmap_prefer(vaddr_t, vaddr_t *, int); 294 #endif 295 296 void pmap_icache_sync_range(pmap_t, vaddr_t, vaddr_t); 297 298 /* Functions we use internally. */ 299 #ifdef PMAP_STEAL_MEMORY 300 void pmap_boot_pagealloc(psize_t, psize_t, psize_t, pv_addr_t *); 301 void pmap_boot_pageadd(pv_addr_t *); 302 vaddr_t pmap_steal_memory(vsize_t, vaddr_t *, vaddr_t *); 303 #endif 304 void pmap_bootstrap(vaddr_t, vaddr_t); 305 306 void pmap_do_remove(pmap_t, vaddr_t, vaddr_t, int); 307 int pmap_fault_fixup(pmap_t, vaddr_t, vm_prot_t, int); 308 bool pmap_get_pde_pte(pmap_t, vaddr_t, pd_entry_t **, pt_entry_t **); 309 bool pmap_get_pde(pmap_t, vaddr_t, pd_entry_t **); 310 void pmap_set_pcb_pagedir(pmap_t, struct pcb *); 311 312 void pmap_debug(int); 313 void pmap_postinit(void); 314 315 void vector_page_setprot(int); 316 317 const struct pmap_devmap *pmap_devmap_find_pa(paddr_t, psize_t); 318 const struct pmap_devmap *pmap_devmap_find_va(vaddr_t, vsize_t); 319 320 /* Bootstrapping routines. */ 321 void pmap_map_section(vaddr_t, vaddr_t, paddr_t, int, int); 322 void pmap_map_entry(vaddr_t, vaddr_t, paddr_t, int, int); 323 vsize_t pmap_map_chunk(vaddr_t, vaddr_t, paddr_t, vsize_t, int, int); 324 void pmap_link_l2pt(vaddr_t, vaddr_t, pv_addr_t *); 325 void pmap_devmap_bootstrap(vaddr_t, const struct pmap_devmap *); 326 void pmap_devmap_register(const struct pmap_devmap *); 327 328 /* 329 * Special page zero routine for use by the idle loop (no cache cleans). 330 */ 331 bool pmap_pageidlezero(paddr_t); 332 #define PMAP_PAGEIDLEZERO(pa) pmap_pageidlezero((pa)) 333 334 /* 335 * used by dumpsys to record the PA of the L1 table 336 */ 337 uint32_t pmap_kernel_L1_addr(void); 338 /* 339 * The current top of kernel VM 340 */ 341 extern vaddr_t pmap_curmaxkvaddr; 342 343 /* 344 * Useful macros and constants 345 */ 346 347 /* Virtual address to page table entry */ 348 static inline pt_entry_t * 349 vtopte(vaddr_t va) 350 { 351 pd_entry_t *pdep; 352 pt_entry_t *ptep; 353 354 if (pmap_get_pde_pte(pmap_kernel(), va, &pdep, &ptep) == false) 355 return (NULL); 356 return (ptep); 357 } 358 359 /* 360 * Virtual address to physical address 361 */ 362 static inline paddr_t 363 vtophys(vaddr_t va) 364 { 365 paddr_t pa; 366 367 if (pmap_extract(pmap_kernel(), va, &pa) == false) 368 return (0); /* XXXSCW: Panic? */ 369 370 return (pa); 371 } 372 373 /* 374 * The new pmap ensures that page-tables are always mapping Write-Thru. 375 * Thus, on some platforms we can run fast and loose and avoid syncing PTEs 376 * on every change. 377 * 378 * Unfortunately, not all CPUs have a write-through cache mode. So we 379 * define PMAP_NEEDS_PTE_SYNC for C code to conditionally do PTE syncs, 380 * and if there is the chance for PTE syncs to be needed, we define 381 * PMAP_INCLUDE_PTE_SYNC so e.g. assembly code can include (and run) 382 * the code. 383 */ 384 extern int pmap_needs_pte_sync; 385 #if defined(_KERNEL_OPT) 386 /* 387 * StrongARM SA-1 caches do not have a write-through mode. So, on these, 388 * we need to do PTE syncs. If only SA-1 is configured, then evaluate 389 * this at compile time. 390 */ 391 #if (ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7 != 0) && (ARM_NMMUS == 1) 392 #define PMAP_INCLUDE_PTE_SYNC 393 #if (ARM_MMU_V7 > 0) 394 #define PMAP_NEEDS_PTE_SYNC 1 395 #else 396 #define PMAP_NEEDS_PTE_SYNC 1 397 #endif 398 #elif (ARM_MMU_SA1 == 0) 399 #define PMAP_NEEDS_PTE_SYNC 0 400 #endif 401 #endif /* _KERNEL_OPT */ 402 403 /* 404 * Provide a fallback in case we were not able to determine it at 405 * compile-time. 406 */ 407 #ifndef PMAP_NEEDS_PTE_SYNC 408 #define PMAP_NEEDS_PTE_SYNC pmap_needs_pte_sync 409 #define PMAP_INCLUDE_PTE_SYNC 410 #endif 411 412 static inline void 413 pmap_ptesync(pt_entry_t *ptep, size_t cnt) 414 { 415 if (PMAP_NEEDS_PTE_SYNC) 416 cpu_dcache_wb_range((vaddr_t)ptep, cnt * sizeof(pt_entry_t)); 417 #if ARM_MMU_V7 > 0 418 __asm("dsb"); 419 #endif 420 } 421 422 #define PTE_SYNC(ptep) pmap_ptesync((ptep), 1) 423 #define PTE_SYNC_RANGE(ptep, cnt) pmap_ptesync((ptep), (cnt)) 424 425 #define l1pte_valid(pde) ((pde) != 0) 426 #define l1pte_section_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_S) 427 #define l1pte_supersection_p(pde) (l1pte_section_p(pde) \ 428 && ((pde) & L1_S_V6_SUPER) != 0) 429 #define l1pte_page_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_C) 430 #define l1pte_fpage_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_F) 431 432 #define l2pte_index(v) (((v) & L2_ADDR_BITS) >> L2_S_SHIFT) 433 #define l2pte_valid(pte) (((pte) & L2_TYPE_MASK) != L2_TYPE_INV) 434 #define l2pte_pa(pte) ((pte) & L2_S_FRAME) 435 #define l2pte_minidata(pte) (((pte) & \ 436 (L2_B | L2_C | L2_XS_T_TEX(TEX_XSCALE_X)))\ 437 == (L2_C | L2_XS_T_TEX(TEX_XSCALE_X))) 438 439 /* L1 and L2 page table macros */ 440 #define pmap_pde_v(pde) l1pte_valid(*(pde)) 441 #define pmap_pde_section(pde) l1pte_section_p(*(pde)) 442 #define pmap_pde_page(pde) l1pte_page_p(*(pde)) 443 #define pmap_pde_fpage(pde) l1pte_fpage_p(*(pde)) 444 445 #define pmap_pte_v(pte) l2pte_valid(*(pte)) 446 #define pmap_pte_pa(pte) l2pte_pa(*(pte)) 447 448 /* Size of the kernel part of the L1 page table */ 449 #define KERNEL_PD_SIZE \ 450 (L1_TABLE_SIZE - (KERNEL_BASE >> L1_S_SHIFT) * sizeof(pd_entry_t)) 451 452 /************************* ARM MMU configuration *****************************/ 453 454 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 455 void pmap_copy_page_generic(paddr_t, paddr_t); 456 void pmap_zero_page_generic(paddr_t); 457 458 void pmap_pte_init_generic(void); 459 #if defined(CPU_ARM8) 460 void pmap_pte_init_arm8(void); 461 #endif 462 #if defined(CPU_ARM9) 463 void pmap_pte_init_arm9(void); 464 #endif /* CPU_ARM9 */ 465 #if defined(CPU_ARM10) 466 void pmap_pte_init_arm10(void); 467 #endif /* CPU_ARM10 */ 468 #if defined(CPU_ARM11) /* ARM_MMU_V6 */ 469 void pmap_pte_init_arm11(void); 470 #endif /* CPU_ARM11 */ 471 #if defined(CPU_ARM11MPCORE) /* ARM_MMU_V6 */ 472 void pmap_pte_init_arm11mpcore(void); 473 #endif 474 #if ARM_MMU_V7 == 1 475 void pmap_pte_init_armv7(void); 476 #endif /* ARM_MMU_V7 */ 477 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */ 478 479 #if ARM_MMU_SA1 == 1 480 void pmap_pte_init_sa1(void); 481 #endif /* ARM_MMU_SA1 == 1 */ 482 483 #if ARM_MMU_XSCALE == 1 484 void pmap_copy_page_xscale(paddr_t, paddr_t); 485 void pmap_zero_page_xscale(paddr_t); 486 487 void pmap_pte_init_xscale(void); 488 489 void xscale_setup_minidata(vaddr_t, vaddr_t, paddr_t); 490 491 #define PMAP_UAREA(va) pmap_uarea(va) 492 void pmap_uarea(vaddr_t); 493 #endif /* ARM_MMU_XSCALE == 1 */ 494 495 extern pt_entry_t pte_l1_s_cache_mode; 496 extern pt_entry_t pte_l1_s_cache_mask; 497 498 extern pt_entry_t pte_l2_l_cache_mode; 499 extern pt_entry_t pte_l2_l_cache_mask; 500 501 extern pt_entry_t pte_l2_s_cache_mode; 502 extern pt_entry_t pte_l2_s_cache_mask; 503 504 extern pt_entry_t pte_l1_s_cache_mode_pt; 505 extern pt_entry_t pte_l2_l_cache_mode_pt; 506 extern pt_entry_t pte_l2_s_cache_mode_pt; 507 508 extern pt_entry_t pte_l1_s_wc_mode; 509 extern pt_entry_t pte_l2_l_wc_mode; 510 extern pt_entry_t pte_l2_s_wc_mode; 511 512 extern pt_entry_t pte_l1_s_prot_u; 513 extern pt_entry_t pte_l1_s_prot_w; 514 extern pt_entry_t pte_l1_s_prot_ro; 515 extern pt_entry_t pte_l1_s_prot_mask; 516 517 extern pt_entry_t pte_l2_s_prot_u; 518 extern pt_entry_t pte_l2_s_prot_w; 519 extern pt_entry_t pte_l2_s_prot_ro; 520 extern pt_entry_t pte_l2_s_prot_mask; 521 522 extern pt_entry_t pte_l2_l_prot_u; 523 extern pt_entry_t pte_l2_l_prot_w; 524 extern pt_entry_t pte_l2_l_prot_ro; 525 extern pt_entry_t pte_l2_l_prot_mask; 526 527 extern pt_entry_t pte_l1_ss_proto; 528 extern pt_entry_t pte_l1_s_proto; 529 extern pt_entry_t pte_l1_c_proto; 530 extern pt_entry_t pte_l2_s_proto; 531 532 extern void (*pmap_copy_page_func)(paddr_t, paddr_t); 533 extern void (*pmap_zero_page_func)(paddr_t); 534 535 #endif /* !_LOCORE */ 536 537 /*****************************************************************************/ 538 539 /* 540 * Definitions for MMU domains 541 */ 542 #define PMAP_DOMAINS 15 /* 15 'user' domains (1-15) */ 543 #define PMAP_DOMAIN_KERNEL 0 /* The kernel uses domain #0 */ 544 545 /* 546 * These macros define the various bit masks in the PTE. 547 * 548 * We use these macros since we use different bits on different processor 549 * models. 550 */ 551 #define L1_S_PROT_U_generic (L1_S_AP(AP_U)) 552 #define L1_S_PROT_W_generic (L1_S_AP(AP_W)) 553 #define L1_S_PROT_RO_generic (0) 554 #define L1_S_PROT_MASK_generic (L1_S_PROT_U|L1_S_PROT_W|L1_S_PROT_RO) 555 556 #define L1_S_PROT_U_xscale (L1_S_AP(AP_U)) 557 #define L1_S_PROT_W_xscale (L1_S_AP(AP_W)) 558 #define L1_S_PROT_RO_xscale (0) 559 #define L1_S_PROT_MASK_xscale (L1_S_PROT_U|L1_S_PROT_W|L1_S_PROT_RO) 560 561 #define L1_S_PROT_U_armv6 (L1_S_AP(AP_R) | L1_S_AP(AP_U)) 562 #define L1_S_PROT_W_armv6 (L1_S_AP(AP_W)) 563 #define L1_S_PROT_RO_armv6 (L1_S_AP(AP_R) | L1_S_AP(AP_RO)) 564 #define L1_S_PROT_MASK_armv6 (L1_S_PROT_U|L1_S_PROT_W|L1_S_PROT_RO) 565 566 #define L1_S_PROT_U_armv7 (L1_S_AP(AP_R) | L1_S_AP(AP_U)) 567 #define L1_S_PROT_W_armv7 (L1_S_AP(AP_W)) 568 #define L1_S_PROT_RO_armv7 (L1_S_AP(AP_R) | L1_S_AP(AP_RO)) 569 #define L1_S_PROT_MASK_armv7 (L1_S_PROT_U|L1_S_PROT_W|L1_S_PROT_RO) 570 571 #define L1_S_CACHE_MASK_generic (L1_S_B|L1_S_C) 572 #define L1_S_CACHE_MASK_xscale (L1_S_B|L1_S_C|L1_S_XS_TEX(TEX_XSCALE_X)) 573 #define L1_S_CACHE_MASK_armv6 (L1_S_B|L1_S_C|L1_S_XS_TEX(TEX_ARMV6_TEX)) 574 #define L1_S_CACHE_MASK_armv7 (L1_S_B|L1_S_C) 575 576 #define L2_L_PROT_U_generic (L2_AP(AP_U)) 577 #define L2_L_PROT_W_generic (L2_AP(AP_W)) 578 #define L2_L_PROT_RO_generic (0) 579 #define L2_L_PROT_MASK_generic (L2_L_PROT_U|L2_L_PROT_W|L2_L_PROT_RO) 580 581 #define L2_L_PROT_U_xscale (L2_AP(AP_U)) 582 #define L2_L_PROT_W_xscale (L2_AP(AP_W)) 583 #define L2_L_PROT_RO_xscale (0) 584 #define L2_L_PROT_MASK_xscale (L2_L_PROT_U|L2_L_PROT_W|L2_L_PROT_RO) 585 586 #define L2_L_PROT_U_armv6n (L2_AP0(AP_R) | L2_AP0(AP_U)) 587 #define L2_L_PROT_W_armv6n (L2_AP0(AP_W)) 588 #define L2_L_PROT_RO_armv6n (L2_AP0(AP_R) | L2_AP0(AP_RO)) 589 #define L2_L_PROT_MASK_armv6n (L2_L_PROT_U|L2_L_PROT_W|L2_L_PROT_RO) 590 591 #define L2_L_PROT_U_armv7 (L2_AP0(AP_R) | L2_AP0(AP_U)) 592 #define L2_L_PROT_W_armv7 (L2_AP0(AP_W)) 593 #define L2_L_PROT_RO_armv7 (L2_AP0(AP_R) | L2_AP0(AP_RO)) 594 #define L2_L_PROT_MASK_armv7 (L2_L_PROT_U|L2_L_PROT_W|L2_L_PROT_RO) 595 596 #define L2_L_CACHE_MASK_generic (L2_B|L2_C) 597 #define L2_L_CACHE_MASK_xscale (L2_B|L2_C|L2_XS_L_TEX(TEX_XSCALE_X)) 598 #define L2_L_CACHE_MASK_armv6 (L2_B|L2_C|L2_V6_L_TEX(TEX_ARMV6_TEX)) 599 #define L2_L_CACHE_MASK_armv7 (L2_B|L2_C) 600 601 #define L2_S_PROT_U_generic (L2_AP(AP_U)) 602 #define L2_S_PROT_W_generic (L2_AP(AP_W)) 603 #define L2_S_PROT_RO_generic (0) 604 #define L2_S_PROT_MASK_generic (L2_S_PROT_U|L2_S_PROT_W|L2_S_PROT_RO) 605 606 #define L2_S_PROT_U_xscale (L2_AP0(AP_U)) 607 #define L2_S_PROT_W_xscale (L2_AP0(AP_W)) 608 #define L2_S_PROT_RO_xscale (0) 609 #define L2_S_PROT_MASK_xscale (L2_S_PROT_U|L2_S_PROT_W|L2_S_PROT_RO) 610 611 #define L2_S_PROT_U_armv6n (L2_AP0(AP_R) | L2_AP0(AP_U)) 612 #define L2_S_PROT_W_armv6n (L2_AP0(AP_W)) 613 #define L2_S_PROT_RO_armv6n (L2_AP0(AP_R) | L2_AP0(AP_RO)) 614 #define L2_S_PROT_MASK_armv6n (L2_S_PROT_U|L2_S_PROT_W|L2_S_PROT_RO) 615 616 #define L2_S_PROT_U_armv7 (L2_AP0(AP_R) | L2_AP0(AP_U)) 617 #define L2_S_PROT_W_armv7 (L2_AP0(AP_W)) 618 #define L2_S_PROT_RO_armv7 (L2_AP0(AP_R) | L2_AP0(AP_RO)) 619 #define L2_S_PROT_MASK_armv7 (L2_S_PROT_U|L2_S_PROT_W|L2_S_PROT_RO) 620 621 #define L2_S_CACHE_MASK_generic (L2_B|L2_C) 622 #define L2_S_CACHE_MASK_xscale (L2_B|L2_C|L2_XS_T_TEX(TEX_XSCALE_X)) 623 #define L2_XS_CACHE_MASK_armv6 (L2_B|L2_C|L2_V6_XS_TEX(TEX_ARMV6_TEX)) 624 #define L2_S_CACHE_MASK_armv6n L2_XS_CACHE_MASK_armv6 625 #ifdef ARMV6_EXTENDED_SMALL_PAGE 626 #define L2_S_CACHE_MASK_armv6c L2_XS_CACHE_MASK_armv6 627 #else 628 #define L2_S_CACHE_MASK_armv6c L2_S_CACHE_MASK_generic 629 #endif 630 #define L2_S_CACHE_MASK_armv7 (L2_B|L2_C) 631 632 633 #define L1_S_PROTO_generic (L1_TYPE_S | L1_S_IMP) 634 #define L1_S_PROTO_xscale (L1_TYPE_S) 635 #define L1_S_PROTO_armv6 (L1_TYPE_S) 636 #define L1_S_PROTO_armv7 (L1_TYPE_S) 637 638 #define L1_SS_PROTO_generic 0 639 #define L1_SS_PROTO_xscale 0 640 #define L1_SS_PROTO_armv6 (L1_TYPE_S | L1_S_V6_SS) 641 #define L1_SS_PROTO_armv7 (L1_TYPE_S | L1_S_V6_SS) 642 643 #define L1_C_PROTO_generic (L1_TYPE_C | L1_C_IMP2) 644 #define L1_C_PROTO_xscale (L1_TYPE_C) 645 #define L1_C_PROTO_armv6 (L1_TYPE_C) 646 #define L1_C_PROTO_armv7 (L1_TYPE_C) 647 648 #define L2_L_PROTO (L2_TYPE_L) 649 650 #define L2_S_PROTO_generic (L2_TYPE_S) 651 #define L2_S_PROTO_xscale (L2_TYPE_XS) 652 #ifdef ARMV6_EXTENDED_SMALL_PAGE 653 #define L2_S_PROTO_armv6c (L2_TYPE_XS) /* XP=0, extended small page */ 654 #else 655 #define L2_S_PROTO_armv6c (L2_TYPE_S) /* XP=0, subpage APs */ 656 #endif 657 #define L2_S_PROTO_armv6n (L2_TYPE_S) /* with XP=1 */ 658 #define L2_S_PROTO_armv7 (L2_TYPE_S) 659 660 /* 661 * User-visible names for the ones that vary with MMU class. 662 */ 663 664 #if ARM_NMMUS > 1 665 /* More than one MMU class configured; use variables. */ 666 #define L1_S_PROT_U pte_l1_s_prot_u 667 #define L1_S_PROT_W pte_l1_s_prot_w 668 #define L1_S_PROT_RO pte_l1_s_prot_ro 669 #define L1_S_PROT_MASK pte_l1_s_prot_mask 670 671 #define L2_S_PROT_U pte_l2_s_prot_u 672 #define L2_S_PROT_W pte_l2_s_prot_w 673 #define L2_S_PROT_RO pte_l2_s_prot_ro 674 #define L2_S_PROT_MASK pte_l2_s_prot_mask 675 676 #define L2_L_PROT_U pte_l2_l_prot_u 677 #define L2_L_PROT_W pte_l2_l_prot_w 678 #define L2_L_PROT_RO pte_l2_l_prot_ro 679 #define L2_L_PROT_MASK pte_l2_l_prot_mask 680 681 #define L1_S_CACHE_MASK pte_l1_s_cache_mask 682 #define L2_L_CACHE_MASK pte_l2_l_cache_mask 683 #define L2_S_CACHE_MASK pte_l2_s_cache_mask 684 685 #define L1_SS_PROTO pte_l1_ss_proto 686 #define L1_S_PROTO pte_l1_s_proto 687 #define L1_C_PROTO pte_l1_c_proto 688 #define L2_S_PROTO pte_l2_s_proto 689 690 #define pmap_copy_page(s, d) (*pmap_copy_page_func)((s), (d)) 691 #define pmap_zero_page(d) (*pmap_zero_page_func)((d)) 692 #elif (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 693 #define L1_S_PROT_U L1_S_PROT_U_generic 694 #define L1_S_PROT_W L1_S_PROT_W_generic 695 #define L1_S_PROT_RO L1_S_PROT_RO_generic 696 #define L1_S_PROT_MASK L1_S_PROT_MASK_generic 697 698 #define L2_S_PROT_U L2_S_PROT_U_generic 699 #define L2_S_PROT_W L2_S_PROT_W_generic 700 #define L2_S_PROT_RO L2_S_PROT_RO_generic 701 #define L2_S_PROT_MASK L2_S_PROT_MASK_generic 702 703 #define L2_L_PROT_U L2_L_PROT_U_generic 704 #define L2_L_PROT_W L2_L_PROT_W_generic 705 #define L2_L_PROT_RO L2_L_PROT_RO_generic 706 #define L2_L_PROT_MASK L2_L_PROT_MASK_generic 707 708 #define L1_S_CACHE_MASK L1_S_CACHE_MASK_generic 709 #define L2_L_CACHE_MASK L2_L_CACHE_MASK_generic 710 #define L2_S_CACHE_MASK L2_S_CACHE_MASK_generic 711 712 #define L1_SS_PROTO L1_SS_PROTO_generic 713 #define L1_S_PROTO L1_S_PROTO_generic 714 #define L1_C_PROTO L1_C_PROTO_generic 715 #define L2_S_PROTO L2_S_PROTO_generic 716 717 #define pmap_copy_page(s, d) pmap_copy_page_generic((s), (d)) 718 #define pmap_zero_page(d) pmap_zero_page_generic((d)) 719 #elif ARM_MMU_V6N != 0 720 #define L1_S_PROT_U L1_S_PROT_U_armv6 721 #define L1_S_PROT_W L1_S_PROT_W_armv6 722 #define L1_S_PROT_RO L1_S_PROT_RO_armv6 723 #define L1_S_PROT_MASK L1_S_PROT_MASK_armv6 724 725 #define L2_S_PROT_U L2_S_PROT_U_armv6n 726 #define L2_S_PROT_W L2_S_PROT_W_armv6n 727 #define L2_S_PROT_RO L2_S_PROT_RO_armv6n 728 #define L2_S_PROT_MASK L2_S_PROT_MASK_armv6n 729 730 #define L2_L_PROT_U L2_L_PROT_U_armv6n 731 #define L2_L_PROT_W L2_L_PROT_W_armv6n 732 #define L2_L_PROT_RO L2_L_PROT_RO_armv6n 733 #define L2_L_PROT_MASK L2_L_PROT_MASK_armv6n 734 735 #define L1_S_CACHE_MASK L1_S_CACHE_MASK_armv6 736 #define L2_L_CACHE_MASK L2_L_CACHE_MASK_armv6 737 #define L2_S_CACHE_MASK L2_S_CACHE_MASK_armv6n 738 739 /* These prototypes make writeable mappings, while the other MMU types 740 * make read-only mappings. */ 741 #define L1_SS_PROTO L1_SS_PROTO_armv6 742 #define L1_S_PROTO L1_S_PROTO_armv6 743 #define L1_C_PROTO L1_C_PROTO_armv6 744 #define L2_S_PROTO L2_S_PROTO_armv6n 745 746 #define pmap_copy_page(s, d) pmap_copy_page_generic((s), (d)) 747 #define pmap_zero_page(d) pmap_zero_page_generic((d)) 748 #elif ARM_MMU_V6C != 0 749 #define L1_S_PROT_U L1_S_PROT_U_generic 750 #define L1_S_PROT_W L1_S_PROT_W_generic 751 #define L1_S_PROT_RO L1_S_PROT_RO_generic 752 #define L1_S_PROT_MASK L1_S_PROT_MASK_generic 753 754 #define L2_S_PROT_U L2_S_PROT_U_generic 755 #define L2_S_PROT_W L2_S_PROT_W_generic 756 #define L2_S_PROT_RO L2_S_PROT_RO_generic 757 #define L2_S_PROT_MASK L2_S_PROT_MASK_generic 758 759 #define L2_L_PROT_U L2_L_PROT_U_generic 760 #define L2_L_PROT_W L2_L_PROT_W_generic 761 #define L2_L_PROT_RO L2_L_PROT_RO_generic 762 #define L2_L_PROT_MASK L2_L_PROT_MASK_generic 763 764 #define L1_S_CACHE_MASK L1_S_CACHE_MASK_generic 765 #define L2_L_CACHE_MASK L2_L_CACHE_MASK_generic 766 #define L2_S_CACHE_MASK L2_S_CACHE_MASK_generic 767 768 #define L1_SS_PROTO L1_SS_PROTO_generic 769 #define L1_S_PROTO L1_S_PROTO_generic 770 #define L1_C_PROTO L1_C_PROTO_generic 771 #define L2_S_PROTO L2_S_PROTO_generic 772 773 #define pmap_copy_page(s, d) pmap_copy_page_generic((s), (d)) 774 #define pmap_zero_page(d) pmap_zero_page_generic((d)) 775 #elif ARM_MMU_XSCALE == 1 776 #define L1_S_PROT_U L1_S_PROT_U_generic 777 #define L1_S_PROT_W L1_S_PROT_W_generic 778 #define L1_S_PROT_RO L1_S_PROT_RO_generic 779 #define L1_S_PROT_MASK L1_S_PROT_MASK_generic 780 781 #define L2_S_PROT_U L2_S_PROT_U_xscale 782 #define L2_S_PROT_W L2_S_PROT_W_xscale 783 #define L2_S_PROT_RO L2_S_PROT_RO_xscale 784 #define L2_S_PROT_MASK L2_S_PROT_MASK_xscale 785 786 #define L2_L_PROT_U L2_L_PROT_U_generic 787 #define L2_L_PROT_W L2_L_PROT_W_generic 788 #define L2_L_PROT_RO L2_L_PROT_RO_generic 789 #define L2_L_PROT_MASK L2_L_PROT_MASK_generic 790 791 #define L1_S_CACHE_MASK L1_S_CACHE_MASK_xscale 792 #define L2_L_CACHE_MASK L2_L_CACHE_MASK_xscale 793 #define L2_S_CACHE_MASK L2_S_CACHE_MASK_xscale 794 795 #define L1_SS_PROTO L1_SS_PROTO_xscale 796 #define L1_S_PROTO L1_S_PROTO_xscale 797 #define L1_C_PROTO L1_C_PROTO_xscale 798 #define L2_S_PROTO L2_S_PROTO_xscale 799 800 #define pmap_copy_page(s, d) pmap_copy_page_xscale((s), (d)) 801 #define pmap_zero_page(d) pmap_zero_page_xscale((d)) 802 #elif ARM_MMU_V7 == 1 803 #define L1_S_PROT_U L1_S_PROT_U_armv7 804 #define L1_S_PROT_W L1_S_PROT_W_armv7 805 #define L1_S_PROT_RO L1_S_PROT_RO_armv7 806 #define L1_S_PROT_MASK L1_S_PROT_MASK_armv7 807 808 #define L2_S_PROT_U L2_S_PROT_U_armv7 809 #define L2_S_PROT_W L2_S_PROT_W_armv7 810 #define L2_S_PROT_RO L2_S_PROT_RO_armv7 811 #define L2_S_PROT_MASK L2_S_PROT_MASK_armv7 812 813 #define L2_L_PROT_U L2_L_PROT_U_armv7 814 #define L2_L_PROT_W L2_L_PROT_W_armv7 815 #define L2_L_PROT_RO L2_L_PROT_RO_armv7 816 #define L2_L_PROT_MASK L2_L_PROT_MASK_armv7 817 818 #define L1_S_CACHE_MASK L1_S_CACHE_MASK_armv7 819 #define L2_L_CACHE_MASK L2_L_CACHE_MASK_armv7 820 #define L2_S_CACHE_MASK L2_S_CACHE_MASK_armv7 821 822 /* These prototypes make writeable mappings, while the other MMU types 823 * make read-only mappings. */ 824 #define L1_SS_PROTO L1_SS_PROTO_armv7 825 #define L1_S_PROTO L1_S_PROTO_armv7 826 #define L1_C_PROTO L1_C_PROTO_armv7 827 #define L2_S_PROTO L2_S_PROTO_armv7 828 829 #define pmap_copy_page(s, d) pmap_copy_page_generic((s), (d)) 830 #define pmap_zero_page(d) pmap_zero_page_generic((d)) 831 #endif /* ARM_NMMUS > 1 */ 832 833 /* 834 * Macros to set and query the write permission on page descriptors. 835 */ 836 #define l1pte_set_writable(pte) (((pte) & ~L1_S_PROT_RO) | L1_S_PROT_W) 837 #define l1pte_set_readonly(pte) (((pte) & ~L1_S_PROT_W) | L1_S_PROT_RO) 838 #define l2pte_set_writable(pte) (((pte) & ~L2_S_PROT_RO) | L2_S_PROT_W) 839 #define l2pte_set_readonly(pte) (((pte) & ~L2_S_PROT_W) | L2_S_PROT_RO) 840 841 #define l2pte_writable_p(pte) (((pte) & L2_S_PROT_W) == L2_S_PROT_W && \ 842 (L2_S_PROT_RO == 0 || \ 843 ((pte) & L2_S_PROT_RO) != L2_S_PROT_RO)) 844 845 /* 846 * These macros return various bits based on kernel/user and protection. 847 * Note that the compiler will usually fold these at compile time. 848 */ 849 #define L1_S_PROT(ku, pr) ((((ku) == PTE_USER) ? L1_S_PROT_U : 0) | \ 850 (((pr) & VM_PROT_WRITE) ? L1_S_PROT_W : L1_S_PROT_RO)) 851 852 #define L2_L_PROT(ku, pr) ((((ku) == PTE_USER) ? L2_L_PROT_U : 0) | \ 853 (((pr) & VM_PROT_WRITE) ? L2_L_PROT_W : L2_L_PROT_RO)) 854 855 #define L2_S_PROT(ku, pr) ((((ku) == PTE_USER) ? L2_S_PROT_U : 0) | \ 856 (((pr) & VM_PROT_WRITE) ? L2_S_PROT_W : L2_S_PROT_RO)) 857 858 /* 859 * Macros to test if a mapping is mappable with an L1 SuperSection, 860 * L1 Section, or an L2 Large Page mapping. 861 */ 862 #define L1_SS_MAPPABLE_P(va, pa, size) \ 863 ((((va) | (pa)) & L1_SS_OFFSET) == 0 && (size) >= L1_SS_SIZE) 864 865 #define L1_S_MAPPABLE_P(va, pa, size) \ 866 ((((va) | (pa)) & L1_S_OFFSET) == 0 && (size) >= L1_S_SIZE) 867 868 #define L2_L_MAPPABLE_P(va, pa, size) \ 869 ((((va) | (pa)) & L2_L_OFFSET) == 0 && (size) >= L2_L_SIZE) 870 871 /* 872 * Hooks for the pool allocator. 873 */ 874 #define POOL_VTOPHYS(va) vtophys((vaddr_t) (va)) 875 876 #ifndef _LOCORE 877 878 /* 879 * pmap-specific data store in the vm_page structure. 880 */ 881 #define __HAVE_VM_PAGE_MD 882 struct vm_page_md { 883 SLIST_HEAD(,pv_entry) pvh_list; /* pv_entry list */ 884 int pvh_attrs; /* page attributes */ 885 u_int uro_mappings; 886 u_int urw_mappings; 887 union { 888 u_short s_mappings[2]; /* Assume kernel count <= 65535 */ 889 u_int i_mappings; 890 } k_u; 891 #define kro_mappings k_u.s_mappings[0] 892 #define krw_mappings k_u.s_mappings[1] 893 #define k_mappings k_u.i_mappings 894 }; 895 896 /* 897 * Set the default color of each page. 898 */ 899 #if ARM_MMU_V6 > 0 900 #define VM_MDPAGE_PVH_ATTRS_INIT(pg) \ 901 (pg)->mdpage.pvh_attrs = (pg)->phys_addr & arm_cache_prefer_mask 902 #else 903 #define VM_MDPAGE_PVH_ATTRS_INIT(pg) \ 904 (pg)->mdpage.pvh_attrs = 0 905 #endif 906 907 #define VM_MDPAGE_INIT(pg) \ 908 do { \ 909 SLIST_INIT(&(pg)->mdpage.pvh_list); \ 910 VM_MDPAGE_PVH_ATTRS_INIT(pg); \ 911 (pg)->mdpage.uro_mappings = 0; \ 912 (pg)->mdpage.urw_mappings = 0; \ 913 (pg)->mdpage.k_mappings = 0; \ 914 } while (/*CONSTCOND*/0) 915 916 #endif /* !_LOCORE */ 917 918 #endif /* _KERNEL */ 919 920 #endif /* _ARM32_PMAP_H_ */ 921
Indexes created Sun Sep 28 16:09:52 GMT 2025