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History log of /src/sys/arch/arm/include/arm32/pmap.h
RevisionDateAuthorComments
 1.178  09-Oct-2025  skrll Add the beginnings of a GENERIC_V5 kernel that targets armv5 boards and
uses FDT.

In this first iteration some support is added for OLinuXino boards.

Thanks to Yuri Honegger for doing the vast majority of the work.
 1.177  12-Oct-2023  skrll Fix non-DIAGNOSTIC builds
 1.176  02-Aug-2023  skrll No need to define cpu_{,set}_tlb_info here - just use the
sys/uvm/pmap/pmap_tlb.h versions.
 1.175  24-Apr-2023  martin Fix DEVMAP_FLAGS, patch from Nick.
 1.174  20-Apr-2023  skrll Provide a shared pmap_devmap implementation and convert all pmap_devmap
arrays to use DEVMAP_ENTRY{,_END}
 1.173  02-Apr-2022  skrll branches: 1.173.4;
Update to support EFI runtime outside the kernel virtual address space
by creating an EFI RT pmap that can be activated / deactivated when
required.

Adds support for EFI RT to ARM_MMU_EXTENDED (ASID) 32-bit Arm machines.

On Arm64 the usage of pmapboot_enter is reduced and the mappings are
created much later in the boot process -- now in cpu_startup_hook.
Backward compatiblity for KVA mapped RT from old bootaa64.efi is
maintained.

Adding support to other platforms should be easier as a result.
 1.172  15-Jan-2022  skrll Remove unnecessary brackets
 1.171  16-Oct-2021  skrll pm_remove_all is a shared field so move it out the #ifdefs
 1.170  04-May-2021  skrll Provide pte_{value,valid_p}
 1.169  30-Oct-2020  skrll branches: 1.169.6;
Retire arm_[di]sb in favour of the isb() and dsb(sy) macro invocations.
 1.168  03-Jul-2020  skrll Consistency...#define<tab>
 1.167  18-Apr-2020  skrll PMAP_DEBUG has been deleted on arm
 1.166  29-Mar-2020  skrll branches: 1.166.2;
Don't define pt_entry_t if _LOCORE

Reported by Patrick Welche
 1.165  29-Mar-2020  skrll Provide a pt_entry_t and PRIxPTE
 1.164  14-Mar-2020  ad pmap_remove_all(): Return a boolean value to indicate the behaviour. If
true, all mappings have been removed, the pmap is totally cleared out, and
UVM can then avoid doing the work to call pmap_remove() for each map entry.
If false, either nothing has been done, or some helpful arch-specific voodoo
has taken place.
 1.163  24-Feb-2020  ad Adjust for UVM locking changes
 1.162  23-Feb-2020  skrll G/C l1pte_pgindex
 1.161  05-Feb-2020  skrll Fix the armv[67] memory attributes for uncached memory. Previously it was
mapped as strongly-ordered which meant that unaligned accesses would fault.

armv7_generic_bs_map now maps pages with PMAP_DEV which is treated as SO

bus_dma continues to use PMAP_NOCACHE as appropriate, but this now get
mapped to the correct memory attribute bits for armv[67]

DEVMAP_ENTRY usees a new flag PTE_DEV.

The workaround for the unaligned access faults is now removed.

XXX Other armv[67] boards bus_space implementations should be checked.
XXX There is scope to reduce the difference to aarch64
 1.160  20-Jan-2020  skrll s/_ARM_ARCH_6/ARM_MMU_EXTENDED/ in the #ifdef for the recent 4k pages
change
 1.159  18-Jan-2020  skrll Use 4K pages on ARM_MMU_EXTENDED platforms (all armv[67] except RPI) by
creating a new pool l1ttpl for the userland L1 translation table which
needs to be 8KB and 8KB aligned.

Limit the pool to maxproc and add hooks to allow the sysctl changing of
maxproc to adjust the pool.

This comes at a 5% performance penalty for build.sh -j8 kernel on a
Tegra TK1.
 1.158  12-Jan-2020  christos fix -Wsign-compare because module tests trigger it.
 1.157  10-Dec-2019  ad branches: 1.157.2;
pg->phys_addr -> VM_PAGE_TO_PHYS(pg)
 1.156  18-Oct-2018  skrll branches: 1.156.4;
Provide generic start code that assumes the MMU is off and caches are
disabled as per the linux booting protocol for ARMv6 and ARMv7 boards.
u-boot image type should be changed to 'linux' for correct behaviour.

The new start code builds a minimal "bootstrap" L1PT with cached access
disabled and uses the same table for all processors. AP startup is
performed in less steps and more code is written in C.

The bootstrap tables and stack are placed into an (orphaned) section
"_init_memory" which is given to uvm when it is no longer used.

Various kernels have been converted to use this code and tested. Some
boards were provided by TNF. Thanks!

The GENERIC kernel now boots on boards using the TEGRA, SUNXI and EXYNOS
kernels. The GENERIC kernel will also work on RPI2 using u-boot.

Thanks to martin@ and aymeric@ for testing on parallella and nanosoc
respectively
 1.155  01-Apr-2018  ryo branches: 1.155.2;
Add initial support for ARMv8 (AARCH64) (by nisimura@ and ryo@)

- sys/arch/evbarm64 is gone and integrated into sys/arch/evbarm. (by skrll@)
- add support fdt. evbarm/conf/GENERIC64 fdt (bcm2837,sunxi,tegra) based generic 64bit kernel config. (by skrll@, jmcneill@)
 1.154  24-Jan-2018  skrll branches: 1.154.2;
Remove port-acorn26

OK core@
 1.153  22-Oct-2017  skrll Centralise defines for DEVMAP_{ALIGN,SIZE,ENTRY,ENTRY_END}
 1.152  29-Aug-2017  skrll Revert the *_PROT_RO_* define changes and do all the work in the *_PROT()
macros for RO kernel pages.

cats boots again - no idea how it slipped through my testing previously
 1.151  11-Jul-2017  skrll Fix up L{1_S,2_L,2_S}_PROT for recent changes to the
L{1_S,2_L,2_S}_PROT_RO* values.
 1.150  06-Jul-2017  skrll KNF two comments
 1.149  06-Jul-2017  skrll Re-define the L*_PROT_RO for MMUs that don't really support RO mapping
and adjust l2pte_set_{writeable,readony} to the new values.

This allows RO mappings for MMUs that actually support them.
 1.148  06-Jul-2017  skrll Trailing whitespace
 1.147  25-May-2017  skrll Use the define name PMAP_HWPAGEWALKER and not PMAP_TLB_HWPAGEWALKER
 1.146  25-May-2017  skrll Spell ARM_MMU_EXTENDED correctly
 1.145  23-Feb-2017  skrll Fixup the compile time decisions around PMAP_{INCLUDE,NEEDS}_PTE_SYNC and
fix the options for xscale boards which require the code in
pmap_l2ptp_ctor marked as #ifndef PMAP_INCLUDE_PTE_SYNC.

Fix the typo (pte -> opte) in this code block and consistently use opte
elsewhere.

PR/51990: Regression data_abort_handler: data_aborts fsr=0x406 far=0xbfffeff5 on copyout in init
 1.144  14-Jul-2016  skrll branches: 1.144.2; 1.144.4;
Spell PMAP_TLB_NEED_SHOOTDOWN correctly
 1.143  11-Nov-2015  skrll Support pmap_pv_track and friends
 1.142  09-Sep-2015  skrll Make L2_S_CACHE_MASK_armv6n consistent with other *_CACHE_MASK_armv6n
 1.141  01-Jun-2015  matt pmap_directbase is a failed experiment, nuke it.
 1.140  30-May-2015  matt Support directmapped systems with >1GB that start memory at 0x80000000.
 1.139  12-May-2015  skrll Add some KASSERTs to catch similar bugs to the cnptes/nptes one
 1.138  25-Feb-2015  joerg Improve inline asm around dsb/dmb/isb:
- always use volatile and mark them as memory barrier
- use the common version from locore.h in all places not included from
userland
 1.137  08-Nov-2014  skrll branches: 1.137.2;
Whitespace
 1.136  29-Oct-2014  skrll Sprinkle #include "opt_multiprocessor.h"
 1.135  31-Jul-2014  skrll branches: 1.135.2;
Trailing whitespace
 1.134  27-Jul-2014  skrll More fixes as a step towards ARM_MMU_EXTENDED on RPI.

- don't set CPU_CONTROL_SYST_ENABLE in arm11x6_setup for ARM_MMU_EXTENDED

- Use the new MMU defines for V6N

- pull in arm/cpuconf.h in vmparam s that VM_MAXUSER_ADDRESS gets set
correctly.
 1.133  15-Jun-2014  ozaki-r Fix macro name; PMAP_TLB_NEED_SHOOTDOWN => PMAP_NEED_TLB_SHOOTDOWN
 1.132  16-Apr-2014  matt Make to flush the secondary cache when syncing PTEs when the Sheeva L2 cache
is used.
 1.131  11-Apr-2014  matt Add a kernel for the CUBIETRUCK (CUBIEBOARD3). Allow direct mapping of all
memory (but for now allow the memory mapped above KERNEL_BASE to used for
poolpages).
 1.130  04-Apr-2014  matt branches: 1.130.2;
For ARM_MMU_V6C enable supersections
 1.129  31-Mar-2014  skrll Deal with large page mappings in l2pte_set.

Now the RPI can get passed setting the new TTB.

ok matt@
 1.128  31-Mar-2014  matt For ARM_MMU_EXTENDED, a KERNEL_BASE >= 0x80000000 is ok but a
VM_USER_MAXADDRESS can not be more than 0x80000000 - PAGE_SIZE.
 1.127  31-Mar-2014  matt Add a missing 0 to an #error
 1.126  30-Mar-2014  matt Make the ARM pmap use ASIDs, split TTBRs, and MP safe. This only happens for
ARMv6 or later CPUs. This means that on context switch that the TLBs and
caches no longer to cleaned/flushed. Also, eXecute Never (XN) protection has
been added so non-exec pages can not be run. Change the page size for ARMv6+
to be 8KB while allows a L1PT to be a normal page. This means that the L1PT
is not special. Use the XN support to only sync pages that are executed from.
 1.125  26-Feb-2014  matt Remove duplicate PMAP_PTE
 1.124  26-Feb-2014  matt Replace 1000 with PAGE_SIZE
 1.123  26-Feb-2014  matt Add PMAP_PTE flag. (map page so it can be used as a PDE or PTE page)
 1.122  18-Aug-2013  matt struct pcb; for a function prototype.
 1.121  03-Jul-2013  matt Add l2pte_set and l2pte_reset inlines to set/reset a pte. These will be
used to support > 4KB pages sizes.
Don't use >> L1_S_SHIFT, use L1_IDX() instead.
 1.120  12-Jun-2013  matt branches: 1.120.2;
Add a ARM_HAS_VBAR option which forces the use of the VBAR register. This
allows much code to deal with vector_page mappings to be eliminated. On a
BEAGLEBONE kernel, this saves 8KB of text and instructions that never have
to be executed. (The PJ4B has VBAR but doesn't implement the security
extensions it is part of so a method was needed to allow it use VBAR with
relying on the default test for the security extensions.)
 1.119  12-Dec-2012  matt Protect more definitions with #ifndef _LOCORE
 1.118  12-Dec-2012  matt Enable direct-mapped poolpages if __HAVE_MM_MD_DIRECT_MAPPED_PHYS is defined.
 1.117  10-Dec-2012  matt Add b{zero,copy}_page{,_vfp} and physical_end
 1.116  10-Dec-2012  matt Add pmap_{copy,zero}_page_vfp
 1.115  12-Nov-2012  skrll C99 types
 1.114  17-Oct-2012  matt Add PMAP_MAP_POOLPAGE / PMAP_UNMAP_POOLPAGE if PMAP_NEED_ALLOC_POOLPAGE is
defined.
 1.113  17-Oct-2012  matt Add a PMAP_NEEDS_ALLOC_POOLPAGE / PMAP_ALLOC_POOLPAGE hook so systems can
allocate pool pages from a specific VM freelist.
 1.112  22-Sep-2012  matt Don't use an asm in pmap_activate to update the TTBR, use cpu_setttb instead
but add a second argument to it to indicate whether the TLB/caches need to be
flushed. Default cortex to pmap_needs_fixup = 1. But check the MMFR3 field
to see if the fixed can be skipped.
Use a cf_flag bit 0 to indicate whether the A9 L2 cache should disable (bit 0 = 1)
or enabeld (bit = 0).

With these changes, the A9 MMU can use traverse caches to do MMU tablewalks
Also, make sure all memory has the shareable bit for the A9.
 1.111  11-Sep-2012  matt branches: 1.111.2;
Fix the CACHE_MASKs for armv6 to include TEX and S bits.
Fix a comment in pte.h
 1.110  07-Sep-2012  matt Switch cortex_a9 back to need_ptesync = 1
Add code to disable the L2 cache on cortex-a9 (for now).
Add evcnt for all the fault types.
Move cache info in a structure and have one for the pcache and one for scache.
Probe L1/L2 caches properly for ARMv7
 1.109  06-Sep-2012  matt Alas, Cortex-A8 can't TLB walk out of their caches so they need to sync each PTE.
 1.108  06-Sep-2012  matt Enable "shareable" access to the page table for armv7. PTE_SYNC only does
a DSB now on an armv7 cpu and no longer needs to flush the cache line to ram.
 1.107  02-Sep-2012  matt Make bus_dma understand supersections.
 1.106  01-Sep-2012  martin Backout previous, Matt fixed it differently
 1.105  01-Sep-2012  martin Move struct pv_addr next to struct bootmem_info into machdep.h and have
pmap.h include that.
Seems to be the least intrusive build fix; Matt: feel free to revamp.
 1.104  30-Aug-2012  matt Add a l1pte_supersection_p macro.
 1.103  20-Aug-2012  matt Add support for mapping SuperSection on armv6 and armv7. These always
a domain of 0 so move the kernel from domain 15 to domain 0.
 1.102  29-Jul-2012  matt Fix more -fno-common fallout.
Move more variables to common locations.
 1.101  28-Jan-2012  matt branches: 1.101.4;
Nuke the simplelock from vm_page_md
 1.100  12-Jun-2011  rmind branches: 1.100.2; 1.100.6;
Welcome to 5.99.53! Merge rmind-uvmplock branch:

- Reorganize locking in UVM and provide extra serialisation for pmap(9).
New lock order: [vmpage-owner-lock] -> pmap-lock.

- Simplify locking in some pmap(9) modules by removing P->V locking.

- Use lock object on vmobjlock (and thus vnode_t::v_interlock) to share
the locks amongst UVM objects where necessary (tmpfs, layerfs, unionfs).

- Rewrite and optimise x86 TLB shootdown code, make it simpler and cleaner.
Add TLBSTATS option for x86 to collect statistics about TLB shootdowns.

- Unify /dev/mem et al in MI code and provide required locking (removes
kernel-lock on some ports). Also, avoid cache-aliasing issues.

Thanks to Andrew Doran and Joerg Sonnenberger, as their initial patches
formed the core changes of this branch.
 1.99  10-Mar-2011  bsh branches: 1.99.2;
Preliminary ARM11 MPCore support.

I have confirmed this commit doesn't affect existing evbarm kernels by
comparing binaries.
 1.98  28-Feb-2011  macallan implement arm32_pmap_flags() to allow mappings with write buffering enabled,
mostly for video memory
Tested on shark
 1.97  14-Nov-2010  uebayasi branches: 1.97.2; 1.97.4;
Move struct vm_page_md definition from vmparam.h to pmap.h, because
it's used only by pmap. vmparam.h has definitions for wider
audience.

All GENERIC kernels build tested, except ia64.

powerpc/include/booke/vmparam.h has one too, but it has no pmap.h,
so it's left as is.
 1.96  02-Nov-2010  uebayasi Fix build of evbarm.
 1.95  16-Jun-2010  jmcneill PR port-arm/43299: Support added for igepv2/cortexa8/omap3530

Apply patch from PR, with build fixes. ok skrll, matt
 1.94  27-Dec-2009  uebayasi branches: 1.94.2; 1.94.4;
Add write-through cache work-around for ARM11 as well as ARM9/ARM10. Analyzed
& tested on i.MX35 with help from Tsubai Masanari.
 1.93  22-Oct-2009  rmind Simplify pmap_remove() a little by avoiding pmap_do_remove() layer, since
possibility to skip wired mappings is not needed anymore. Apart from that,
no functional differences are intended.
 1.92  19-Aug-2009  thorpej Use PMAP_ENABLE_PMAP_KMPAGE to enable PMAP_KMPAGE. We still want the bit
defined in the MI space, not in an MD header.
 1.91  19-Aug-2009  thorpej Rationalize the definition of PMAP_KMPAGE.
 1.90  30-Dec-2008  matt Reclaim PVF_KNC in VIPT to be PVF_MULTCLR (page has multiple colors).
Track when a page is mapping in multiple colors and deal with the ramifications.
When a page's MOD attribute is cleared, clean it from the cache.
Fix a logic inversion.

With these changes, the TI SDP2420 H4 board can successfully natively build a
TISDP2420 kernel.
 1.89  09-Dec-2008  pooka Make pmap_kernel() a MI macro for struct pmap *kernel_pmap_ptr,
which is now the "API" provided by the pmap module. pmap_kernel()
remains as the syntactic sugar.

Bonus cosmetics round: move all the pmap_t pointer typedefs into
uvm_pmap.h.

Thanks to Greg Oster for providing cpu muscle for doing test builds.
 1.88  13-Aug-2008  matt branches: 1.88.2; 1.88.10;
Fix a few more corner cases. Always KMPAGE or pages with unmanaged writeable
kernel mappings as modified. Only ever set DIRTY bit is DMOD is true and
NC is false. Don't modify unmanaged mappings in pmap_clearbit.
 1.87  21-Jul-2008  matt Add PMAP_KMPAGE defintion (forgotten commit). Also add PVF_DIRTY which will
be used by an update pmap.c shortly (to note what pages may have dirty
cache lines).
 1.86  16-Jul-2008  matt Revamp bookkeeping for pages entered by pmap_kenter_pa. Keep track of them
on pvlists so that the cacheability can be properly tracked.
 1.85  27-Apr-2008  matt branches: 1.85.2; 1.85.4; 1.85.6;
Merge kernel changes in matt-armv6 to HEAD.
 1.84  01-Jan-2008  chris branches: 1.84.6; 1.84.8; 1.84.10;
Add support for kcore headers to arm32 kernel core dumps.

The kcore code is based on i386's kcore header handling.

Having an asm stub for dumpsys, to dump the registers onto the stack, and
then call the C code to do the memory dump is based on amd64's core dump
code.

This allows a successful core dump on cats.

Part of fixing PR cats/18026.
 1.83  17-Oct-2007  garbled branches: 1.83.2; 1.83.8;
Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.
 1.82  15-Sep-2007  scw ARM cpu_switchto() has been partially broken since yamt-idlelwp was merged
as its cache/tlb management smarts relied too heavily on pre-merge context-
switch behaviour. See PR kern/36548 for one manifestation of the breakage.

To address this:
- Ditch the shadow pmap variables in the PCB (pagedir, l1vec, dacr, cstate)
as it was too easy for them to get out of sync with the pmap.
- Re-write (and fix) the convoluted cpuswitch.S cache/tlb ASM code in C.
It's only slightly less efficient, but is much more readable/maintainable.
- Document cpufuncs.cf_context_switch() as being C-callable.
- pmap_activate() becomes a no-op if the lwp's vmspace is already active.
(Good performance win, since pmap_activate() is now invoked on every
context-switch, even though ARM's cpu_switchto() already does all the
grunt work)

XXX: Some CPU-specific armXX_context_switch() implementations (arm67,
arm7tdmi, arm8) always flush the I+D caches. This should not be necessary.
Someone with access to hardware (acorn32?) needs to deal with this.
 1.81  22-Feb-2007  thorpej branches: 1.81.4; 1.81.12; 1.81.18; 1.81.20; 1.81.22; 1.81.24;
TRUE -> true, FALSE -> false
 1.80  21-Feb-2007  thorpej Replace the Mach-derived boolean_t type with the C99 bool type. A
future commit will replace use of TRUE and FALSE with true and false.
 1.79  24-Dec-2005  perry branches: 1.79.26; 1.79.30;
Remove leading __ from __(const|inline|signed|volatile) -- it is obsolete.
 1.78  10-Dec-2005  scw Implement pmap_collect() for arm32.
 1.77  13-Oct-2003  scw branches: 1.77.16;
On Xscale, define PMAP_UAREA() and use it to tweak uarea mappings so
they use the mini D$.

This results in a small performance boost on xscale platforms, since
flushing the main cache on a context switch won't affect the kernel
stack/pcb.
 1.76  06-Sep-2003  rearnsha Add support for ARM10 class processors.
 1.75  18-Jun-2003  bsh branches: 1.75.2;
protect with #ifndef _LOCORE so that assembler codes can share
definitions in this file such as PMAP_DOMAIN_KERNEL.
 1.74  15-Jun-2003  thorpej Add another devmap routine that allows bootstrap code to register
a devmap reflecting mappings that are created by really early
bootstrap code before pmap_devmap_bootstrap() is called.
 1.73  15-Jun-2003  thorpej Replace the ad-hoc "section mapping table" for static device mappings
with a more generic "devmap" structure that can also handle mappings
made with large and small pages. Add new pmap routines to enter these
mappings during bootstrap (and "remember" the devmap), and routines to
look up the static mappings once the kernel is running.
 1.72  21-May-2003  thorpej Remove #ifdefs supporting the old pmap, switching fully to the new.
 1.71  03-May-2003  thorpej Reduce differences between ARM32_NEW_VM_LAYOUT and not; always pass
the start and end of the kernel managed virtual address space to
pmap_bootstrap() in the new pmap.
 1.70  28-Apr-2003  scw Fix the bug reported by Richard Earnshaw in port-arm32/21349.

Make sure to check the access permissions before doing
ref/mod/domain fixups. This is particularly important
on machines with ARM_VECTORS_LOW.
 1.69  22-Apr-2003  thorpej Some ARM32_PMAP_NEW-related cleanup:
* Define a new "MMU type", ARM_MMU_SA1. While the SA-1's MMU is basically
compatible with the generic, the SA-1 cache does not have a write-through
mode, and it is useful to know have an indication of this.
* Add a new PMAP_NEEDS_PTE_SYNC indicator, and try to evaluate it at
compile time. We evaluate it like so:
- If SA-1-style MMU is the only type configured -> 1
- If SA-1-style MMU is not configured -> 0
- Otherwise, defer to a run-time variable.
If PMAP_NEEDS_PTE_SYNC might evaluate to true (SA-1 only or run-time
check), then we also define PMAP_INCLUDE_PTE_SYNC so that e.g. assembly
code can include the necessary run-time support. PMAP_INCLUDE_PTE_SYNC
largely replaces the ARM32_PMAP_NEEDS_PTE_SYNC manual setting Steve
included with the original new pmap.
* In the new pmap, make pmap_pte_init_generic() check to see if the CPU
has a write-back cache. If so, init the PT cache mode to C=1,B=0 to get
write-through mode. Otherwise, init the PT cache mode to C=1,B=1.
* Add a new pmap_pte_init_arm8(). Old pmap, same as generic. New pmap,
sets page table cacheability to 0 (ARM8 has a write-back cache, but
flushing it is quite expensive).
* In the new pmap, make pmap_pte_init_arm9() reset the PT cache mode to
C=1,B=0, since the write-back check in generic gets it wrong for ARM9,
since we use write-through mode all the time on ARM9 right now. (What
this really tells me is that the test for write-through cache is less
than perfect, but we can fix that later.)
* Add a new pmap_pte_init_sa1(). Old pmap, same as generic. New pmap,
does generic initialization, then resets page table cache mode to
C=1,B=1, since C=1,B=0 does not produce write-through on the SA-1.
 1.68  18-Apr-2003  thorpej Gah, fix *another* typo.
 1.67  18-Apr-2003  thorpej Oops, fix typo.
 1.66  18-Apr-2003  thorpej Define two new macros to test if a mapping is mappable with an L1 Section
mapping or an L2 Large Page mapping.
 1.65  18-Apr-2003  scw Add the generic arm32 bits of the new pmap, contributed by Wasabi Systems.

Some features of the new pmap are:

- It allows L1 descriptor tables to be shared efficiently between
multiple processes. A typical "maxusers 32" kernel, where NPROC is set
to 532, requires 35 L1s. A "maxusers 2" kernel runs quite happily
with just 4 L1s. This completely solves the problem of running out
of contiguous physical memory for allocating new L1s at runtime on a
busy system.

- Much improved cache/TLB management "smarts". This change ripples
out to encompass the low-level context switch code, which is also
much smarter about when to flush the cache/TLB, and when not to.

- Faster allocation of L2 page tables and associated metadata thanks,
in part, to the pool_cache enhancements recently contributed to
NetBSD by Wasabi Systems.

- Faster VM space teardown due to accurate referenced tracking of L2
page tables.

- Better/faster cache-alias tracking.

The new pmap is enabled by adding options ARM32_PMAP_NEW to the kernel
config file, and making the necessary changes to the port-specific
initarm() function. Several ports have already been converted and will
be committed shortly.
 1.64  09-Apr-2003  thorpej Add the ability for pool caches to cache the physical address of
objects. Clients of the pool_cache API must consistently use
the "paddr" variants or not, otherwise behavior is undefined.

Enable this on Alpha, ARM, MIPS, and x86. Other platforms must
define POOL_VTOPHYS() in the appropriate manner in order to enable
the feature.

Part 1 of a series of simple patches contributed by Wasabi Systems
to improve network performance.
 1.63  23-Mar-2003  chris Garbage collect pmap_map, the last (and only?) use has been removed.
 1.62  12-Nov-2002  chris Fix PTE_FLUSH_RANGE macro, it should have had a cnt parameter.
 1.61  22-Sep-2002  chs it really helps to get the stub right before cutting + pasting it 27 times.
alas, I did not. doh.
 1.60  22-Sep-2002  chs add pmap_remove_all() hook (empty on most platforms so far).
 1.59  24-Aug-2002  thorpej Define macros describing the 4M super-sections that our pmap
actually uses (since we allocate PT pages in 4K chunks, rather
than 1K chunks).
 1.58  24-Aug-2002  thorpej Enable caching on kernel and user page tables. This saves having
to do uncached memory access during VM operations (which can be
quite expensive on some CPUs).

We currently write-back PTEs as soon as they're modified; there is
some room for optimization (to write them back in larger chunks).
For PTEs in the APTE space (i.e. PTEs for pmaps that describe another
process's address space), PTEs must also be evicted from the cache
complete (PTEs in PTE space will be evicted durint a context switch).
 1.57  22-Aug-2002  thorpej * Add PTE_SYNC() and PTE_SYNC_RANGE() macros. These don't actually do
anything yet.
* Use PTE_SYNC() and PTE_SYNC_RANGE() in some obvious places, i.e.
where vtopte() is used.
 1.56  09-Aug-2002  thorpej Add a PVF_EXEC -- we don't use it yet, though.
 1.55  31-Jul-2002  thorpej Overhaul how DMA ranges work in the ARM bus_dma implementation.

A new "arm32_dma_range" structure now describes a DMA window, with
a system address base, bus address base, and length. In addition to
providing info about which memory regions are legal for DMA, the new
structure provides address translation support, as well.

As before, if a tag does not list any ranges, then all addresses are
considered valid, and no DMA address translation is performed.

This allows us to remove a large chunk of code which was duplicated and
tweaked slightly (to do the address translation) from the stock ARM
bus_dma in the XScale IOP and ARM Integrator ports.

Test compiled on all ARM platforms, test booted on Intel IQ80321 and Shark.
 1.54  31-Jul-2002  thorpej Move the calls to uvm_page_physload() out of pmap_bootstrap() and
into platform-specific initialization code, giving platform-specific
code control over which free list a given chunk of memory gets put
onto.

Changes are essentially mechanical. Test compiled for all ARM
platforms, test booted on Intel IQ80321 and Shark.

Discussed some time ago on port-arm.
 1.53  12-Apr-2002  thorpej branches: 1.53.2;
Default all XScale core processors to the read/write-allocate write-back
cache mode. Add a new XSCALE_CACHE_WRITE_THROUGH option for people who
are paranoid about the cache-related errata (you *do* have to line up
the planets correctly to trip them, but having the option is useful).
 1.52  12-Apr-2002  thorpej Centralize ARM CPU configuration information by adding a new header
file, <arm/cpuconf.h>, which pulls in "opt_cputypes.h" and then defines
the following:
* CPU_NTYPES -- now many CPU types are configured into the kernel. What
you really want to know is "== 1" or "> 1".
* Defines ARM_ARCH_2, ARM_ARCH_3, ARM_ARCH_4, ARM_ARCH_5, depending
on which ARM architecture versions are configured (based on CPU_*
options). Also defines ARM_NARCH to determins how many architecture
versions are configured.
* Defines ARM_MMU_MEMC, ARM_MMU_GENERIC, ARM_MMU_XSCALE depending on
which classes of ARM MMUs are configured into the kernel, and ARM_NMMUS
to determine how many MMU classes are configured.

Remove the needless inclusion of "opt_cputypes.h" in several places.
Convert remaining users to <arm/cpuconf.h>.
 1.51  10-Apr-2002  thorpej Add separate pmap_{zero,copy}_page() functions for generic ARM
vs. XScale. Use the mini-data cache for the destination on XScale,
thus saving tossing out 4K of possible-useful data from the main
data cache each time.

This significantly improves every test in lmbench.
 1.50  09-Apr-2002  thorpej * Move the code that cleans the XScale mini-data cache into its
own function.
* Add a new function which sets up the mini-data cache clean area
properly.
 1.49  09-Apr-2002  thorpej * Split pte_cache_mode into pte_l1_s_cache_mode, pte_l2_l_cache_mode,
and pte_l2_s_cache_mode. The cache-meaningful bits are different
for these descriptor types on some processor models.
* Add pte_*_cache_mask, corresponding to each above, which has a mask
of the cache-meangful bits, and define those for generic and XScale
MMU classes. Note, the L2_S_CACHE_MASK_xscale definition requires
use of the Extended Small Page L2 descriptor (the "X" bit overlaps
with AP bits otherwise).
 1.48  09-Apr-2002  thorpej Use the "Extended Small Page" L2 descriptor type on XScale (note
this means that there are no 1K sub-pages on XScale, but we don't
use them anyway).
 1.47  09-Apr-2002  thorpej Remove the implementation-defined bits from L1_S_PROTO_xscale and
L1_C_PROTO_xscale; while they are supposed to be set to 1 on generic
ARM MMUs (according to the SA-110 and ARM920T manuals), they are listed
as "should be zero" in the i80200 manual.
 1.46  09-Apr-2002  thorpej Define 2 classes of ARM MMUs:
1. Generic (compatible with ARM6)
1. XScale (can be used as generic, but also has certainly nifty extensions).

Define abstract PTE bit defintions for each MMU class. If only one MMU
class is configured into the kernel (based on CPU_* options), then we
get the constants for that MMU class. Otherwise we indirect through
varaibles set up via set_cpufuncs().

XXX The XScale bits are currently the same as the generic bits. Baby steps.
 1.45  09-Apr-2002  thorpej Use abstract names for the protection and PTE type bits in
L1 and L2 descriptors. This will allow us to support different
PTE layouts that enable the use of extensions on different
processor models.
 1.44  05-Apr-2002  thorpej * Rewrite the 32-bit ARM pte.h based on the ARM architecture manual.
Significant cleanup, here, including better PTE bit names.
* Add XScale PTE extensions (ECC enable, write-allocate cache mode).
* Mechanical changes everywhere else to update for new pte.h. While
doing this, two bugs (as a result of typos) were fixed in

arm/arm32/bus_dma.c
evbarm/integrator/int_bus_dma.c
 1.43  04-Apr-2002  thorpej Rename flags that are really part of the pv_entry/mdpage into
pmap.h and give them more descriptive names and better comments:
* PT_M -> PVF_MOD (page is modified)
* PT_H -> PVF_REF (page is referenced)
* PT_W -> PVF_WIRED (mapping is wired)
* PT_Wr -> PVF_WRITE (mapping is writable)
* PT_NC -> PVF_NC (mapping is non-cacheable; multiple mappings)
 1.42  03-Apr-2002  thorpej Clean up handling of the vector page on 32-bit ARM systems:
* Don't refer to VA 0, instead refer to a new variable: vector_page
* Delete the old zero_page_*() functions, replacing them with a new
one: vector_page_setprot().
* When manipulating vector page mappings in user pmaps, only do so if
the vector page is below KERNEL_BASE (if it's above KERNEL_BASE, the
vector page is mapped by the kernel pmap).
* Add a new function, arm32_vector_init(), which takes the virtual
address of the vector page (which MUST be valid when the function
is called) and a bitmask of vectors the kernel is going to take
over, and performs all vector page initialization, including setting
the V bit in the CPU Control register ("relocate vectors to high
address"), if necessary.
 1.41  25-Mar-2002  thorpej * Some cleanup.
* Delete the call to pmap_copy() in pmap.h
 1.40  25-Mar-2002  thorpej Move some private pmap data structures into pmap.c
 1.39  25-Mar-2002  thorpej Tidy a few things up.
 1.38  25-Mar-2002  thorpej Correct the comment describing the layout of the VM space. In
particular, don't describe a recursive PTE mapping, since the ARM
port doesn't (and can't) use one.
 1.37  24-Mar-2002  thorpej Remove exported pmap_pte() prototype.
 1.36  24-Mar-2002  thorpej Clean up PTE access macros a bit.
 1.35  24-Mar-2002  thorpej * arm_byte_to_page() -> arm_btop()
* arm_page_to_byte() -> arm_ptob()
 1.34  23-Mar-2002  thorpej Garbage-collect the "pagehook" stuff.
 1.33  23-Mar-2002  thorpej * Rename PROCESS_PAGE_TBLS_BASE -> PTE_BASE
* Rename ALT_PAGE_TBLS_BASE -> APTE_BASE
* Garbage-collect PAGE_TABLE_SPACE_START
 1.32  23-Mar-2002  thorpej Remove redundant #ifdef _KERNEL
 1.31  05-Mar-2002  thorpej * Make pmap_is_{modified,referenced}() macros in pmap.h that just
test the attributes in the vm_page_md directly.
* Clean up pmap_clear_{modified,referenced}().
* Delete now-unused pmap_testbit().
 1.30  05-Mar-2002  thorpej Switch back to using vm_page_md (thanks chuq for finding the bug
in the code that made it unstable before!)
 1.29  03-Mar-2002  chris Implement pmap_growkernel for arm32 based ports.
Note that this has been compiled on some systems, cats, IQ80310, IPAQ, netwinder and shark (note that shark's build is currently broken due to other reasons), but only actually run on cats.
Shark doesn't make use of the functionality as I believe there has to be a correlation between OFW and the kernel tables so that calls into OFW work.
 1.28  21-Feb-2002  thorpej Keep track of which kernel PTs are available during bootstrap,
and let pmap_map_chunk() lookup the correct one to use for the
current VA. Eliminate the "l2table" argument to pmap_map_chunk().

Add a second L2 table for mapping kernel text/data/bss on the
IQ80310 (fixes booting kernels with ramdisks).
 1.27  21-Feb-2002  thorpej map_chunk() -> pmap_map_chunk(), and move it to pmap.c
 1.26  20-Feb-2002  thorpej map_pagetable() -> pmap_link_l2pt(), and move it to pmap.c
 1.25  20-Feb-2002  thorpej Collapse map_entry{,ro,nc}() into a single pmap_map_entry() that
takes a prot and a "cacheable" indicator.
 1.24  20-Feb-2002  thorpej Rename map_section() to pmap_map_section(), move it to pmap.c, and give it
an extra argument (prot - specifies protection of the mapping).
 1.23  06-Feb-2002  thorpej Back out all the vm_page_md changes. They are causing some
mysterious problems (a similar change to the i386 pmap causes
mysterious problems there, as well), and the issue needs to
be investigated more.
 1.22  06-Feb-2002  thorpej Efficiency tweaks, some made possible by vm_page_md.
 1.21  05-Feb-2002  thorpej Use vm_page_md rather than pmap_physseg. Saves lots of cycles in
common operations.
 1.20  19-Jan-2002  chs add a new flag PMAP_CACHE_VIVT for the pmap to inform the MI code that
that the cache is virtually-indexed and virtually-tagged (such as on the ARM),
and use this flag in the UBC code to be more friendly to those caches.
 1.19  23-Nov-2001  thorpej Use <arm/cpufunc.h>, not <machine/cpufunc.h>.
 1.18  23-Nov-2001  thorpej - Move more contents of various <machine/vmparam.h> files into
<arm/arm32/vmparam.h> (mostly the stuff that's tied to the pmap
implementation).
- Since the MMU definitions in pte.h are specific to ARM processors
that support 32-bit mode, move pte.h to <arm/arm32/pte.h>.
- Make the Netwinder startup file build again (use PT_B|PT_C, rather
than PT_CACHEABLE, since the latter expands to a variable these days).
 1.17  19-Nov-2001  thorpej Implement pmap_update(). Currently it just calls cpu_cpwait(),
which ensures that TLB/cache operations have completed.
 1.16  03-Nov-2001  rearnsha branches: 1.16.2;
Define boolean predicates pmap_pde_page, pmap_pde_section & pmap_pde_fpage,
which return true if their pde argument is a coarse page, section or
fine page respectively.
 1.15  13-Sep-2001  chris branches: 1.15.2;
Sprinkle some static and inline into a couple of functions. Remove dead entries from pmap.h.
 1.14  10-Sep-2001  chris Update pmap_update to now take the updated pmap as an argument.
This will allow improvements to the pmaps so that they can more easily defer expensive operations, eg tlb/cache flush, til the last possible moment.

Currently this is a no-op on most platforms, so they should see no difference.

Reviewed by Jason.
 1.13  11-Aug-2001  chris branches: 1.13.2;
Checking a whole host of pmap changes:
Improved locking (not that we actually use it on a uniprocessor, but one day :)
Removed unneeded splvm's
tweaked pmap_clean_page code to only flush the cache if the page is mapped in the current pmap (based on diff from richard E)
Adopted pv entry allocation mechanism from i386.
Laid framework for returning ptp's when we've finished with them rather than holding onto them till the process exits.
ptp's are now allocated with a uvm object for the pmap, means that we can walk a list to free them off in pmap_release, until they get freed off by pmap_remove.

Also implemented a page zeroing function when the processor is idling. Note that hpcarm may wish to disable this.

I believe this code to be stable, if anyone has any problems please shout up.
 1.12  29-Jul-2001  chris Rework the pmap_release code to not have to walk the ptpt, it now uses a uvm_object to track the allocated vm_pages, this means it can free off the entries in the uvm_object.

Testing shows that it's about 5% faster on the make configure step for gmake.
 1.11  28-Jul-2001  chris A couple of tidy ups to pmap:
pmap_t -> struct pmap * in pmap.c and pmap.h
kernel_pmap -> pmap_kernel() everywhere.

Compiled and booted on riscpc and cats.
 1.10  22-Jun-2001  chris branches: 1.10.2;
GC a couple of unused entries in the pmap struct
 1.9  26-May-2001  chs replace vm_page_t with struct vm_page *.
 1.8  26-May-2001  chs replace {simple_,}lock{_data,}_t with struct {simple,}lock {,*}.
 1.7  22-Apr-2001  thorpej Undo a misguided previous change to the pmap_update() API.
 1.6  22-Apr-2001  thorpej Give pmap_update() an argument (a pmap_t) so that it knows which
pmap it should be updating.
 1.5  21-Apr-2001  thorpej Update the comment for pmap_update().
 1.4  04-Mar-2001  matt branches: 1.4.2; 1.4.4;
more vm_offset_t/vm_size_t -> {p,v}{addr,size}_t changes
move pmap_* declarations to pmap.h. fix conflicts this
exposed (e.g different definitions for pmap_bootstrap).
 1.3  04-Mar-2001  matt Convert some vm_size_t to vsize_t/psize_t. Change vaddr_t to paddr_t
where appropriate.
 1.2  04-Mar-2001  matt s/vm_offset_t/vaddr_t/g
 1.1  23-Feb-2001  reinoud Big patch for merging common include files of the new hpcarm tree and the old arm32
tree into the new arm substree. All moved files are relinked with a stub that included
the file from the new location; this might be done better later.
 1.4.4.3  23-Apr-2001  bouyer Sync with HEAD.
 1.4.4.2  12-Mar-2001  bouyer Sync with HEAD.
 1.4.4.1  04-Mar-2001  bouyer file pmap.h was added on branch thorpej_scsipi on 2001-03-12 13:27:25 +0000
 1.4.2.1  21-Jun-2001  nathanw Catch up to -current.
 1.10.2.9  10-Oct-2002  jdolecek sync kqueue with -current; this includes merge of gehenna-devsw branch,
merge of i386 MP branch, and part of autoconf rototil work
 1.10.2.8  06-Sep-2002  jdolecek sync kqueue branch with HEAD
 1.10.2.7  23-Jun-2002  jdolecek catch up with -current on kqueue branch
 1.10.2.6  16-Mar-2002  jdolecek Catch up with -current.
 1.10.2.5  11-Feb-2002  jdolecek Sync w/ -current.
 1.10.2.4  10-Jan-2002  thorpej Sync kqueue branch with -current.
 1.10.2.3  13-Sep-2001  thorpej Update the kqueue branch to HEAD.
 1.10.2.2  25-Aug-2001  thorpej Merge Aug 24 -current into the kqueue branch.
 1.10.2.1  03-Aug-2001  lukem update to -current
 1.13.2.1  01-Oct-2001  fvdl Catch up with -current.
 1.15.2.1  12-Nov-2001  thorpej Sync the thorpej-mips-cache branch with -current.
 1.16.2.9  11-Dec-2002  thorpej Sync with HEAD.
 1.16.2.8  18-Oct-2002  nathanw Catch up to -current.
 1.16.2.7  27-Aug-2002  thorpej Sync with -current.
 1.16.2.6  13-Aug-2002  nathanw Catch up to -current.
 1.16.2.5  17-Apr-2002  nathanw Catch up to -current.
 1.16.2.4  01-Apr-2002  nathanw Catch up to -current.
(CVS: It's not just a program. It's an adventure!)
 1.16.2.3  28-Feb-2002  nathanw Catch up to -current.
 1.16.2.2  08-Jan-2002  nathanw Catch up to -current.
 1.16.2.1  03-Nov-2001  nathanw file pmap.h was added on branch nathanw_sa on 2002-01-08 00:23:12 +0000
 1.53.2.1  30-Aug-2002  gehenna catch up with -current.
 1.75.2.4  11-Dec-2005  christos Sync with head.
 1.75.2.3  21-Sep-2004  skrll Fix the sync with head I botched.
 1.75.2.2  18-Sep-2004  skrll Sync with HEAD.
 1.75.2.1  03-Aug-2004  skrll Sync with HEAD
 1.77.16.4  21-Jan-2008  yamt sync with head
 1.77.16.3  27-Oct-2007  yamt sync with head.
 1.77.16.2  26-Feb-2007  yamt sync with head.
 1.77.16.1  21-Jun-2006  yamt sync with head.
 1.79.30.1  10-Nov-2007  matt Add AT91 support from Sami Kantoluoto
Add TI OMAP2430 support from Marty Fouts @ Danger Inc
 1.79.26.1  27-Feb-2007  yamt - sync with head.
- move sched_changepri back to kern_synch.c as it doesn't know PPQ anymore.
 1.81.24.5  09-Jan-2008  matt sync with HEAD
 1.81.24.4  09-Nov-2007  matt Add pmap_icache_sync_range and change arm32_sync_icache to use it.
This will only invalidate va that have valid PTEs. This avoids cleaning
unneeded cache lines.
 1.81.24.3  09-Nov-2007  matt Make all the evbarm kernels build again. Fix lossage from rebase.
 1.81.24.2  06-Nov-2007  matt sync with HEAD
 1.81.24.1  12-Oct-2007  matt Import TI OMAP 2430 and ARM11/ARMv6 support. Now on ARMv6, the cache is
no longer purged on context switches.
 1.81.22.1  01-Jan-2008  chris Sync with HEAD.
 1.81.20.1  02-Oct-2007  joerg Sync with HEAD.
 1.81.18.2  28-Feb-2008  rjs Sync with HEAD.
 1.81.18.1  01-Nov-2007  rjs Sync with HEAD.
 1.81.12.1  03-Oct-2007  garbled Sync with HEAD
 1.81.4.1  09-Oct-2007  ad Sync with head.
 1.83.8.1  02-Jan-2008  bouyer Sync with HEAD
 1.83.2.1  18-Feb-2008  mjf Sync with HEAD.
 1.84.10.6  11-Aug-2010  yamt sync with head.
 1.84.10.5  11-Mar-2010  yamt sync with head
 1.84.10.4  16-Sep-2009  yamt sync with head
 1.84.10.3  19-Aug-2009  yamt sync with head.
 1.84.10.2  04-May-2009  yamt sync with head.
 1.84.10.1  16-May-2008  yamt sync with head.
 1.84.8.1  18-May-2008  yamt sync with head.
 1.84.6.3  17-Jan-2009  mjf Sync with HEAD.
 1.84.6.2  28-Sep-2008  mjf Sync with HEAD.
 1.84.6.1  02-Jun-2008  mjf Sync with HEAD.
 1.85.6.2  13-Dec-2008  haad Update haad-dm branch to haad-dm-base2.
 1.85.6.1  19-Oct-2008  haad Sync with HEAD.
 1.85.4.2  28-Jul-2008  simonb Sync with head.
 1.85.4.1  18-Jul-2008  simonb Sync with head.
 1.85.2.1  18-Sep-2008  wrstuden Sync with wrstuden-revivesa-base-2.
 1.88.10.2  24-Mar-2014  matt Define PMAP_KMPAGE
 1.88.10.1  15-Feb-2014  matt Merge armv7 support from HEAD, specifically support for the BCM5301X
and BCM56340 evbarm kernels.
 1.88.2.1  19-Jan-2009  skrll Sync with HEAD.
 1.94.4.4  21-Apr-2011  rmind sync with head
 1.94.4.3  05-Mar-2011  rmind sync with head
 1.94.4.2  03-Jul-2010  rmind sync with head
 1.94.4.1  16-Mar-2010  rmind Change struct uvm_object::vmobjlock to be dynamically allocated with
mutex_obj_alloc(). It allows us to share the locks among UVM objects.
 1.94.2.4  15-Nov-2010  uebayasi Sync with HEAD.
 1.94.2.3  17-Aug-2010  uebayasi Sync with HEAD.
 1.94.2.2  25-Feb-2010  uebayasi A few more VM_PAGE_TO_MD().
 1.94.2.1  10-Feb-2010  uebayasi Missing bits of pmap_is_page_colored_p() conversion.
 1.97.4.1  05-Mar-2011  bouyer Sync with HEAD
 1.97.2.1  06-Jun-2011  jruoho Sync with HEAD.
 1.99.2.1  23-Jun-2011  cherry Catchup with rmind-uvmplock merge.
 1.100.6.1  18-Feb-2012  mrg merge to -current.
 1.100.2.4  22-May-2014  yamt sync with head.

for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.

this commit was splitted into small chunks to avoid
a limitation of cvs. ("Protocol error: too many arguments")
 1.100.2.3  16-Jan-2013  yamt sync with (a bit old) head
 1.100.2.2  30-Oct-2012  yamt sync with head
 1.100.2.1  17-Apr-2012  yamt sync with head
 1.101.4.2  07-Feb-2013  matt pullup pmap changes from HEAD
 1.101.4.1  28-Nov-2012  matt Merge improved arm support (especially Cortex) from HEAD
including OMAP and BCM53xx support.
 1.111.2.5  03-Dec-2017  jdolecek update from HEAD
 1.111.2.4  20-Aug-2014  tls Rebase to HEAD as of a few days ago.
 1.111.2.3  23-Jun-2013  tls resync from head
 1.111.2.2  25-Feb-2013  tls resync with head
 1.111.2.1  20-Nov-2012  tls Resync to 2012-11-19 00:00:00 UTC
 1.120.2.2  18-May-2014  rmind sync with head
 1.120.2.1  28-Aug-2013  rmind sync with head
 1.130.2.1  10-Aug-2014  tls Rebase.
 1.135.2.3  11-Mar-2017  snj Pull up following revision(s) (requested by skrll in ticket #1366):
sys/arch/arm/include/arm32/pmap.h: 1.145
sys/arch/arm/arm32/pmap.c: 1.343, 1.344
sys/arch/evbarm/gumstix/gumstix_machdep.c: 1.58 via patch
Fixup the compile time decisions around PMAP_{INCLUDE,NEEDS}_PTE_SYNC and
fix the options for xscale boards which require the code in
pmap_l2ptp_ctor marked as #ifndef PMAP_INCLUDE_PTE_SYNC.
Fix the typo (pte -> opte) in this code block and consistently use opte
elsewhere.
PR/51990: Regression data_abort_handler: data_aborts fsr=0x406 far=0xbfffeff5 on copyout in init
--
fix unused.
--
Set xscale_cache_clean_addr appropriately and re-arrange default KVA
layout to allow direct map for all boards.
OVERO/DUOVERO/PEPPER aren't tested.
PR/52010: Regression: Gumstix Verdex is hanging in enabling cache + KASSERT ram_size
 1.135.2.2  27-May-2015  msaitoh branches: 1.135.2.2.4;
Pull up following revision(s) (requested by skrll in ticket #805):
sys/arch/arm/include/arm32/pmap.h: revision 1.138
sys/arch/arm/arm/cpufunc.c: revision 1.151
sys/arch/arm/arm32/bus_dma.c: revision 1.90
sys/arch/arm/broadcom/bcm53xx_pax.c: revision 1.14
sys/arch/arm/arm32/bus_dma.c: revision 1.91
sys/arch/arm/samsung/exynos_space.c: revision 1.2
sys/arch/arm/arm32/db_machdep.c: revision 1.23
sys/arch/arm/allwinner/awin_space.c: revision 1.4
sys/arch/arm/include/rwlock.h: revision 1.9
sys/arch/arm/amlogic/amlogic_space.c: revision 1.2
sys/arch/arm/zynq/zynq_space.c: revision 1.2
sys/arch/arm/broadcom/bcm2835_space.c: revision 1.7
sys/arch/arm/arm32/pmap.c: revision 1.317
sys/arch/arm/include/locore.h: revision 1.19
sys/arch/arm/include/mutex.h: revision 1.20
sys/arch/arm/include/lock.h: revision 1.31
sys/arch/arm/include/lock.h: revision 1.32
sys/arch/arm/broadcom/bcmgen_space.c: revision 1.5
- Kill redundant semicolons.
- Indentation.
- Improve inline asm around dsb/dmb/isb:
- always use volatile and mark them as memory barrier
- use the common version from locore.h in all places not included from
userland
 1.135.2.1  09-Nov-2014  martin Pull up following revision(s) (requested by skrll in ticket #188):
sys/arch/arm/include/arm32/pmap.h: revision 1.136
sys/arch/arm/include/armreg.h: revision 1.100
sys/arch/arm/cortex/gic.c: revision 1.11
sys/arch/arm/arm32/db_interface.c: revision 1.54
sys/arch/arm/include/armreg.h: revision 1.101
sys/arch/arm/cortex/gic.c: revision 1.12
sys/arch/arm/arm32/arm32_machdep.c: revision 1.107
sys/arch/arm/arm/cpufunc_asm_armv7.S: revision 1.19
sys/arch/arm/cortex/a9_mpsubr.S: revision 1.20
sys/arch/evbarm/conf/BPI: revision 1.5
sys/arch/arm/cortex/a9_mpsubr.S: revision 1.21
sys/arch/arm/arm32/pmap.c: revision 1.306
sys/arch/arm/arm32/db_machdep.c: revision 1.22
sys/arch/arm/arm32/arm32_tlb.c: revision 1.3
sys/arch/arm/arm/undefined.c: revision 1.55
sys/arch/arm/cortex/a9_mpsubr.S: revision 1.22
sys/arch/arm/arm32/pmap.c: revision 1.307
sys/arch/arm/arm32/arm32_tlb.c: revision 1.4
sys/arch/arm/cortex/a9_mpsubr.S: revision 1.23
sys/arch/arm/arm32/arm32_tlb.c: revision 1.5
sys/arch/evbarm/conf/BPI: revision 1.8
sys/arch/arm/cortex/a9_mpsubr.S: revision 1.24
sys/arch/arm/arm32/arm32_tlb.c: revision 1.6
sys/arch/arm/arm32/arm32_tlb.c: revision 1.7
sys/arch/evbarm/conf/CUBIETRUCK: revision 1.5
sys/arch/arm/pic/pic.c: revision 1.23
sys/arch/arm/pic/pic.c: revision 1.24
sys/arch/arm/pic/picvar.h: revision 1.11
sys/arch/arm/arm/cpufunc_asm_armv7.S: revision 1.20
sys/arch/arm/mainbus/cpu_mainbus.c: revision 1.16
sys/arch/arm/arm32/pmap.c: revision 1.298
sys/arch/arm/arm/cpufunc_asm_arm11.S: revision 1.17
sys/arch/arm/arm/cpufunc_asm_pj4b.S: revision 1.5
sys/arch/arm/arm32/pmap.c: revision 1.310
sys/arch/arm/arm32/pmap.c: revision 1.311
sys/arch/arm/arm32/arm32_kvminit.c: revision 1.32
sys/arch/arm/cortex/a9_mpsubr.S: revision 1.19
sys/arch/arm/arm32/arm32_boot.c: revision 1.10
sys/arch/arm/arm/ast.c: revision 1.25
sys/arch/arm/include/armreg.h: revision 1.98
sys/uvm/pmap/pmap_tlb.c: revision 1.10
sys/arch/arm/arm32/arm32_boot.c: revision 1.8
sys/arch/arm/arm32/arm32_boot.c: revision 1.9
sys/arch/arm/arm/arm_machdep.c: revision 1.43
Various ARM MP fixes.
 1.135.2.2.4.1  13-Mar-2017  skrll Sync with netbsd-7-1-RELEASE
 1.137.2.6  28-Aug-2017  skrll Sync with HEAD
 1.137.2.5  05-Oct-2016  skrll Sync with HEAD
 1.137.2.4  27-Dec-2015  skrll Sync with HEAD (as of 26th Dec)
 1.137.2.3  22-Sep-2015  skrll Sync with HEAD
 1.137.2.2  06-Jun-2015  skrll Sync with HEAD
 1.137.2.1  06-Apr-2015  skrll Sync with HEAD
 1.144.4.1  21-Apr-2017  bouyer Sync with HEAD
 1.144.2.1  20-Mar-2017  pgoyette Sync with HEAD
 1.154.2.2  20-Oct-2018  pgoyette Sync with head
 1.154.2.1  07-Apr-2018  pgoyette Sync with HEAD. 77 conflicts resolved - all of them $NetBSD$
 1.155.2.3  21-Apr-2020  martin Sync with HEAD
 1.155.2.2  08-Apr-2020  martin Merge changes from current as of 20200406
 1.155.2.1  10-Jun-2019  christos Sync with HEAD
 1.156.4.1  27-Feb-2020  martin Pull up following revision(s) (requested by skrll in ticket #742):

sys/arch/arm/arm32/pmap.c: revision 1.388
sys/arch/arm/arm32/armv7_generic_space.c: revision 1.11
sys/arch/arm/arm/cpufunc.c: revision 1.176
sys/arch/arm/conf/Makefile.arm: revision 1.54 (via patch)
sys/arch/arm/include/arm32/pmap.h: revision 1.161

Fix the armv[67] memory attributes for uncached memory. Previously it was
mapped as strongly-ordered which meant that unaligned accesses would fault.
armv7_generic_bs_map now maps pages with PMAP_DEV which is treated as SO
bus_dma continues to use PMAP_NOCACHE as appropriate, but this now get
mapped to the correct memory attribute bits for armv[67]

DEVMAP_ENTRY usees a new flag PTE_DEV.

The workaround for the unaligned access faults is now removed.
XXX Other armv[67] boards bus_space implementations should be checked.
XXX There is scope to reduce the difference to aarch64
 1.157.2.3  29-Feb-2020  ad Sync with head.
 1.157.2.2  25-Jan-2020  ad Sync with head.
 1.157.2.1  17-Jan-2020  ad Sync with head.
 1.166.2.1  20-Apr-2020  bouyer Sync with HEAD
 1.169.6.1  13-May-2021  thorpej Sync with HEAD.
 1.173.4.1  14-Oct-2023  martin Pull up following revision(s) (requested by skrll in ticket #411):

sys/arch/evbarm/nslu2/nslu2_machdep.c: revision 1.41
sys/arch/evbarm/gumstix/gumstix_machdep.c: revision 1.75
sys/arch/evbarm/iq80321/iq80321_machdep.c: revision 1.66
sys/arch/iyonix/iyonix/iyonix_machdep.c: revision 1.34
sys/arch/zaurus/zaurus/machdep.c: revision 1.52
sys/arch/evbarm/g42xxeb/g42xxeb_machdep.c: revision 1.41
sys/arch/hpcarm/hpcarm/pxa2x0_hpc_machdep.c: revision 1.33
sys/arch/evbarm/iq80310/iq80310_machdep.c: revision 1.96
sys/arch/evbarm/adi_brh/brh_machdep.c: revision 1.53
sys/arch/arm/include/arm32/pmap.h: revision 1.177
sys/arch/evbarm/viper/viper_machdep.c: revision 1.34
sys/arch/evbarm/iyonix/iyonix_machdep.c: revision 1.5
sys/arch/evbarm/npwr_fc/npwr_fc_machdep.c: revision 1.30
sys/arch/evbarm/hdl_g/hdlg_machdep.c: revision 1.35
sys/arch/arm/arm32/pmap.c: revision 1.440
sys/arch/evbarm/lubbock/lubbock_machdep.c: revision 1.45
sys/arch/evbarm/ixdp425/ixdp425_machdep.c: revision 1.47

Fix non-DIAGNOSTIC builds

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