pmap.h revision 1.107
1 /* $NetBSD: pmap.h,v 1.107 2012/09/02 14:43:21 matt Exp $ */ 2 3 /* 4 * Copyright (c) 2002, 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe & Steve C. Woodford for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Copyright (c) 1994,1995 Mark Brinicombe. 40 * All rights reserved. 41 * 42 * Redistribution and use in source and binary forms, with or without 43 * modification, are permitted provided that the following conditions 44 * are met: 45 * 1. Redistributions of source code must retain the above copyright 46 * notice, this list of conditions and the following disclaimer. 47 * 2. Redistributions in binary form must reproduce the above copyright 48 * notice, this list of conditions and the following disclaimer in the 49 * documentation and/or other materials provided with the distribution. 50 * 3. All advertising materials mentioning features or use of this software 51 * must display the following acknowledgement: 52 * This product includes software developed by Mark Brinicombe 53 * 4. The name of the author may not be used to endorse or promote products 54 * derived from this software without specific prior written permission. 55 * 56 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 57 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 58 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 59 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 60 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 61 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 62 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 63 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 64 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 65 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 #ifndef _ARM32_PMAP_H_ 69 #define _ARM32_PMAP_H_ 70 71 #ifdef _KERNEL 72 73 #include <arm/cpuconf.h> 74 #include <arm/arm32/pte.h> 75 #ifndef _LOCORE 76 #if defined(_KERNEL_OPT) 77 #include "opt_arm32_pmap.h" 78 #endif 79 #include <arm/cpufunc.h> 80 #include <uvm/uvm_object.h> 81 #endif 82 83 /* 84 * a pmap describes a processes' 4GB virtual address space. this 85 * virtual address space can be broken up into 4096 1MB regions which 86 * are described by L1 PTEs in the L1 table. 87 * 88 * There is a line drawn at KERNEL_BASE. Everything below that line 89 * changes when the VM context is switched. Everything above that line 90 * is the same no matter which VM context is running. This is achieved 91 * by making the L1 PTEs for those slots above KERNEL_BASE reference 92 * kernel L2 tables. 93 * 94 * The basic layout of the virtual address space thus looks like this: 95 * 96 * 0xffffffff 97 * . 98 * . 99 * . 100 * KERNEL_BASE 101 * -------------------- 102 * . 103 * . 104 * . 105 * 0x00000000 106 */ 107 108 /* 109 * The number of L2 descriptor tables which can be tracked by an l2_dtable. 110 * A bucket size of 16 provides for 16MB of contiguous virtual address 111 * space per l2_dtable. Most processes will, therefore, require only two or 112 * three of these to map their whole working set. 113 */ 114 #define L2_BUCKET_LOG2 4 115 #define L2_BUCKET_SIZE (1 << L2_BUCKET_LOG2) 116 117 /* 118 * Given the above "L2-descriptors-per-l2_dtable" constant, the number 119 * of l2_dtable structures required to track all possible page descriptors 120 * mappable by an L1 translation table is given by the following constants: 121 */ 122 #define L2_LOG2 ((32 - L1_S_SHIFT) - L2_BUCKET_LOG2) 123 #define L2_SIZE (1 << L2_LOG2) 124 125 /* 126 * tell MI code that the cache is virtually-indexed. 127 * ARMv6 is physically-tagged but all others are virtually-tagged. 128 */ 129 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 130 #define PMAP_CACHE_VIPT 131 #else 132 #define PMAP_CACHE_VIVT 133 #endif 134 135 #ifndef _LOCORE 136 137 struct l1_ttable; 138 struct l2_dtable; 139 140 /* 141 * Track cache/tlb occupancy using the following structure 142 */ 143 union pmap_cache_state { 144 struct { 145 union { 146 u_int8_t csu_cache_b[2]; 147 u_int16_t csu_cache; 148 } cs_cache_u; 149 150 union { 151 u_int8_t csu_tlb_b[2]; 152 u_int16_t csu_tlb; 153 } cs_tlb_u; 154 } cs_s; 155 u_int32_t cs_all; 156 }; 157 #define cs_cache_id cs_s.cs_cache_u.csu_cache_b[0] 158 #define cs_cache_d cs_s.cs_cache_u.csu_cache_b[1] 159 #define cs_cache cs_s.cs_cache_u.csu_cache 160 #define cs_tlb_id cs_s.cs_tlb_u.csu_tlb_b[0] 161 #define cs_tlb_d cs_s.cs_tlb_u.csu_tlb_b[1] 162 #define cs_tlb cs_s.cs_tlb_u.csu_tlb 163 164 /* 165 * Assigned to cs_all to force cacheops to work for a particular pmap 166 */ 167 #define PMAP_CACHE_STATE_ALL 0xffffffffu 168 169 /* 170 * This structure is used by machine-dependent code to describe 171 * static mappings of devices, created at bootstrap time. 172 */ 173 struct pmap_devmap { 174 vaddr_t pd_va; /* virtual address */ 175 paddr_t pd_pa; /* physical address */ 176 psize_t pd_size; /* size of region */ 177 vm_prot_t pd_prot; /* protection code */ 178 int pd_cache; /* cache attributes */ 179 }; 180 181 /* 182 * The pmap structure itself 183 */ 184 struct pmap { 185 u_int8_t pm_domain; 186 bool pm_remove_all; 187 bool pm_activated; 188 struct l1_ttable *pm_l1; 189 pd_entry_t *pm_pl1vec; 190 pd_entry_t pm_l1vec; 191 union pmap_cache_state pm_cstate; 192 struct uvm_object pm_obj; 193 kmutex_t pm_obj_lock; 194 #define pm_lock pm_obj.vmobjlock 195 struct l2_dtable *pm_l2[L2_SIZE]; 196 struct pmap_statistics pm_stats; 197 LIST_ENTRY(pmap) pm_list; 198 }; 199 200 /* 201 * Physical / virtual address structure. In a number of places (particularly 202 * during bootstrapping) we need to keep track of the physical and virtual 203 * addresses of various pages 204 */ 205 typedef struct pv_addr { 206 SLIST_ENTRY(pv_addr) pv_list; 207 paddr_t pv_pa; 208 vaddr_t pv_va; 209 vsize_t pv_size; 210 uint8_t pv_cache; 211 uint8_t pv_prot; 212 } pv_addr_t; 213 typedef SLIST_HEAD(, pv_addr) pv_addrqh_t; 214 215 extern pv_addrqh_t pmap_freeq; 216 extern pv_addr_t kernelstack; 217 extern pv_addr_t abtstack; 218 extern pv_addr_t fiqstack; 219 extern pv_addr_t irqstack; 220 extern pv_addr_t undstack; 221 extern pv_addr_t idlestack; 222 extern pv_addr_t systempage; 223 extern pv_addr_t kernel_l1pt; 224 225 /* 226 * Determine various modes for PTEs (user vs. kernel, cacheable 227 * vs. non-cacheable). 228 */ 229 #define PTE_KERNEL 0 230 #define PTE_USER 1 231 #define PTE_NOCACHE 0 232 #define PTE_CACHE 1 233 #define PTE_PAGETABLE 2 234 235 /* 236 * Flags that indicate attributes of pages or mappings of pages. 237 * 238 * The PVF_MOD and PVF_REF flags are stored in the mdpage for each 239 * page. PVF_WIRED, PVF_WRITE, and PVF_NC are kept in individual 240 * pv_entry's for each page. They live in the same "namespace" so 241 * that we can clear multiple attributes at a time. 242 * 243 * Note the "non-cacheable" flag generally means the page has 244 * multiple mappings in a given address space. 245 */ 246 #define PVF_MOD 0x01 /* page is modified */ 247 #define PVF_REF 0x02 /* page is referenced */ 248 #define PVF_WIRED 0x04 /* mapping is wired */ 249 #define PVF_WRITE 0x08 /* mapping is writable */ 250 #define PVF_EXEC 0x10 /* mapping is executable */ 251 #ifdef PMAP_CACHE_VIVT 252 #define PVF_UNC 0x20 /* mapping is 'user' non-cacheable */ 253 #define PVF_KNC 0x40 /* mapping is 'kernel' non-cacheable */ 254 #define PVF_NC (PVF_UNC|PVF_KNC) 255 #endif 256 #ifdef PMAP_CACHE_VIPT 257 #define PVF_NC 0x20 /* mapping is 'kernel' non-cacheable */ 258 #define PVF_MULTCLR 0x40 /* mapping is multi-colored */ 259 #endif 260 #define PVF_COLORED 0x80 /* page has or had a color */ 261 #define PVF_KENTRY 0x0100 /* page entered via pmap_kenter_pa */ 262 #define PVF_KMPAGE 0x0200 /* page is used for kmem */ 263 #define PVF_DIRTY 0x0400 /* page may have dirty cache lines */ 264 #define PVF_KMOD 0x0800 /* unmanaged page is modified */ 265 #define PVF_KWRITE (PVF_KENTRY|PVF_WRITE) 266 #define PVF_DMOD (PVF_MOD|PVF_KMOD|PVF_KMPAGE) 267 268 /* 269 * Commonly referenced structures 270 */ 271 extern int pmap_debug_level; /* Only exists if PMAP_DEBUG */ 272 273 /* 274 * Macros that we need to export 275 */ 276 #define pmap_resident_count(pmap) ((pmap)->pm_stats.resident_count) 277 #define pmap_wired_count(pmap) ((pmap)->pm_stats.wired_count) 278 279 #define pmap_is_modified(pg) \ 280 (((pg)->mdpage.pvh_attrs & PVF_MOD) != 0) 281 #define pmap_is_referenced(pg) \ 282 (((pg)->mdpage.pvh_attrs & PVF_REF) != 0) 283 #define pmap_is_page_colored_p(md) \ 284 (((md)->pvh_attrs & PVF_COLORED) != 0) 285 286 #define pmap_copy(dp, sp, da, l, sa) /* nothing */ 287 288 #define pmap_phys_address(ppn) (arm_ptob((ppn))) 289 u_int arm32_mmap_flags(paddr_t); 290 #define ARM32_MMAP_WRITECOMBINE 0x40000000 291 #define ARM32_MMAP_CACHEABLE 0x20000000 292 #define pmap_mmap_flags(ppn) arm32_mmap_flags(ppn) 293 294 /* 295 * Functions that we need to export 296 */ 297 void pmap_procwr(struct proc *, vaddr_t, int); 298 void pmap_remove_all(pmap_t); 299 bool pmap_extract(pmap_t, vaddr_t, paddr_t *); 300 301 #define PMAP_NEED_PROCWR 302 #define PMAP_GROWKERNEL /* turn on pmap_growkernel interface */ 303 #define PMAP_ENABLE_PMAP_KMPAGE /* enable the PMAP_KMPAGE flag */ 304 305 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 306 #define PMAP_PREFER(hint, vap, sz, td) pmap_prefer((hint), (vap), (td)) 307 void pmap_prefer(vaddr_t, vaddr_t *, int); 308 #endif 309 310 void pmap_icache_sync_range(pmap_t, vaddr_t, vaddr_t); 311 312 /* Functions we use internally. */ 313 #ifdef PMAP_STEAL_MEMORY 314 void pmap_boot_pagealloc(psize_t, psize_t, psize_t, pv_addr_t *); 315 void pmap_boot_pageadd(pv_addr_t *); 316 vaddr_t pmap_steal_memory(vsize_t, vaddr_t *, vaddr_t *); 317 #endif 318 void pmap_bootstrap(vaddr_t, vaddr_t); 319 320 void pmap_do_remove(pmap_t, vaddr_t, vaddr_t, int); 321 int pmap_fault_fixup(pmap_t, vaddr_t, vm_prot_t, int); 322 bool pmap_get_pde_pte(pmap_t, vaddr_t, pd_entry_t **, pt_entry_t **); 323 bool pmap_get_pde(pmap_t, vaddr_t, pd_entry_t **); 324 void pmap_set_pcb_pagedir(pmap_t, struct pcb *); 325 326 void pmap_debug(int); 327 void pmap_postinit(void); 328 329 void vector_page_setprot(int); 330 331 const struct pmap_devmap *pmap_devmap_find_pa(paddr_t, psize_t); 332 const struct pmap_devmap *pmap_devmap_find_va(vaddr_t, vsize_t); 333 334 /* Bootstrapping routines. */ 335 void pmap_map_section(vaddr_t, vaddr_t, paddr_t, int, int); 336 void pmap_map_entry(vaddr_t, vaddr_t, paddr_t, int, int); 337 vsize_t pmap_map_chunk(vaddr_t, vaddr_t, paddr_t, vsize_t, int, int); 338 void pmap_link_l2pt(vaddr_t, vaddr_t, pv_addr_t *); 339 void pmap_devmap_bootstrap(vaddr_t, const struct pmap_devmap *); 340 void pmap_devmap_register(const struct pmap_devmap *); 341 342 /* 343 * Special page zero routine for use by the idle loop (no cache cleans). 344 */ 345 bool pmap_pageidlezero(paddr_t); 346 #define PMAP_PAGEIDLEZERO(pa) pmap_pageidlezero((pa)) 347 348 /* 349 * used by dumpsys to record the PA of the L1 table 350 */ 351 uint32_t pmap_kernel_L1_addr(void); 352 /* 353 * The current top of kernel VM 354 */ 355 extern vaddr_t pmap_curmaxkvaddr; 356 357 /* 358 * Useful macros and constants 359 */ 360 361 /* Virtual address to page table entry */ 362 static inline pt_entry_t * 363 vtopte(vaddr_t va) 364 { 365 pd_entry_t *pdep; 366 pt_entry_t *ptep; 367 368 if (pmap_get_pde_pte(pmap_kernel(), va, &pdep, &ptep) == false) 369 return (NULL); 370 return (ptep); 371 } 372 373 /* 374 * Virtual address to physical address 375 */ 376 static inline paddr_t 377 vtophys(vaddr_t va) 378 { 379 paddr_t pa; 380 381 if (pmap_extract(pmap_kernel(), va, &pa) == false) 382 return (0); /* XXXSCW: Panic? */ 383 384 return (pa); 385 } 386 387 /* 388 * The new pmap ensures that page-tables are always mapping Write-Thru. 389 * Thus, on some platforms we can run fast and loose and avoid syncing PTEs 390 * on every change. 391 * 392 * Unfortunately, not all CPUs have a write-through cache mode. So we 393 * define PMAP_NEEDS_PTE_SYNC for C code to conditionally do PTE syncs, 394 * and if there is the chance for PTE syncs to be needed, we define 395 * PMAP_INCLUDE_PTE_SYNC so e.g. assembly code can include (and run) 396 * the code. 397 */ 398 extern int pmap_needs_pte_sync; 399 #if defined(_KERNEL_OPT) 400 /* 401 * StrongARM SA-1 caches do not have a write-through mode. So, on these, 402 * we need to do PTE syncs. If only SA-1 is configured, then evaluate 403 * this at compile time. 404 */ 405 #if (ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7 != 0) && (ARM_NMMUS == 1) 406 #define PMAP_INCLUDE_PTE_SYNC 407 #if (ARM_MMU_V7 > 0) 408 #define PMAP_NEEDS_PTE_SYNC 1 409 #else 410 #define PMAP_NEEDS_PTE_SYNC 1 411 #endif 412 #elif (ARM_MMU_SA1 == 0) 413 #define PMAP_NEEDS_PTE_SYNC 0 414 #endif 415 #endif /* _KERNEL_OPT */ 416 417 /* 418 * Provide a fallback in case we were not able to determine it at 419 * compile-time. 420 */ 421 #ifndef PMAP_NEEDS_PTE_SYNC 422 #define PMAP_NEEDS_PTE_SYNC pmap_needs_pte_sync 423 #define PMAP_INCLUDE_PTE_SYNC 424 #endif 425 426 static inline void 427 pmap_ptesync(pt_entry_t *ptep, size_t cnt) 428 { 429 if (PMAP_NEEDS_PTE_SYNC) 430 cpu_dcache_wb_range((vaddr_t)ptep, cnt * sizeof(pt_entry_t)); 431 #if ARM_MMU_V7 > 0 432 __asm("dsb"); 433 #endif 434 } 435 436 #define PTE_SYNC(ptep) pmap_ptesync((ptep), 1) 437 #define PTE_SYNC_RANGE(ptep, cnt) pmap_ptesync((ptep), (cnt)) 438 439 #define l1pte_valid(pde) ((pde) != 0) 440 #define l1pte_section_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_S) 441 #define l1pte_supersection_p(pde) (l1pte_section_p(pde) \ 442 && ((pde) & L1_S_V6_SUPER) != 0) 443 #define l1pte_page_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_C) 444 #define l1pte_fpage_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_F) 445 446 #define l2pte_index(v) (((v) & L2_ADDR_BITS) >> L2_S_SHIFT) 447 #define l2pte_valid(pte) (((pte) & L2_TYPE_MASK) != L2_TYPE_INV) 448 #define l2pte_pa(pte) ((pte) & L2_S_FRAME) 449 #define l2pte_minidata(pte) (((pte) & \ 450 (L2_B | L2_C | L2_XS_T_TEX(TEX_XSCALE_X)))\ 451 == (L2_C | L2_XS_T_TEX(TEX_XSCALE_X))) 452 453 /* L1 and L2 page table macros */ 454 #define pmap_pde_v(pde) l1pte_valid(*(pde)) 455 #define pmap_pde_section(pde) l1pte_section_p(*(pde)) 456 #define pmap_pde_supersection(pde) l1pte_supersection_p(*(pde)) 457 #define pmap_pde_page(pde) l1pte_page_p(*(pde)) 458 #define pmap_pde_fpage(pde) l1pte_fpage_p(*(pde)) 459 460 #define pmap_pte_v(pte) l2pte_valid(*(pte)) 461 #define pmap_pte_pa(pte) l2pte_pa(*(pte)) 462 463 /* Size of the kernel part of the L1 page table */ 464 #define KERNEL_PD_SIZE \ 465 (L1_TABLE_SIZE - (KERNEL_BASE >> L1_S_SHIFT) * sizeof(pd_entry_t)) 466 467 /************************* ARM MMU configuration *****************************/ 468 469 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 470 void pmap_copy_page_generic(paddr_t, paddr_t); 471 void pmap_zero_page_generic(paddr_t); 472 473 void pmap_pte_init_generic(void); 474 #if defined(CPU_ARM8) 475 void pmap_pte_init_arm8(void); 476 #endif 477 #if defined(CPU_ARM9) 478 void pmap_pte_init_arm9(void); 479 #endif /* CPU_ARM9 */ 480 #if defined(CPU_ARM10) 481 void pmap_pte_init_arm10(void); 482 #endif /* CPU_ARM10 */ 483 #if defined(CPU_ARM11) /* ARM_MMU_V6 */ 484 void pmap_pte_init_arm11(void); 485 #endif /* CPU_ARM11 */ 486 #if defined(CPU_ARM11MPCORE) /* ARM_MMU_V6 */ 487 void pmap_pte_init_arm11mpcore(void); 488 #endif 489 #if ARM_MMU_V7 == 1 490 void pmap_pte_init_armv7(void); 491 #endif /* ARM_MMU_V7 */ 492 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */ 493 494 #if ARM_MMU_SA1 == 1 495 void pmap_pte_init_sa1(void); 496 #endif /* ARM_MMU_SA1 == 1 */ 497 498 #if ARM_MMU_XSCALE == 1 499 void pmap_copy_page_xscale(paddr_t, paddr_t); 500 void pmap_zero_page_xscale(paddr_t); 501 502 void pmap_pte_init_xscale(void); 503 504 void xscale_setup_minidata(vaddr_t, vaddr_t, paddr_t); 505 506 #define PMAP_UAREA(va) pmap_uarea(va) 507 void pmap_uarea(vaddr_t); 508 #endif /* ARM_MMU_XSCALE == 1 */ 509 510 extern pt_entry_t pte_l1_s_cache_mode; 511 extern pt_entry_t pte_l1_s_cache_mask; 512 513 extern pt_entry_t pte_l2_l_cache_mode; 514 extern pt_entry_t pte_l2_l_cache_mask; 515 516 extern pt_entry_t pte_l2_s_cache_mode; 517 extern pt_entry_t pte_l2_s_cache_mask; 518 519 extern pt_entry_t pte_l1_s_cache_mode_pt; 520 extern pt_entry_t pte_l2_l_cache_mode_pt; 521 extern pt_entry_t pte_l2_s_cache_mode_pt; 522 523 extern pt_entry_t pte_l1_s_wc_mode; 524 extern pt_entry_t pte_l2_l_wc_mode; 525 extern pt_entry_t pte_l2_s_wc_mode; 526 527 extern pt_entry_t pte_l1_s_prot_u; 528 extern pt_entry_t pte_l1_s_prot_w; 529 extern pt_entry_t pte_l1_s_prot_ro; 530 extern pt_entry_t pte_l1_s_prot_mask; 531 532 extern pt_entry_t pte_l2_s_prot_u; 533 extern pt_entry_t pte_l2_s_prot_w; 534 extern pt_entry_t pte_l2_s_prot_ro; 535 extern pt_entry_t pte_l2_s_prot_mask; 536 537 extern pt_entry_t pte_l2_l_prot_u; 538 extern pt_entry_t pte_l2_l_prot_w; 539 extern pt_entry_t pte_l2_l_prot_ro; 540 extern pt_entry_t pte_l2_l_prot_mask; 541 542 extern pt_entry_t pte_l1_ss_proto; 543 extern pt_entry_t pte_l1_s_proto; 544 extern pt_entry_t pte_l1_c_proto; 545 extern pt_entry_t pte_l2_s_proto; 546 547 extern void (*pmap_copy_page_func)(paddr_t, paddr_t); 548 extern void (*pmap_zero_page_func)(paddr_t); 549 550 #endif /* !_LOCORE */ 551 552 /*****************************************************************************/ 553 554 /* 555 * Definitions for MMU domains 556 */ 557 #define PMAP_DOMAINS 15 /* 15 'user' domains (1-15) */ 558 #define PMAP_DOMAIN_KERNEL 0 /* The kernel uses domain #0 */ 559 560 /* 561 * These macros define the various bit masks in the PTE. 562 * 563 * We use these macros since we use different bits on different processor 564 * models. 565 */ 566 #define L1_S_PROT_U_generic (L1_S_AP(AP_U)) 567 #define L1_S_PROT_W_generic (L1_S_AP(AP_W)) 568 #define L1_S_PROT_RO_generic (0) 569 #define L1_S_PROT_MASK_generic (L1_S_PROT_U|L1_S_PROT_W|L1_S_PROT_RO) 570 571 #define L1_S_PROT_U_xscale (L1_S_AP(AP_U)) 572 #define L1_S_PROT_W_xscale (L1_S_AP(AP_W)) 573 #define L1_S_PROT_RO_xscale (0) 574 #define L1_S_PROT_MASK_xscale (L1_S_PROT_U|L1_S_PROT_W|L1_S_PROT_RO) 575 576 #define L1_S_PROT_U_armv6 (L1_S_AP(AP_R) | L1_S_AP(AP_U)) 577 #define L1_S_PROT_W_armv6 (L1_S_AP(AP_W)) 578 #define L1_S_PROT_RO_armv6 (L1_S_AP(AP_R) | L1_S_AP(AP_RO)) 579 #define L1_S_PROT_MASK_armv6 (L1_S_PROT_U|L1_S_PROT_W|L1_S_PROT_RO) 580 581 #define L1_S_PROT_U_armv7 (L1_S_AP(AP_R) | L1_S_AP(AP_U)) 582 #define L1_S_PROT_W_armv7 (L1_S_AP(AP_W)) 583 #define L1_S_PROT_RO_armv7 (L1_S_AP(AP_R) | L1_S_AP(AP_RO)) 584 #define L1_S_PROT_MASK_armv7 (L1_S_PROT_U|L1_S_PROT_W|L1_S_PROT_RO) 585 586 #define L1_S_CACHE_MASK_generic (L1_S_B|L1_S_C) 587 #define L1_S_CACHE_MASK_xscale (L1_S_B|L1_S_C|L1_S_XS_TEX(TEX_XSCALE_X)) 588 #define L1_S_CACHE_MASK_armv6 (L1_S_B|L1_S_C|L1_S_XS_TEX(TEX_ARMV6_TEX)) 589 #define L1_S_CACHE_MASK_armv7 (L1_S_B|L1_S_C) 590 591 #define L2_L_PROT_U_generic (L2_AP(AP_U)) 592 #define L2_L_PROT_W_generic (L2_AP(AP_W)) 593 #define L2_L_PROT_RO_generic (0) 594 #define L2_L_PROT_MASK_generic (L2_L_PROT_U|L2_L_PROT_W|L2_L_PROT_RO) 595 596 #define L2_L_PROT_U_xscale (L2_AP(AP_U)) 597 #define L2_L_PROT_W_xscale (L2_AP(AP_W)) 598 #define L2_L_PROT_RO_xscale (0) 599 #define L2_L_PROT_MASK_xscale (L2_L_PROT_U|L2_L_PROT_W|L2_L_PROT_RO) 600 601 #define L2_L_PROT_U_armv6n (L2_AP0(AP_R) | L2_AP0(AP_U)) 602 #define L2_L_PROT_W_armv6n (L2_AP0(AP_W)) 603 #define L2_L_PROT_RO_armv6n (L2_AP0(AP_R) | L2_AP0(AP_RO)) 604 #define L2_L_PROT_MASK_armv6n (L2_L_PROT_U|L2_L_PROT_W|L2_L_PROT_RO) 605 606 #define L2_L_PROT_U_armv7 (L2_AP0(AP_R) | L2_AP0(AP_U)) 607 #define L2_L_PROT_W_armv7 (L2_AP0(AP_W)) 608 #define L2_L_PROT_RO_armv7 (L2_AP0(AP_R) | L2_AP0(AP_RO)) 609 #define L2_L_PROT_MASK_armv7 (L2_L_PROT_U|L2_L_PROT_W|L2_L_PROT_RO) 610 611 #define L2_L_CACHE_MASK_generic (L2_B|L2_C) 612 #define L2_L_CACHE_MASK_xscale (L2_B|L2_C|L2_XS_L_TEX(TEX_XSCALE_X)) 613 #define L2_L_CACHE_MASK_armv6 (L2_B|L2_C|L2_V6_L_TEX(TEX_ARMV6_TEX)) 614 #define L2_L_CACHE_MASK_armv7 (L2_B|L2_C) 615 616 #define L2_S_PROT_U_generic (L2_AP(AP_U)) 617 #define L2_S_PROT_W_generic (L2_AP(AP_W)) 618 #define L2_S_PROT_RO_generic (0) 619 #define L2_S_PROT_MASK_generic (L2_S_PROT_U|L2_S_PROT_W|L2_S_PROT_RO) 620 621 #define L2_S_PROT_U_xscale (L2_AP0(AP_U)) 622 #define L2_S_PROT_W_xscale (L2_AP0(AP_W)) 623 #define L2_S_PROT_RO_xscale (0) 624 #define L2_S_PROT_MASK_xscale (L2_S_PROT_U|L2_S_PROT_W|L2_S_PROT_RO) 625 626 #define L2_S_PROT_U_armv6n (L2_AP0(AP_R) | L2_AP0(AP_U)) 627 #define L2_S_PROT_W_armv6n (L2_AP0(AP_W)) 628 #define L2_S_PROT_RO_armv6n (L2_AP0(AP_R) | L2_AP0(AP_RO)) 629 #define L2_S_PROT_MASK_armv6n (L2_S_PROT_U|L2_S_PROT_W|L2_S_PROT_RO) 630 631 #define L2_S_PROT_U_armv7 (L2_AP0(AP_R) | L2_AP0(AP_U)) 632 #define L2_S_PROT_W_armv7 (L2_AP0(AP_W)) 633 #define L2_S_PROT_RO_armv7 (L2_AP0(AP_R) | L2_AP0(AP_RO)) 634 #define L2_S_PROT_MASK_armv7 (L2_S_PROT_U|L2_S_PROT_W|L2_S_PROT_RO) 635 636 #define L2_S_CACHE_MASK_generic (L2_B|L2_C) 637 #define L2_S_CACHE_MASK_xscale (L2_B|L2_C|L2_XS_T_TEX(TEX_XSCALE_X)) 638 #define L2_XS_CACHE_MASK_armv6 (L2_B|L2_C|L2_V6_XS_TEX(TEX_ARMV6_TEX)) 639 #define L2_S_CACHE_MASK_armv6n L2_XS_CACHE_MASK_armv6 640 #ifdef ARMV6_EXTENDED_SMALL_PAGE 641 #define L2_S_CACHE_MASK_armv6c L2_XS_CACHE_MASK_armv6 642 #else 643 #define L2_S_CACHE_MASK_armv6c L2_S_CACHE_MASK_generic 644 #endif 645 #define L2_S_CACHE_MASK_armv7 (L2_B|L2_C) 646 647 648 #define L1_S_PROTO_generic (L1_TYPE_S | L1_S_IMP) 649 #define L1_S_PROTO_xscale (L1_TYPE_S) 650 #define L1_S_PROTO_armv6 (L1_TYPE_S) 651 #define L1_S_PROTO_armv7 (L1_TYPE_S) 652 653 #define L1_SS_PROTO_generic 0 654 #define L1_SS_PROTO_xscale 0 655 #define L1_SS_PROTO_armv6 (L1_TYPE_S | L1_S_V6_SS) 656 #define L1_SS_PROTO_armv7 (L1_TYPE_S | L1_S_V6_SS) 657 658 #define L1_C_PROTO_generic (L1_TYPE_C | L1_C_IMP2) 659 #define L1_C_PROTO_xscale (L1_TYPE_C) 660 #define L1_C_PROTO_armv6 (L1_TYPE_C) 661 #define L1_C_PROTO_armv7 (L1_TYPE_C) 662 663 #define L2_L_PROTO (L2_TYPE_L) 664 665 #define L2_S_PROTO_generic (L2_TYPE_S) 666 #define L2_S_PROTO_xscale (L2_TYPE_XS) 667 #ifdef ARMV6_EXTENDED_SMALL_PAGE 668 #define L2_S_PROTO_armv6c (L2_TYPE_XS) /* XP=0, extended small page */ 669 #else 670 #define L2_S_PROTO_armv6c (L2_TYPE_S) /* XP=0, subpage APs */ 671 #endif 672 #define L2_S_PROTO_armv6n (L2_TYPE_S) /* with XP=1 */ 673 #define L2_S_PROTO_armv7 (L2_TYPE_S) 674 675 /* 676 * User-visible names for the ones that vary with MMU class. 677 */ 678 679 #if ARM_NMMUS > 1 680 /* More than one MMU class configured; use variables. */ 681 #define L1_S_PROT_U pte_l1_s_prot_u 682 #define L1_S_PROT_W pte_l1_s_prot_w 683 #define L1_S_PROT_RO pte_l1_s_prot_ro 684 #define L1_S_PROT_MASK pte_l1_s_prot_mask 685 686 #define L2_S_PROT_U pte_l2_s_prot_u 687 #define L2_S_PROT_W pte_l2_s_prot_w 688 #define L2_S_PROT_RO pte_l2_s_prot_ro 689 #define L2_S_PROT_MASK pte_l2_s_prot_mask 690 691 #define L2_L_PROT_U pte_l2_l_prot_u 692 #define L2_L_PROT_W pte_l2_l_prot_w 693 #define L2_L_PROT_RO pte_l2_l_prot_ro 694 #define L2_L_PROT_MASK pte_l2_l_prot_mask 695 696 #define L1_S_CACHE_MASK pte_l1_s_cache_mask 697 #define L2_L_CACHE_MASK pte_l2_l_cache_mask 698 #define L2_S_CACHE_MASK pte_l2_s_cache_mask 699 700 #define L1_SS_PROTO pte_l1_ss_proto 701 #define L1_S_PROTO pte_l1_s_proto 702 #define L1_C_PROTO pte_l1_c_proto 703 #define L2_S_PROTO pte_l2_s_proto 704 705 #define pmap_copy_page(s, d) (*pmap_copy_page_func)((s), (d)) 706 #define pmap_zero_page(d) (*pmap_zero_page_func)((d)) 707 #elif (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 708 #define L1_S_PROT_U L1_S_PROT_U_generic 709 #define L1_S_PROT_W L1_S_PROT_W_generic 710 #define L1_S_PROT_RO L1_S_PROT_RO_generic 711 #define L1_S_PROT_MASK L1_S_PROT_MASK_generic 712 713 #define L2_S_PROT_U L2_S_PROT_U_generic 714 #define L2_S_PROT_W L2_S_PROT_W_generic 715 #define L2_S_PROT_RO L2_S_PROT_RO_generic 716 #define L2_S_PROT_MASK L2_S_PROT_MASK_generic 717 718 #define L2_L_PROT_U L2_L_PROT_U_generic 719 #define L2_L_PROT_W L2_L_PROT_W_generic 720 #define L2_L_PROT_RO L2_L_PROT_RO_generic 721 #define L2_L_PROT_MASK L2_L_PROT_MASK_generic 722 723 #define L1_S_CACHE_MASK L1_S_CACHE_MASK_generic 724 #define L2_L_CACHE_MASK L2_L_CACHE_MASK_generic 725 #define L2_S_CACHE_MASK L2_S_CACHE_MASK_generic 726 727 #define L1_SS_PROTO L1_SS_PROTO_generic 728 #define L1_S_PROTO L1_S_PROTO_generic 729 #define L1_C_PROTO L1_C_PROTO_generic 730 #define L2_S_PROTO L2_S_PROTO_generic 731 732 #define pmap_copy_page(s, d) pmap_copy_page_generic((s), (d)) 733 #define pmap_zero_page(d) pmap_zero_page_generic((d)) 734 #elif ARM_MMU_V6N != 0 735 #define L1_S_PROT_U L1_S_PROT_U_armv6 736 #define L1_S_PROT_W L1_S_PROT_W_armv6 737 #define L1_S_PROT_RO L1_S_PROT_RO_armv6 738 #define L1_S_PROT_MASK L1_S_PROT_MASK_armv6 739 740 #define L2_S_PROT_U L2_S_PROT_U_armv6n 741 #define L2_S_PROT_W L2_S_PROT_W_armv6n 742 #define L2_S_PROT_RO L2_S_PROT_RO_armv6n 743 #define L2_S_PROT_MASK L2_S_PROT_MASK_armv6n 744 745 #define L2_L_PROT_U L2_L_PROT_U_armv6n 746 #define L2_L_PROT_W L2_L_PROT_W_armv6n 747 #define L2_L_PROT_RO L2_L_PROT_RO_armv6n 748 #define L2_L_PROT_MASK L2_L_PROT_MASK_armv6n 749 750 #define L1_S_CACHE_MASK L1_S_CACHE_MASK_armv6 751 #define L2_L_CACHE_MASK L2_L_CACHE_MASK_armv6 752 #define L2_S_CACHE_MASK L2_S_CACHE_MASK_armv6n 753 754 /* These prototypes make writeable mappings, while the other MMU types 755 * make read-only mappings. */ 756 #define L1_SS_PROTO L1_SS_PROTO_armv6 757 #define L1_S_PROTO L1_S_PROTO_armv6 758 #define L1_C_PROTO L1_C_PROTO_armv6 759 #define L2_S_PROTO L2_S_PROTO_armv6n 760 761 #define pmap_copy_page(s, d) pmap_copy_page_generic((s), (d)) 762 #define pmap_zero_page(d) pmap_zero_page_generic((d)) 763 #elif ARM_MMU_V6C != 0 764 #define L1_S_PROT_U L1_S_PROT_U_generic 765 #define L1_S_PROT_W L1_S_PROT_W_generic 766 #define L1_S_PROT_RO L1_S_PROT_RO_generic 767 #define L1_S_PROT_MASK L1_S_PROT_MASK_generic 768 769 #define L2_S_PROT_U L2_S_PROT_U_generic 770 #define L2_S_PROT_W L2_S_PROT_W_generic 771 #define L2_S_PROT_RO L2_S_PROT_RO_generic 772 #define L2_S_PROT_MASK L2_S_PROT_MASK_generic 773 774 #define L2_L_PROT_U L2_L_PROT_U_generic 775 #define L2_L_PROT_W L2_L_PROT_W_generic 776 #define L2_L_PROT_RO L2_L_PROT_RO_generic 777 #define L2_L_PROT_MASK L2_L_PROT_MASK_generic 778 779 #define L1_S_CACHE_MASK L1_S_CACHE_MASK_generic 780 #define L2_L_CACHE_MASK L2_L_CACHE_MASK_generic 781 #define L2_S_CACHE_MASK L2_S_CACHE_MASK_generic 782 783 #define L1_SS_PROTO L1_SS_PROTO_generic 784 #define L1_S_PROTO L1_S_PROTO_generic 785 #define L1_C_PROTO L1_C_PROTO_generic 786 #define L2_S_PROTO L2_S_PROTO_generic 787 788 #define pmap_copy_page(s, d) pmap_copy_page_generic((s), (d)) 789 #define pmap_zero_page(d) pmap_zero_page_generic((d)) 790 #elif ARM_MMU_XSCALE == 1 791 #define L1_S_PROT_U L1_S_PROT_U_generic 792 #define L1_S_PROT_W L1_S_PROT_W_generic 793 #define L1_S_PROT_RO L1_S_PROT_RO_generic 794 #define L1_S_PROT_MASK L1_S_PROT_MASK_generic 795 796 #define L2_S_PROT_U L2_S_PROT_U_xscale 797 #define L2_S_PROT_W L2_S_PROT_W_xscale 798 #define L2_S_PROT_RO L2_S_PROT_RO_xscale 799 #define L2_S_PROT_MASK L2_S_PROT_MASK_xscale 800 801 #define L2_L_PROT_U L2_L_PROT_U_generic 802 #define L2_L_PROT_W L2_L_PROT_W_generic 803 #define L2_L_PROT_RO L2_L_PROT_RO_generic 804 #define L2_L_PROT_MASK L2_L_PROT_MASK_generic 805 806 #define L1_S_CACHE_MASK L1_S_CACHE_MASK_xscale 807 #define L2_L_CACHE_MASK L2_L_CACHE_MASK_xscale 808 #define L2_S_CACHE_MASK L2_S_CACHE_MASK_xscale 809 810 #define L1_SS_PROTO L1_SS_PROTO_xscale 811 #define L1_S_PROTO L1_S_PROTO_xscale 812 #define L1_C_PROTO L1_C_PROTO_xscale 813 #define L2_S_PROTO L2_S_PROTO_xscale 814 815 #define pmap_copy_page(s, d) pmap_copy_page_xscale((s), (d)) 816 #define pmap_zero_page(d) pmap_zero_page_xscale((d)) 817 #elif ARM_MMU_V7 == 1 818 #define L1_S_PROT_U L1_S_PROT_U_armv7 819 #define L1_S_PROT_W L1_S_PROT_W_armv7 820 #define L1_S_PROT_RO L1_S_PROT_RO_armv7 821 #define L1_S_PROT_MASK L1_S_PROT_MASK_armv7 822 823 #define L2_S_PROT_U L2_S_PROT_U_armv7 824 #define L2_S_PROT_W L2_S_PROT_W_armv7 825 #define L2_S_PROT_RO L2_S_PROT_RO_armv7 826 #define L2_S_PROT_MASK L2_S_PROT_MASK_armv7 827 828 #define L2_L_PROT_U L2_L_PROT_U_armv7 829 #define L2_L_PROT_W L2_L_PROT_W_armv7 830 #define L2_L_PROT_RO L2_L_PROT_RO_armv7 831 #define L2_L_PROT_MASK L2_L_PROT_MASK_armv7 832 833 #define L1_S_CACHE_MASK L1_S_CACHE_MASK_armv7 834 #define L2_L_CACHE_MASK L2_L_CACHE_MASK_armv7 835 #define L2_S_CACHE_MASK L2_S_CACHE_MASK_armv7 836 837 /* These prototypes make writeable mappings, while the other MMU types 838 * make read-only mappings. */ 839 #define L1_SS_PROTO L1_SS_PROTO_armv7 840 #define L1_S_PROTO L1_S_PROTO_armv7 841 #define L1_C_PROTO L1_C_PROTO_armv7 842 #define L2_S_PROTO L2_S_PROTO_armv7 843 844 #define pmap_copy_page(s, d) pmap_copy_page_generic((s), (d)) 845 #define pmap_zero_page(d) pmap_zero_page_generic((d)) 846 #endif /* ARM_NMMUS > 1 */ 847 848 /* 849 * Macros to set and query the write permission on page descriptors. 850 */ 851 #define l1pte_set_writable(pte) (((pte) & ~L1_S_PROT_RO) | L1_S_PROT_W) 852 #define l1pte_set_readonly(pte) (((pte) & ~L1_S_PROT_W) | L1_S_PROT_RO) 853 #define l2pte_set_writable(pte) (((pte) & ~L2_S_PROT_RO) | L2_S_PROT_W) 854 #define l2pte_set_readonly(pte) (((pte) & ~L2_S_PROT_W) | L2_S_PROT_RO) 855 856 #define l2pte_writable_p(pte) (((pte) & L2_S_PROT_W) == L2_S_PROT_W && \ 857 (L2_S_PROT_RO == 0 || \ 858 ((pte) & L2_S_PROT_RO) != L2_S_PROT_RO)) 859 860 /* 861 * These macros return various bits based on kernel/user and protection. 862 * Note that the compiler will usually fold these at compile time. 863 */ 864 #define L1_S_PROT(ku, pr) ((((ku) == PTE_USER) ? L1_S_PROT_U : 0) | \ 865 (((pr) & VM_PROT_WRITE) ? L1_S_PROT_W : L1_S_PROT_RO)) 866 867 #define L2_L_PROT(ku, pr) ((((ku) == PTE_USER) ? L2_L_PROT_U : 0) | \ 868 (((pr) & VM_PROT_WRITE) ? L2_L_PROT_W : L2_L_PROT_RO)) 869 870 #define L2_S_PROT(ku, pr) ((((ku) == PTE_USER) ? L2_S_PROT_U : 0) | \ 871 (((pr) & VM_PROT_WRITE) ? L2_S_PROT_W : L2_S_PROT_RO)) 872 873 /* 874 * Macros to test if a mapping is mappable with an L1 SuperSection, 875 * L1 Section, or an L2 Large Page mapping. 876 */ 877 #define L1_SS_MAPPABLE_P(va, pa, size) \ 878 ((((va) | (pa)) & L1_SS_OFFSET) == 0 && (size) >= L1_SS_SIZE) 879 880 #define L1_S_MAPPABLE_P(va, pa, size) \ 881 ((((va) | (pa)) & L1_S_OFFSET) == 0 && (size) >= L1_S_SIZE) 882 883 #define L2_L_MAPPABLE_P(va, pa, size) \ 884 ((((va) | (pa)) & L2_L_OFFSET) == 0 && (size) >= L2_L_SIZE) 885 886 /* 887 * Hooks for the pool allocator. 888 */ 889 #define POOL_VTOPHYS(va) vtophys((vaddr_t) (va)) 890 891 #ifndef _LOCORE 892 893 /* 894 * pmap-specific data store in the vm_page structure. 895 */ 896 #define __HAVE_VM_PAGE_MD 897 struct vm_page_md { 898 SLIST_HEAD(,pv_entry) pvh_list; /* pv_entry list */ 899 int pvh_attrs; /* page attributes */ 900 u_int uro_mappings; 901 u_int urw_mappings; 902 union { 903 u_short s_mappings[2]; /* Assume kernel count <= 65535 */ 904 u_int i_mappings; 905 } k_u; 906 #define kro_mappings k_u.s_mappings[0] 907 #define krw_mappings k_u.s_mappings[1] 908 #define k_mappings k_u.i_mappings 909 }; 910 911 /* 912 * Set the default color of each page. 913 */ 914 #if ARM_MMU_V6 > 0 915 #define VM_MDPAGE_PVH_ATTRS_INIT(pg) \ 916 (pg)->mdpage.pvh_attrs = (pg)->phys_addr & arm_cache_prefer_mask 917 #else 918 #define VM_MDPAGE_PVH_ATTRS_INIT(pg) \ 919 (pg)->mdpage.pvh_attrs = 0 920 #endif 921 922 #define VM_MDPAGE_INIT(pg) \ 923 do { \ 924 SLIST_INIT(&(pg)->mdpage.pvh_list); \ 925 VM_MDPAGE_PVH_ATTRS_INIT(pg); \ 926 (pg)->mdpage.uro_mappings = 0; \ 927 (pg)->mdpage.urw_mappings = 0; \ 928 (pg)->mdpage.k_mappings = 0; \ 929 } while (/*CONSTCOND*/0) 930 931 #endif /* !_LOCORE */ 932 933 #endif /* _KERNEL */ 934 935 #endif /* _ARM32_PMAP_H_ */ 936
Indexes created Wed Sep 24 14:09:57 GMT 2025