pmap.h revision 1.116
1 /* $NetBSD: pmap.h,v 1.116 2012/12/10 06:53:52 matt Exp $ */ 2 3 /* 4 * Copyright (c) 2002, 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe & Steve C. Woodford for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Copyright (c) 1994,1995 Mark Brinicombe. 40 * All rights reserved. 41 * 42 * Redistribution and use in source and binary forms, with or without 43 * modification, are permitted provided that the following conditions 44 * are met: 45 * 1. Redistributions of source code must retain the above copyright 46 * notice, this list of conditions and the following disclaimer. 47 * 2. Redistributions in binary form must reproduce the above copyright 48 * notice, this list of conditions and the following disclaimer in the 49 * documentation and/or other materials provided with the distribution. 50 * 3. All advertising materials mentioning features or use of this software 51 * must display the following acknowledgement: 52 * This product includes software developed by Mark Brinicombe 53 * 4. The name of the author may not be used to endorse or promote products 54 * derived from this software without specific prior written permission. 55 * 56 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 57 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 58 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 59 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 60 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 61 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 62 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 63 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 64 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 65 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 #ifndef _ARM32_PMAP_H_ 69 #define _ARM32_PMAP_H_ 70 71 #ifdef _KERNEL 72 73 #include <arm/cpuconf.h> 74 #include <arm/arm32/pte.h> 75 #ifndef _LOCORE 76 #if defined(_KERNEL_OPT) 77 #include "opt_arm32_pmap.h" 78 #endif 79 #include <arm/cpufunc.h> 80 #include <uvm/uvm_object.h> 81 #endif 82 83 /* 84 * a pmap describes a processes' 4GB virtual address space. this 85 * virtual address space can be broken up into 4096 1MB regions which 86 * are described by L1 PTEs in the L1 table. 87 * 88 * There is a line drawn at KERNEL_BASE. Everything below that line 89 * changes when the VM context is switched. Everything above that line 90 * is the same no matter which VM context is running. This is achieved 91 * by making the L1 PTEs for those slots above KERNEL_BASE reference 92 * kernel L2 tables. 93 * 94 * The basic layout of the virtual address space thus looks like this: 95 * 96 * 0xffffffff 97 * . 98 * . 99 * . 100 * KERNEL_BASE 101 * -------------------- 102 * . 103 * . 104 * . 105 * 0x00000000 106 */ 107 108 /* 109 * The number of L2 descriptor tables which can be tracked by an l2_dtable. 110 * A bucket size of 16 provides for 16MB of contiguous virtual address 111 * space per l2_dtable. Most processes will, therefore, require only two or 112 * three of these to map their whole working set. 113 */ 114 #define L2_BUCKET_LOG2 4 115 #define L2_BUCKET_SIZE (1 << L2_BUCKET_LOG2) 116 117 /* 118 * Given the above "L2-descriptors-per-l2_dtable" constant, the number 119 * of l2_dtable structures required to track all possible page descriptors 120 * mappable by an L1 translation table is given by the following constants: 121 */ 122 #define L2_LOG2 ((32 - L1_S_SHIFT) - L2_BUCKET_LOG2) 123 #define L2_SIZE (1 << L2_LOG2) 124 125 /* 126 * tell MI code that the cache is virtually-indexed. 127 * ARMv6 is physically-tagged but all others are virtually-tagged. 128 */ 129 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 130 #define PMAP_CACHE_VIPT 131 #else 132 #define PMAP_CACHE_VIVT 133 #endif 134 135 #ifndef _LOCORE 136 137 struct l1_ttable; 138 struct l2_dtable; 139 140 /* 141 * Track cache/tlb occupancy using the following structure 142 */ 143 union pmap_cache_state { 144 struct { 145 union { 146 uint8_t csu_cache_b[2]; 147 uint16_t csu_cache; 148 } cs_cache_u; 149 150 union { 151 uint8_t csu_tlb_b[2]; 152 uint16_t csu_tlb; 153 } cs_tlb_u; 154 } cs_s; 155 uint32_t cs_all; 156 }; 157 #define cs_cache_id cs_s.cs_cache_u.csu_cache_b[0] 158 #define cs_cache_d cs_s.cs_cache_u.csu_cache_b[1] 159 #define cs_cache cs_s.cs_cache_u.csu_cache 160 #define cs_tlb_id cs_s.cs_tlb_u.csu_tlb_b[0] 161 #define cs_tlb_d cs_s.cs_tlb_u.csu_tlb_b[1] 162 #define cs_tlb cs_s.cs_tlb_u.csu_tlb 163 164 /* 165 * Assigned to cs_all to force cacheops to work for a particular pmap 166 */ 167 #define PMAP_CACHE_STATE_ALL 0xffffffffu 168 169 /* 170 * This structure is used by machine-dependent code to describe 171 * static mappings of devices, created at bootstrap time. 172 */ 173 struct pmap_devmap { 174 vaddr_t pd_va; /* virtual address */ 175 paddr_t pd_pa; /* physical address */ 176 psize_t pd_size; /* size of region */ 177 vm_prot_t pd_prot; /* protection code */ 178 int pd_cache; /* cache attributes */ 179 }; 180 181 /* 182 * The pmap structure itself 183 */ 184 struct pmap { 185 uint8_t pm_domain; 186 bool pm_remove_all; 187 bool pm_activated; 188 struct l1_ttable *pm_l1; 189 pd_entry_t *pm_pl1vec; 190 pd_entry_t pm_l1vec; 191 union pmap_cache_state pm_cstate; 192 struct uvm_object pm_obj; 193 kmutex_t pm_obj_lock; 194 #define pm_lock pm_obj.vmobjlock 195 struct l2_dtable *pm_l2[L2_SIZE]; 196 struct pmap_statistics pm_stats; 197 LIST_ENTRY(pmap) pm_list; 198 }; 199 200 /* 201 * Physical / virtual address structure. In a number of places (particularly 202 * during bootstrapping) we need to keep track of the physical and virtual 203 * addresses of various pages 204 */ 205 typedef struct pv_addr { 206 SLIST_ENTRY(pv_addr) pv_list; 207 paddr_t pv_pa; 208 vaddr_t pv_va; 209 vsize_t pv_size; 210 uint8_t pv_cache; 211 uint8_t pv_prot; 212 } pv_addr_t; 213 typedef SLIST_HEAD(, pv_addr) pv_addrqh_t; 214 215 extern pv_addrqh_t pmap_freeq; 216 extern pv_addr_t kernelstack; 217 extern pv_addr_t abtstack; 218 extern pv_addr_t fiqstack; 219 extern pv_addr_t irqstack; 220 extern pv_addr_t undstack; 221 extern pv_addr_t idlestack; 222 extern pv_addr_t systempage; 223 extern pv_addr_t kernel_l1pt; 224 225 /* 226 * Determine various modes for PTEs (user vs. kernel, cacheable 227 * vs. non-cacheable). 228 */ 229 #define PTE_KERNEL 0 230 #define PTE_USER 1 231 #define PTE_NOCACHE 0 232 #define PTE_CACHE 1 233 #define PTE_PAGETABLE 2 234 235 /* 236 * Flags that indicate attributes of pages or mappings of pages. 237 * 238 * The PVF_MOD and PVF_REF flags are stored in the mdpage for each 239 * page. PVF_WIRED, PVF_WRITE, and PVF_NC are kept in individual 240 * pv_entry's for each page. They live in the same "namespace" so 241 * that we can clear multiple attributes at a time. 242 * 243 * Note the "non-cacheable" flag generally means the page has 244 * multiple mappings in a given address space. 245 */ 246 #define PVF_MOD 0x01 /* page is modified */ 247 #define PVF_REF 0x02 /* page is referenced */ 248 #define PVF_WIRED 0x04 /* mapping is wired */ 249 #define PVF_WRITE 0x08 /* mapping is writable */ 250 #define PVF_EXEC 0x10 /* mapping is executable */ 251 #ifdef PMAP_CACHE_VIVT 252 #define PVF_UNC 0x20 /* mapping is 'user' non-cacheable */ 253 #define PVF_KNC 0x40 /* mapping is 'kernel' non-cacheable */ 254 #define PVF_NC (PVF_UNC|PVF_KNC) 255 #endif 256 #ifdef PMAP_CACHE_VIPT 257 #define PVF_NC 0x20 /* mapping is 'kernel' non-cacheable */ 258 #define PVF_MULTCLR 0x40 /* mapping is multi-colored */ 259 #endif 260 #define PVF_COLORED 0x80 /* page has or had a color */ 261 #define PVF_KENTRY 0x0100 /* page entered via pmap_kenter_pa */ 262 #define PVF_KMPAGE 0x0200 /* page is used for kmem */ 263 #define PVF_DIRTY 0x0400 /* page may have dirty cache lines */ 264 #define PVF_KMOD 0x0800 /* unmanaged page is modified */ 265 #define PVF_KWRITE (PVF_KENTRY|PVF_WRITE) 266 #define PVF_DMOD (PVF_MOD|PVF_KMOD|PVF_KMPAGE) 267 268 /* 269 * Commonly referenced structures 270 */ 271 extern int pmap_debug_level; /* Only exists if PMAP_DEBUG */ 272 extern int arm_poolpage_vmfreelist; 273 274 /* 275 * Macros that we need to export 276 */ 277 #define pmap_resident_count(pmap) ((pmap)->pm_stats.resident_count) 278 #define pmap_wired_count(pmap) ((pmap)->pm_stats.wired_count) 279 280 #define pmap_is_modified(pg) \ 281 (((pg)->mdpage.pvh_attrs & PVF_MOD) != 0) 282 #define pmap_is_referenced(pg) \ 283 (((pg)->mdpage.pvh_attrs & PVF_REF) != 0) 284 #define pmap_is_page_colored_p(md) \ 285 (((md)->pvh_attrs & PVF_COLORED) != 0) 286 287 #define pmap_copy(dp, sp, da, l, sa) /* nothing */ 288 289 #define pmap_phys_address(ppn) (arm_ptob((ppn))) 290 u_int arm32_mmap_flags(paddr_t); 291 #define ARM32_MMAP_WRITECOMBINE 0x40000000 292 #define ARM32_MMAP_CACHEABLE 0x20000000 293 #define pmap_mmap_flags(ppn) arm32_mmap_flags(ppn) 294 295 /* 296 * Functions that we need to export 297 */ 298 void pmap_procwr(struct proc *, vaddr_t, int); 299 void pmap_remove_all(pmap_t); 300 bool pmap_extract(pmap_t, vaddr_t, paddr_t *); 301 302 #define PMAP_NEED_PROCWR 303 #define PMAP_GROWKERNEL /* turn on pmap_growkernel interface */ 304 #define PMAP_ENABLE_PMAP_KMPAGE /* enable the PMAP_KMPAGE flag */ 305 306 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 307 #define PMAP_PREFER(hint, vap, sz, td) pmap_prefer((hint), (vap), (td)) 308 void pmap_prefer(vaddr_t, vaddr_t *, int); 309 #endif 310 311 void pmap_icache_sync_range(pmap_t, vaddr_t, vaddr_t); 312 313 /* Functions we use internally. */ 314 #ifdef PMAP_STEAL_MEMORY 315 void pmap_boot_pagealloc(psize_t, psize_t, psize_t, pv_addr_t *); 316 void pmap_boot_pageadd(pv_addr_t *); 317 vaddr_t pmap_steal_memory(vsize_t, vaddr_t *, vaddr_t *); 318 #endif 319 void pmap_bootstrap(vaddr_t, vaddr_t); 320 321 void pmap_do_remove(pmap_t, vaddr_t, vaddr_t, int); 322 int pmap_fault_fixup(pmap_t, vaddr_t, vm_prot_t, int); 323 bool pmap_get_pde_pte(pmap_t, vaddr_t, pd_entry_t **, pt_entry_t **); 324 bool pmap_get_pde(pmap_t, vaddr_t, pd_entry_t **); 325 void pmap_set_pcb_pagedir(pmap_t, struct pcb *); 326 327 void pmap_debug(int); 328 void pmap_postinit(void); 329 330 void vector_page_setprot(int); 331 332 const struct pmap_devmap *pmap_devmap_find_pa(paddr_t, psize_t); 333 const struct pmap_devmap *pmap_devmap_find_va(vaddr_t, vsize_t); 334 335 /* Bootstrapping routines. */ 336 void pmap_map_section(vaddr_t, vaddr_t, paddr_t, int, int); 337 void pmap_map_entry(vaddr_t, vaddr_t, paddr_t, int, int); 338 vsize_t pmap_map_chunk(vaddr_t, vaddr_t, paddr_t, vsize_t, int, int); 339 void pmap_link_l2pt(vaddr_t, vaddr_t, pv_addr_t *); 340 void pmap_devmap_bootstrap(vaddr_t, const struct pmap_devmap *); 341 void pmap_devmap_register(const struct pmap_devmap *); 342 343 /* 344 * Special page zero routine for use by the idle loop (no cache cleans). 345 */ 346 bool pmap_pageidlezero(paddr_t); 347 #define PMAP_PAGEIDLEZERO(pa) pmap_pageidlezero((pa)) 348 349 /* 350 * used by dumpsys to record the PA of the L1 table 351 */ 352 uint32_t pmap_kernel_L1_addr(void); 353 /* 354 * The current top of kernel VM 355 */ 356 extern vaddr_t pmap_curmaxkvaddr; 357 358 /* 359 * Useful macros and constants 360 */ 361 362 /* Virtual address to page table entry */ 363 static inline pt_entry_t * 364 vtopte(vaddr_t va) 365 { 366 pd_entry_t *pdep; 367 pt_entry_t *ptep; 368 369 if (pmap_get_pde_pte(pmap_kernel(), va, &pdep, &ptep) == false) 370 return (NULL); 371 return (ptep); 372 } 373 374 /* 375 * Virtual address to physical address 376 */ 377 static inline paddr_t 378 vtophys(vaddr_t va) 379 { 380 paddr_t pa; 381 382 if (pmap_extract(pmap_kernel(), va, &pa) == false) 383 return (0); /* XXXSCW: Panic? */ 384 385 return (pa); 386 } 387 388 /* 389 * The new pmap ensures that page-tables are always mapping Write-Thru. 390 * Thus, on some platforms we can run fast and loose and avoid syncing PTEs 391 * on every change. 392 * 393 * Unfortunately, not all CPUs have a write-through cache mode. So we 394 * define PMAP_NEEDS_PTE_SYNC for C code to conditionally do PTE syncs, 395 * and if there is the chance for PTE syncs to be needed, we define 396 * PMAP_INCLUDE_PTE_SYNC so e.g. assembly code can include (and run) 397 * the code. 398 */ 399 extern int pmap_needs_pte_sync; 400 #if defined(_KERNEL_OPT) 401 /* 402 * StrongARM SA-1 caches do not have a write-through mode. So, on these, 403 * we need to do PTE syncs. If only SA-1 is configured, then evaluate 404 * this at compile time. 405 */ 406 #if (ARM_MMU_SA1 + ARM_MMU_V6 != 0) && (ARM_NMMUS == 1) 407 #define PMAP_INCLUDE_PTE_SYNC 408 #if (ARM_MMU_V6 > 0) 409 #define PMAP_NEEDS_PTE_SYNC 1 410 #elif (ARM_MMU_SA1 == 0) 411 #define PMAP_NEEDS_PTE_SYNC 0 412 #endif 413 #endif 414 #endif /* _KERNEL_OPT */ 415 416 /* 417 * Provide a fallback in case we were not able to determine it at 418 * compile-time. 419 */ 420 #ifndef PMAP_NEEDS_PTE_SYNC 421 #define PMAP_NEEDS_PTE_SYNC pmap_needs_pte_sync 422 #define PMAP_INCLUDE_PTE_SYNC 423 #endif 424 425 static inline void 426 pmap_ptesync(pt_entry_t *ptep, size_t cnt) 427 { 428 if (PMAP_NEEDS_PTE_SYNC) 429 cpu_dcache_wb_range((vaddr_t)ptep, cnt * sizeof(pt_entry_t)); 430 #if ARM_MMU_V7 > 0 431 __asm("dsb"); 432 #endif 433 } 434 435 #define PTE_SYNC(ptep) pmap_ptesync((ptep), 1) 436 #define PTE_SYNC_RANGE(ptep, cnt) pmap_ptesync((ptep), (cnt)) 437 438 #define l1pte_valid(pde) ((pde) != 0) 439 #define l1pte_section_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_S) 440 #define l1pte_supersection_p(pde) (l1pte_section_p(pde) \ 441 && ((pde) & L1_S_V6_SUPER) != 0) 442 #define l1pte_page_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_C) 443 #define l1pte_fpage_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_F) 444 445 #define l2pte_index(v) (((v) & L2_ADDR_BITS) >> L2_S_SHIFT) 446 #define l2pte_valid(pte) (((pte) & L2_TYPE_MASK) != L2_TYPE_INV) 447 #define l2pte_pa(pte) ((pte) & L2_S_FRAME) 448 #define l2pte_minidata(pte) (((pte) & \ 449 (L2_B | L2_C | L2_XS_T_TEX(TEX_XSCALE_X)))\ 450 == (L2_C | L2_XS_T_TEX(TEX_XSCALE_X))) 451 452 /* L1 and L2 page table macros */ 453 #define pmap_pde_v(pde) l1pte_valid(*(pde)) 454 #define pmap_pde_section(pde) l1pte_section_p(*(pde)) 455 #define pmap_pde_supersection(pde) l1pte_supersection_p(*(pde)) 456 #define pmap_pde_page(pde) l1pte_page_p(*(pde)) 457 #define pmap_pde_fpage(pde) l1pte_fpage_p(*(pde)) 458 459 #define pmap_pte_v(pte) l2pte_valid(*(pte)) 460 #define pmap_pte_pa(pte) l2pte_pa(*(pte)) 461 462 /* Size of the kernel part of the L1 page table */ 463 #define KERNEL_PD_SIZE \ 464 (L1_TABLE_SIZE - (KERNEL_BASE >> L1_S_SHIFT) * sizeof(pd_entry_t)) 465 466 /************************* ARM MMU configuration *****************************/ 467 468 #ifdef FPU_VFP 469 void pmap_copy_page_vfp(paddr_t, paddr_t); 470 void pmap_zero_page_vfp(paddr_t); 471 #endif 472 473 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 474 void pmap_copy_page_generic(paddr_t, paddr_t); 475 void pmap_zero_page_generic(paddr_t); 476 477 void pmap_pte_init_generic(void); 478 #if defined(CPU_ARM8) 479 void pmap_pte_init_arm8(void); 480 #endif 481 #if defined(CPU_ARM9) 482 void pmap_pte_init_arm9(void); 483 #endif /* CPU_ARM9 */ 484 #if defined(CPU_ARM10) 485 void pmap_pte_init_arm10(void); 486 #endif /* CPU_ARM10 */ 487 #if defined(CPU_ARM11) /* ARM_MMU_V6 */ 488 void pmap_pte_init_arm11(void); 489 #endif /* CPU_ARM11 */ 490 #if defined(CPU_ARM11MPCORE) /* ARM_MMU_V6 */ 491 void pmap_pte_init_arm11mpcore(void); 492 #endif 493 #if ARM_MMU_V7 == 1 494 void pmap_pte_init_armv7(void); 495 #endif /* ARM_MMU_V7 */ 496 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */ 497 498 #if ARM_MMU_SA1 == 1 499 void pmap_pte_init_sa1(void); 500 #endif /* ARM_MMU_SA1 == 1 */ 501 502 #if ARM_MMU_XSCALE == 1 503 void pmap_copy_page_xscale(paddr_t, paddr_t); 504 void pmap_zero_page_xscale(paddr_t); 505 506 void pmap_pte_init_xscale(void); 507 508 void xscale_setup_minidata(vaddr_t, vaddr_t, paddr_t); 509 510 #define PMAP_UAREA(va) pmap_uarea(va) 511 void pmap_uarea(vaddr_t); 512 #endif /* ARM_MMU_XSCALE == 1 */ 513 514 extern pt_entry_t pte_l1_s_cache_mode; 515 extern pt_entry_t pte_l1_s_cache_mask; 516 517 extern pt_entry_t pte_l2_l_cache_mode; 518 extern pt_entry_t pte_l2_l_cache_mask; 519 520 extern pt_entry_t pte_l2_s_cache_mode; 521 extern pt_entry_t pte_l2_s_cache_mask; 522 523 extern pt_entry_t pte_l1_s_cache_mode_pt; 524 extern pt_entry_t pte_l2_l_cache_mode_pt; 525 extern pt_entry_t pte_l2_s_cache_mode_pt; 526 527 extern pt_entry_t pte_l1_s_wc_mode; 528 extern pt_entry_t pte_l2_l_wc_mode; 529 extern pt_entry_t pte_l2_s_wc_mode; 530 531 extern pt_entry_t pte_l1_s_prot_u; 532 extern pt_entry_t pte_l1_s_prot_w; 533 extern pt_entry_t pte_l1_s_prot_ro; 534 extern pt_entry_t pte_l1_s_prot_mask; 535 536 extern pt_entry_t pte_l2_s_prot_u; 537 extern pt_entry_t pte_l2_s_prot_w; 538 extern pt_entry_t pte_l2_s_prot_ro; 539 extern pt_entry_t pte_l2_s_prot_mask; 540 541 extern pt_entry_t pte_l2_l_prot_u; 542 extern pt_entry_t pte_l2_l_prot_w; 543 extern pt_entry_t pte_l2_l_prot_ro; 544 extern pt_entry_t pte_l2_l_prot_mask; 545 546 extern pt_entry_t pte_l1_ss_proto; 547 extern pt_entry_t pte_l1_s_proto; 548 extern pt_entry_t pte_l1_c_proto; 549 extern pt_entry_t pte_l2_s_proto; 550 551 extern void (*pmap_copy_page_func)(paddr_t, paddr_t); 552 extern void (*pmap_zero_page_func)(paddr_t); 553 554 #endif /* !_LOCORE */ 555 556 /*****************************************************************************/ 557 558 /* 559 * Definitions for MMU domains 560 */ 561 #define PMAP_DOMAINS 15 /* 15 'user' domains (1-15) */ 562 #define PMAP_DOMAIN_KERNEL 0 /* The kernel uses domain #0 */ 563 564 /* 565 * These macros define the various bit masks in the PTE. 566 * 567 * We use these macros since we use different bits on different processor 568 * models. 569 */ 570 #define L1_S_PROT_U_generic (L1_S_AP(AP_U)) 571 #define L1_S_PROT_W_generic (L1_S_AP(AP_W)) 572 #define L1_S_PROT_RO_generic (0) 573 #define L1_S_PROT_MASK_generic (L1_S_PROT_U|L1_S_PROT_W|L1_S_PROT_RO) 574 575 #define L1_S_PROT_U_xscale (L1_S_AP(AP_U)) 576 #define L1_S_PROT_W_xscale (L1_S_AP(AP_W)) 577 #define L1_S_PROT_RO_xscale (0) 578 #define L1_S_PROT_MASK_xscale (L1_S_PROT_U|L1_S_PROT_W|L1_S_PROT_RO) 579 580 #define L1_S_PROT_U_armv6 (L1_S_AP(AP_R) | L1_S_AP(AP_U)) 581 #define L1_S_PROT_W_armv6 (L1_S_AP(AP_W)) 582 #define L1_S_PROT_RO_armv6 (L1_S_AP(AP_R) | L1_S_AP(AP_RO)) 583 #define L1_S_PROT_MASK_armv6 (L1_S_PROT_U|L1_S_PROT_W|L1_S_PROT_RO) 584 585 #define L1_S_PROT_U_armv7 (L1_S_AP(AP_R) | L1_S_AP(AP_U)) 586 #define L1_S_PROT_W_armv7 (L1_S_AP(AP_W)) 587 #define L1_S_PROT_RO_armv7 (L1_S_AP(AP_R) | L1_S_AP(AP_RO)) 588 #define L1_S_PROT_MASK_armv7 (L1_S_PROT_U|L1_S_PROT_W|L1_S_PROT_RO) 589 590 #define L1_S_CACHE_MASK_generic (L1_S_B|L1_S_C) 591 #define L1_S_CACHE_MASK_xscale (L1_S_B|L1_S_C|L1_S_XS_TEX(TEX_XSCALE_X)) 592 #define L1_S_CACHE_MASK_armv6 (L1_S_B|L1_S_C|L1_S_XS_TEX(TEX_ARMV6_TEX)) 593 #define L1_S_CACHE_MASK_armv7 (L1_S_B|L1_S_C|L1_S_XS_TEX(TEX_ARMV6_TEX)|L1_S_V6_S) 594 595 #define L2_L_PROT_U_generic (L2_AP(AP_U)) 596 #define L2_L_PROT_W_generic (L2_AP(AP_W)) 597 #define L2_L_PROT_RO_generic (0) 598 #define L2_L_PROT_MASK_generic (L2_L_PROT_U|L2_L_PROT_W|L2_L_PROT_RO) 599 600 #define L2_L_PROT_U_xscale (L2_AP(AP_U)) 601 #define L2_L_PROT_W_xscale (L2_AP(AP_W)) 602 #define L2_L_PROT_RO_xscale (0) 603 #define L2_L_PROT_MASK_xscale (L2_L_PROT_U|L2_L_PROT_W|L2_L_PROT_RO) 604 605 #define L2_L_PROT_U_armv6n (L2_AP0(AP_R) | L2_AP0(AP_U)) 606 #define L2_L_PROT_W_armv6n (L2_AP0(AP_W)) 607 #define L2_L_PROT_RO_armv6n (L2_AP0(AP_R) | L2_AP0(AP_RO)) 608 #define L2_L_PROT_MASK_armv6n (L2_L_PROT_U|L2_L_PROT_W|L2_L_PROT_RO) 609 610 #define L2_L_PROT_U_armv7 (L2_AP0(AP_R) | L2_AP0(AP_U)) 611 #define L2_L_PROT_W_armv7 (L2_AP0(AP_W)) 612 #define L2_L_PROT_RO_armv7 (L2_AP0(AP_R) | L2_AP0(AP_RO)) 613 #define L2_L_PROT_MASK_armv7 (L2_L_PROT_U|L2_L_PROT_W|L2_L_PROT_RO) 614 615 #define L2_L_CACHE_MASK_generic (L2_B|L2_C) 616 #define L2_L_CACHE_MASK_xscale (L2_B|L2_C|L2_XS_L_TEX(TEX_XSCALE_X)) 617 #define L2_L_CACHE_MASK_armv6 (L2_B|L2_C|L2_V6_L_TEX(TEX_ARMV6_TEX)) 618 #define L2_L_CACHE_MASK_armv7 (L2_B|L2_C|L2_V6_L_TEX(TEX_ARMV6_TEX)|L2_XS_S) 619 620 #define L2_S_PROT_U_generic (L2_AP(AP_U)) 621 #define L2_S_PROT_W_generic (L2_AP(AP_W)) 622 #define L2_S_PROT_RO_generic (0) 623 #define L2_S_PROT_MASK_generic (L2_S_PROT_U|L2_S_PROT_W|L2_S_PROT_RO) 624 625 #define L2_S_PROT_U_xscale (L2_AP0(AP_U)) 626 #define L2_S_PROT_W_xscale (L2_AP0(AP_W)) 627 #define L2_S_PROT_RO_xscale (0) 628 #define L2_S_PROT_MASK_xscale (L2_S_PROT_U|L2_S_PROT_W|L2_S_PROT_RO) 629 630 #define L2_S_PROT_U_armv6n (L2_AP0(AP_R) | L2_AP0(AP_U)) 631 #define L2_S_PROT_W_armv6n (L2_AP0(AP_W)) 632 #define L2_S_PROT_RO_armv6n (L2_AP0(AP_R) | L2_AP0(AP_RO)) 633 #define L2_S_PROT_MASK_armv6n (L2_S_PROT_U|L2_S_PROT_W|L2_S_PROT_RO) 634 635 #define L2_S_PROT_U_armv7 (L2_AP0(AP_R) | L2_AP0(AP_U)) 636 #define L2_S_PROT_W_armv7 (L2_AP0(AP_W)) 637 #define L2_S_PROT_RO_armv7 (L2_AP0(AP_R) | L2_AP0(AP_RO)) 638 #define L2_S_PROT_MASK_armv7 (L2_S_PROT_U|L2_S_PROT_W|L2_S_PROT_RO) 639 640 #define L2_S_CACHE_MASK_generic (L2_B|L2_C) 641 #define L2_S_CACHE_MASK_xscale (L2_B|L2_C|L2_XS_T_TEX(TEX_XSCALE_X)) 642 #define L2_XS_CACHE_MASK_armv6 (L2_B|L2_C|L2_V6_XS_TEX(TEX_ARMV6_TEX)) 643 #define L2_S_CACHE_MASK_armv6n L2_XS_CACHE_MASK_armv6 644 #ifdef ARMV6_EXTENDED_SMALL_PAGE 645 #define L2_S_CACHE_MASK_armv6c L2_XS_CACHE_MASK_armv6 646 #else 647 #define L2_S_CACHE_MASK_armv6c L2_S_CACHE_MASK_generic 648 #endif 649 #define L2_S_CACHE_MASK_armv7 (L2_B|L2_C|L2_V6_XS_TEX(TEX_ARMV6_TEX)|L2_XS_S) 650 651 652 #define L1_S_PROTO_generic (L1_TYPE_S | L1_S_IMP) 653 #define L1_S_PROTO_xscale (L1_TYPE_S) 654 #define L1_S_PROTO_armv6 (L1_TYPE_S) 655 #define L1_S_PROTO_armv7 (L1_TYPE_S) 656 657 #define L1_SS_PROTO_generic 0 658 #define L1_SS_PROTO_xscale 0 659 #define L1_SS_PROTO_armv6 (L1_TYPE_S | L1_S_V6_SS) 660 #define L1_SS_PROTO_armv7 (L1_TYPE_S | L1_S_V6_SS) 661 662 #define L1_C_PROTO_generic (L1_TYPE_C | L1_C_IMP2) 663 #define L1_C_PROTO_xscale (L1_TYPE_C) 664 #define L1_C_PROTO_armv6 (L1_TYPE_C) 665 #define L1_C_PROTO_armv7 (L1_TYPE_C) 666 667 #define L2_L_PROTO (L2_TYPE_L) 668 669 #define L2_S_PROTO_generic (L2_TYPE_S) 670 #define L2_S_PROTO_xscale (L2_TYPE_XS) 671 #ifdef ARMV6_EXTENDED_SMALL_PAGE 672 #define L2_S_PROTO_armv6c (L2_TYPE_XS) /* XP=0, extended small page */ 673 #else 674 #define L2_S_PROTO_armv6c (L2_TYPE_S) /* XP=0, subpage APs */ 675 #endif 676 #define L2_S_PROTO_armv6n (L2_TYPE_S) /* with XP=1 */ 677 #define L2_S_PROTO_armv7 (L2_TYPE_S) 678 679 /* 680 * User-visible names for the ones that vary with MMU class. 681 */ 682 683 #if ARM_NMMUS > 1 684 /* More than one MMU class configured; use variables. */ 685 #define L1_S_PROT_U pte_l1_s_prot_u 686 #define L1_S_PROT_W pte_l1_s_prot_w 687 #define L1_S_PROT_RO pte_l1_s_prot_ro 688 #define L1_S_PROT_MASK pte_l1_s_prot_mask 689 690 #define L2_S_PROT_U pte_l2_s_prot_u 691 #define L2_S_PROT_W pte_l2_s_prot_w 692 #define L2_S_PROT_RO pte_l2_s_prot_ro 693 #define L2_S_PROT_MASK pte_l2_s_prot_mask 694 695 #define L2_L_PROT_U pte_l2_l_prot_u 696 #define L2_L_PROT_W pte_l2_l_prot_w 697 #define L2_L_PROT_RO pte_l2_l_prot_ro 698 #define L2_L_PROT_MASK pte_l2_l_prot_mask 699 700 #define L1_S_CACHE_MASK pte_l1_s_cache_mask 701 #define L2_L_CACHE_MASK pte_l2_l_cache_mask 702 #define L2_S_CACHE_MASK pte_l2_s_cache_mask 703 704 #define L1_SS_PROTO pte_l1_ss_proto 705 #define L1_S_PROTO pte_l1_s_proto 706 #define L1_C_PROTO pte_l1_c_proto 707 #define L2_S_PROTO pte_l2_s_proto 708 709 #define pmap_copy_page(s, d) (*pmap_copy_page_func)((s), (d)) 710 #define pmap_zero_page(d) (*pmap_zero_page_func)((d)) 711 #elif (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 712 #define L1_S_PROT_U L1_S_PROT_U_generic 713 #define L1_S_PROT_W L1_S_PROT_W_generic 714 #define L1_S_PROT_RO L1_S_PROT_RO_generic 715 #define L1_S_PROT_MASK L1_S_PROT_MASK_generic 716 717 #define L2_S_PROT_U L2_S_PROT_U_generic 718 #define L2_S_PROT_W L2_S_PROT_W_generic 719 #define L2_S_PROT_RO L2_S_PROT_RO_generic 720 #define L2_S_PROT_MASK L2_S_PROT_MASK_generic 721 722 #define L2_L_PROT_U L2_L_PROT_U_generic 723 #define L2_L_PROT_W L2_L_PROT_W_generic 724 #define L2_L_PROT_RO L2_L_PROT_RO_generic 725 #define L2_L_PROT_MASK L2_L_PROT_MASK_generic 726 727 #define L1_S_CACHE_MASK L1_S_CACHE_MASK_generic 728 #define L2_L_CACHE_MASK L2_L_CACHE_MASK_generic 729 #define L2_S_CACHE_MASK L2_S_CACHE_MASK_generic 730 731 #define L1_SS_PROTO L1_SS_PROTO_generic 732 #define L1_S_PROTO L1_S_PROTO_generic 733 #define L1_C_PROTO L1_C_PROTO_generic 734 #define L2_S_PROTO L2_S_PROTO_generic 735 736 #define pmap_copy_page(s, d) pmap_copy_page_generic((s), (d)) 737 #define pmap_zero_page(d) pmap_zero_page_generic((d)) 738 #elif ARM_MMU_V6N != 0 739 #define L1_S_PROT_U L1_S_PROT_U_armv6 740 #define L1_S_PROT_W L1_S_PROT_W_armv6 741 #define L1_S_PROT_RO L1_S_PROT_RO_armv6 742 #define L1_S_PROT_MASK L1_S_PROT_MASK_armv6 743 744 #define L2_S_PROT_U L2_S_PROT_U_armv6n 745 #define L2_S_PROT_W L2_S_PROT_W_armv6n 746 #define L2_S_PROT_RO L2_S_PROT_RO_armv6n 747 #define L2_S_PROT_MASK L2_S_PROT_MASK_armv6n 748 749 #define L2_L_PROT_U L2_L_PROT_U_armv6n 750 #define L2_L_PROT_W L2_L_PROT_W_armv6n 751 #define L2_L_PROT_RO L2_L_PROT_RO_armv6n 752 #define L2_L_PROT_MASK L2_L_PROT_MASK_armv6n 753 754 #define L1_S_CACHE_MASK L1_S_CACHE_MASK_armv6 755 #define L2_L_CACHE_MASK L2_L_CACHE_MASK_armv6 756 #define L2_S_CACHE_MASK L2_S_CACHE_MASK_armv6n 757 758 /* These prototypes make writeable mappings, while the other MMU types 759 * make read-only mappings. */ 760 #define L1_SS_PROTO L1_SS_PROTO_armv6 761 #define L1_S_PROTO L1_S_PROTO_armv6 762 #define L1_C_PROTO L1_C_PROTO_armv6 763 #define L2_S_PROTO L2_S_PROTO_armv6n 764 765 #define pmap_copy_page(s, d) pmap_copy_page_generic((s), (d)) 766 #define pmap_zero_page(d) pmap_zero_page_generic((d)) 767 #elif ARM_MMU_V6C != 0 768 #define L1_S_PROT_U L1_S_PROT_U_generic 769 #define L1_S_PROT_W L1_S_PROT_W_generic 770 #define L1_S_PROT_RO L1_S_PROT_RO_generic 771 #define L1_S_PROT_MASK L1_S_PROT_MASK_generic 772 773 #define L2_S_PROT_U L2_S_PROT_U_generic 774 #define L2_S_PROT_W L2_S_PROT_W_generic 775 #define L2_S_PROT_RO L2_S_PROT_RO_generic 776 #define L2_S_PROT_MASK L2_S_PROT_MASK_generic 777 778 #define L2_L_PROT_U L2_L_PROT_U_generic 779 #define L2_L_PROT_W L2_L_PROT_W_generic 780 #define L2_L_PROT_RO L2_L_PROT_RO_generic 781 #define L2_L_PROT_MASK L2_L_PROT_MASK_generic 782 783 #define L1_S_CACHE_MASK L1_S_CACHE_MASK_generic 784 #define L2_L_CACHE_MASK L2_L_CACHE_MASK_generic 785 #define L2_S_CACHE_MASK L2_S_CACHE_MASK_generic 786 787 #define L1_SS_PROTO L1_SS_PROTO_generic 788 #define L1_S_PROTO L1_S_PROTO_generic 789 #define L1_C_PROTO L1_C_PROTO_generic 790 #define L2_S_PROTO L2_S_PROTO_generic 791 792 #define pmap_copy_page(s, d) pmap_copy_page_generic((s), (d)) 793 #define pmap_zero_page(d) pmap_zero_page_generic((d)) 794 #elif ARM_MMU_XSCALE == 1 795 #define L1_S_PROT_U L1_S_PROT_U_generic 796 #define L1_S_PROT_W L1_S_PROT_W_generic 797 #define L1_S_PROT_RO L1_S_PROT_RO_generic 798 #define L1_S_PROT_MASK L1_S_PROT_MASK_generic 799 800 #define L2_S_PROT_U L2_S_PROT_U_xscale 801 #define L2_S_PROT_W L2_S_PROT_W_xscale 802 #define L2_S_PROT_RO L2_S_PROT_RO_xscale 803 #define L2_S_PROT_MASK L2_S_PROT_MASK_xscale 804 805 #define L2_L_PROT_U L2_L_PROT_U_generic 806 #define L2_L_PROT_W L2_L_PROT_W_generic 807 #define L2_L_PROT_RO L2_L_PROT_RO_generic 808 #define L2_L_PROT_MASK L2_L_PROT_MASK_generic 809 810 #define L1_S_CACHE_MASK L1_S_CACHE_MASK_xscale 811 #define L2_L_CACHE_MASK L2_L_CACHE_MASK_xscale 812 #define L2_S_CACHE_MASK L2_S_CACHE_MASK_xscale 813 814 #define L1_SS_PROTO L1_SS_PROTO_xscale 815 #define L1_S_PROTO L1_S_PROTO_xscale 816 #define L1_C_PROTO L1_C_PROTO_xscale 817 #define L2_S_PROTO L2_S_PROTO_xscale 818 819 #define pmap_copy_page(s, d) pmap_copy_page_xscale((s), (d)) 820 #define pmap_zero_page(d) pmap_zero_page_xscale((d)) 821 #elif ARM_MMU_V7 == 1 822 #define L1_S_PROT_U L1_S_PROT_U_armv7 823 #define L1_S_PROT_W L1_S_PROT_W_armv7 824 #define L1_S_PROT_RO L1_S_PROT_RO_armv7 825 #define L1_S_PROT_MASK L1_S_PROT_MASK_armv7 826 827 #define L2_S_PROT_U L2_S_PROT_U_armv7 828 #define L2_S_PROT_W L2_S_PROT_W_armv7 829 #define L2_S_PROT_RO L2_S_PROT_RO_armv7 830 #define L2_S_PROT_MASK L2_S_PROT_MASK_armv7 831 832 #define L2_L_PROT_U L2_L_PROT_U_armv7 833 #define L2_L_PROT_W L2_L_PROT_W_armv7 834 #define L2_L_PROT_RO L2_L_PROT_RO_armv7 835 #define L2_L_PROT_MASK L2_L_PROT_MASK_armv7 836 837 #define L1_S_CACHE_MASK L1_S_CACHE_MASK_armv7 838 #define L2_L_CACHE_MASK L2_L_CACHE_MASK_armv7 839 #define L2_S_CACHE_MASK L2_S_CACHE_MASK_armv7 840 841 /* These prototypes make writeable mappings, while the other MMU types 842 * make read-only mappings. */ 843 #define L1_SS_PROTO L1_SS_PROTO_armv7 844 #define L1_S_PROTO L1_S_PROTO_armv7 845 #define L1_C_PROTO L1_C_PROTO_armv7 846 #define L2_S_PROTO L2_S_PROTO_armv7 847 848 #define pmap_copy_page(s, d) pmap_copy_page_generic((s), (d)) 849 #define pmap_zero_page(d) pmap_zero_page_generic((d)) 850 #endif /* ARM_NMMUS > 1 */ 851 852 /* 853 * Macros to set and query the write permission on page descriptors. 854 */ 855 #define l1pte_set_writable(pte) (((pte) & ~L1_S_PROT_RO) | L1_S_PROT_W) 856 #define l1pte_set_readonly(pte) (((pte) & ~L1_S_PROT_W) | L1_S_PROT_RO) 857 #define l2pte_set_writable(pte) (((pte) & ~L2_S_PROT_RO) | L2_S_PROT_W) 858 #define l2pte_set_readonly(pte) (((pte) & ~L2_S_PROT_W) | L2_S_PROT_RO) 859 860 #define l2pte_writable_p(pte) (((pte) & L2_S_PROT_W) == L2_S_PROT_W && \ 861 (L2_S_PROT_RO == 0 || \ 862 ((pte) & L2_S_PROT_RO) != L2_S_PROT_RO)) 863 864 /* 865 * These macros return various bits based on kernel/user and protection. 866 * Note that the compiler will usually fold these at compile time. 867 */ 868 #define L1_S_PROT(ku, pr) ((((ku) == PTE_USER) ? L1_S_PROT_U : 0) | \ 869 (((pr) & VM_PROT_WRITE) ? L1_S_PROT_W : L1_S_PROT_RO)) 870 871 #define L2_L_PROT(ku, pr) ((((ku) == PTE_USER) ? L2_L_PROT_U : 0) | \ 872 (((pr) & VM_PROT_WRITE) ? L2_L_PROT_W : L2_L_PROT_RO)) 873 874 #define L2_S_PROT(ku, pr) ((((ku) == PTE_USER) ? L2_S_PROT_U : 0) | \ 875 (((pr) & VM_PROT_WRITE) ? L2_S_PROT_W : L2_S_PROT_RO)) 876 877 /* 878 * Macros to test if a mapping is mappable with an L1 SuperSection, 879 * L1 Section, or an L2 Large Page mapping. 880 */ 881 #define L1_SS_MAPPABLE_P(va, pa, size) \ 882 ((((va) | (pa)) & L1_SS_OFFSET) == 0 && (size) >= L1_SS_SIZE) 883 884 #define L1_S_MAPPABLE_P(va, pa, size) \ 885 ((((va) | (pa)) & L1_S_OFFSET) == 0 && (size) >= L1_S_SIZE) 886 887 #define L2_L_MAPPABLE_P(va, pa, size) \ 888 ((((va) | (pa)) & L2_L_OFFSET) == 0 && (size) >= L2_L_SIZE) 889 890 /* 891 * Hooks for the pool allocator. 892 */ 893 #define POOL_VTOPHYS(va) vtophys((vaddr_t) (va)) 894 #ifdef PMAP_NEED_ALLOC_POOLPAGE 895 extern paddr_t physical_start; 896 struct vm_page *arm_pmap_alloc_poolpage(int); 897 #define PMAP_ALLOC_POOLPAGE arm_pmap_alloc_poolpage 898 #define PMAP_MAP_POOLPAGE(pa) \ 899 ((vaddr_t)((paddr_t)(pa) - physical_start + KERNEL_BASE)) 900 #define PMAP_UNMAP_POOLPAGE(va) \ 901 ((paddr_t)((vaddr_t)(va) - KERNEL_BASE + physical_start)) 902 #endif 903 904 #ifndef _LOCORE 905 906 /* 907 * pmap-specific data store in the vm_page structure. 908 */ 909 #define __HAVE_VM_PAGE_MD 910 struct vm_page_md { 911 SLIST_HEAD(,pv_entry) pvh_list; /* pv_entry list */ 912 int pvh_attrs; /* page attributes */ 913 u_int uro_mappings; 914 u_int urw_mappings; 915 union { 916 u_short s_mappings[2]; /* Assume kernel count <= 65535 */ 917 u_int i_mappings; 918 } k_u; 919 #define kro_mappings k_u.s_mappings[0] 920 #define krw_mappings k_u.s_mappings[1] 921 #define k_mappings k_u.i_mappings 922 }; 923 924 /* 925 * Set the default color of each page. 926 */ 927 #if ARM_MMU_V6 > 0 928 #define VM_MDPAGE_PVH_ATTRS_INIT(pg) \ 929 (pg)->mdpage.pvh_attrs = (pg)->phys_addr & arm_cache_prefer_mask 930 #else 931 #define VM_MDPAGE_PVH_ATTRS_INIT(pg) \ 932 (pg)->mdpage.pvh_attrs = 0 933 #endif 934 935 #define VM_MDPAGE_INIT(pg) \ 936 do { \ 937 SLIST_INIT(&(pg)->mdpage.pvh_list); \ 938 VM_MDPAGE_PVH_ATTRS_INIT(pg); \ 939 (pg)->mdpage.uro_mappings = 0; \ 940 (pg)->mdpage.urw_mappings = 0; \ 941 (pg)->mdpage.k_mappings = 0; \ 942 } while (/*CONSTCOND*/0) 943 944 #endif /* !_LOCORE */ 945 946 #endif /* _KERNEL */ 947 948 #endif /* _ARM32_PMAP_H_ */ 949
Indexes created Fri Sep 26 08:10:20 GMT 2025