pmap.h revision 1.125
1 /* $NetBSD: pmap.h,v 1.125 2014/02/26 01:51:51 matt Exp $ */ 2 3 /* 4 * Copyright (c) 2002, 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe & Steve C. Woodford for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Copyright (c) 1994,1995 Mark Brinicombe. 40 * All rights reserved. 41 * 42 * Redistribution and use in source and binary forms, with or without 43 * modification, are permitted provided that the following conditions 44 * are met: 45 * 1. Redistributions of source code must retain the above copyright 46 * notice, this list of conditions and the following disclaimer. 47 * 2. Redistributions in binary form must reproduce the above copyright 48 * notice, this list of conditions and the following disclaimer in the 49 * documentation and/or other materials provided with the distribution. 50 * 3. All advertising materials mentioning features or use of this software 51 * must display the following acknowledgement: 52 * This product includes software developed by Mark Brinicombe 53 * 4. The name of the author may not be used to endorse or promote products 54 * derived from this software without specific prior written permission. 55 * 56 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 57 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 58 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 59 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 60 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 61 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 62 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 63 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 64 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 65 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 #ifndef _ARM32_PMAP_H_ 69 #define _ARM32_PMAP_H_ 70 71 #ifdef _KERNEL 72 73 #include <arm/cpuconf.h> 74 #include <arm/arm32/pte.h> 75 #ifndef _LOCORE 76 #if defined(_KERNEL_OPT) 77 #include "opt_arm32_pmap.h" 78 #endif 79 #include <arm/cpufunc.h> 80 #include <uvm/uvm_object.h> 81 #endif 82 83 #ifdef ARM_MMU_EXTENDED 84 #define PMAP_TLB_MAX 1 85 #define PMAP_TLB_HWPAGEWALKER 1 86 #define PMAP_TLB_NUM_PIDS 256 87 #define cpu_set_tlb_info(ci, ti) ((void)((ci)->ci_tlb_info = (ti))) 88 #if PMAP_TLB_MAX > 1 89 #define cpu_tlb_info(ci) ((ci)->ci_tlb_info) 90 #else 91 #define cpu_tlb_info(ci) (&pmap_tlb0_info) 92 #endif 93 #define pmap_md_tlb_asid_max() (PMAP_TLB_NUM_PIDS - 1) 94 #include <uvm/pmap/tlb.h> 95 #include <uvm/pmap/pmap_tlb.h> 96 97 /* 98 * If we have an EXTENDED MMU and the address space is split evenly between 99 * user and kernel, we can use the TTBR0/TTBR1 to have separate L1 tables for 100 * user and kernel address spaces. 101 */ 102 #if KERNEL_BASE != 0x80000000 103 #error ARMv6 or later systems must have a KERNEL_BASE of 0x8000000 104 #endif 105 #endif /* ARM_MMU_EXTENDED */ 106 107 /* 108 * a pmap describes a processes' 4GB virtual address space. this 109 * virtual address space can be broken up into 4096 1MB regions which 110 * are described by L1 PTEs in the L1 table. 111 * 112 * There is a line drawn at KERNEL_BASE. Everything below that line 113 * changes when the VM context is switched. Everything above that line 114 * is the same no matter which VM context is running. This is achieved 115 * by making the L1 PTEs for those slots above KERNEL_BASE reference 116 * kernel L2 tables. 117 * 118 * The basic layout of the virtual address space thus looks like this: 119 * 120 * 0xffffffff 121 * . 122 * . 123 * . 124 * KERNEL_BASE 125 * -------------------- 126 * . 127 * . 128 * . 129 * 0x00000000 130 */ 131 132 /* 133 * The number of L2 descriptor tables which can be tracked by an l2_dtable. 134 * A bucket size of 16 provides for 16MB of contiguous virtual address 135 * space per l2_dtable. Most processes will, therefore, require only two or 136 * three of these to map their whole working set. 137 */ 138 #define L2_BUCKET_XLOG2 (L1_S_SHIFT) 139 #define L2_BUCKET_XSIZE (1 << L2_BUCKET_XLOG2) 140 #define L2_BUCKET_LOG2 4 141 #define L2_BUCKET_SIZE (1 << L2_BUCKET_LOG2) 142 143 /* 144 * Given the above "L2-descriptors-per-l2_dtable" constant, the number 145 * of l2_dtable structures required to track all possible page descriptors 146 * mappable by an L1 translation table is given by the following constants: 147 */ 148 #define L2_LOG2 (32 - (L2_BUCKET_XLOG2 + L2_BUCKET_LOG2)) 149 #define L2_SIZE (1 << L2_LOG2) 150 151 /* 152 * tell MI code that the cache is virtually-indexed. 153 * ARMv6 is physically-tagged but all others are virtually-tagged. 154 */ 155 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 156 #define PMAP_CACHE_VIPT 157 #else 158 #define PMAP_CACHE_VIVT 159 #endif 160 161 #ifndef _LOCORE 162 163 #ifndef PMAP_MMU_EXTENDED 164 struct l1_ttable; 165 struct l2_dtable; 166 167 /* 168 * Track cache/tlb occupancy using the following structure 169 */ 170 union pmap_cache_state { 171 struct { 172 union { 173 uint8_t csu_cache_b[2]; 174 uint16_t csu_cache; 175 } cs_cache_u; 176 177 union { 178 uint8_t csu_tlb_b[2]; 179 uint16_t csu_tlb; 180 } cs_tlb_u; 181 } cs_s; 182 uint32_t cs_all; 183 }; 184 #define cs_cache_id cs_s.cs_cache_u.csu_cache_b[0] 185 #define cs_cache_d cs_s.cs_cache_u.csu_cache_b[1] 186 #define cs_cache cs_s.cs_cache_u.csu_cache 187 #define cs_tlb_id cs_s.cs_tlb_u.csu_tlb_b[0] 188 #define cs_tlb_d cs_s.cs_tlb_u.csu_tlb_b[1] 189 #define cs_tlb cs_s.cs_tlb_u.csu_tlb 190 191 /* 192 * Assigned to cs_all to force cacheops to work for a particular pmap 193 */ 194 #define PMAP_CACHE_STATE_ALL 0xffffffffu 195 #endif /* !ARM_MMU_EXTENDED */ 196 197 /* 198 * This structure is used by machine-dependent code to describe 199 * static mappings of devices, created at bootstrap time. 200 */ 201 struct pmap_devmap { 202 vaddr_t pd_va; /* virtual address */ 203 paddr_t pd_pa; /* physical address */ 204 psize_t pd_size; /* size of region */ 205 vm_prot_t pd_prot; /* protection code */ 206 int pd_cache; /* cache attributes */ 207 }; 208 209 /* 210 * The pmap structure itself 211 */ 212 struct pmap { 213 struct uvm_object pm_obj; 214 kmutex_t pm_obj_lock; 215 #define pm_lock pm_obj.vmobjlock 216 #ifndef ARM_HAS_VBAR 217 pd_entry_t *pm_pl1vec; 218 pd_entry_t pm_l1vec; 219 #endif 220 struct l2_dtable *pm_l2[L2_SIZE]; 221 struct pmap_statistics pm_stats; 222 LIST_ENTRY(pmap) pm_list; 223 #ifdef ARM_MMU_EXTENDED 224 pd_entry_t *pm_l1; 225 paddr_t pm_l1_pa; 226 bool pm_remove_all; 227 #ifdef MULTIPROCESSOR 228 kcpuset_t *pm_onproc; 229 kcpuset_t *pm_active; 230 struct pmap_asid_info pm_pai[2]; 231 #else 232 struct pmap_asid_info pm_pai[1]; 233 #endif 234 #else 235 struct l1_ttable *pm_l1; 236 union pmap_cache_state pm_cstate; 237 uint8_t pm_domain; 238 bool pm_activated; 239 bool pm_remove_all; 240 #endif 241 }; 242 243 struct pmap_kernel { 244 struct pmap kernel_pmap; 245 }; 246 247 /* 248 * Physical / virtual address structure. In a number of places (particularly 249 * during bootstrapping) we need to keep track of the physical and virtual 250 * addresses of various pages 251 */ 252 typedef struct pv_addr { 253 SLIST_ENTRY(pv_addr) pv_list; 254 paddr_t pv_pa; 255 vaddr_t pv_va; 256 vsize_t pv_size; 257 uint8_t pv_cache; 258 uint8_t pv_prot; 259 } pv_addr_t; 260 typedef SLIST_HEAD(, pv_addr) pv_addrqh_t; 261 262 extern pv_addrqh_t pmap_freeq; 263 extern pv_addr_t kernelstack; 264 extern pv_addr_t abtstack; 265 extern pv_addr_t fiqstack; 266 extern pv_addr_t irqstack; 267 extern pv_addr_t undstack; 268 extern pv_addr_t idlestack; 269 extern pv_addr_t systempage; 270 extern pv_addr_t kernel_l1pt; 271 272 /* 273 * Determine various modes for PTEs (user vs. kernel, cacheable 274 * vs. non-cacheable). 275 */ 276 #define PTE_KERNEL 0 277 #define PTE_USER 1 278 #define PTE_NOCACHE 0 279 #define PTE_CACHE 1 280 #define PTE_PAGETABLE 2 281 282 /* 283 * Flags that indicate attributes of pages or mappings of pages. 284 * 285 * The PVF_MOD and PVF_REF flags are stored in the mdpage for each 286 * page. PVF_WIRED, PVF_WRITE, and PVF_NC are kept in individual 287 * pv_entry's for each page. They live in the same "namespace" so 288 * that we can clear multiple attributes at a time. 289 * 290 * Note the "non-cacheable" flag generally means the page has 291 * multiple mappings in a given address space. 292 */ 293 #define PVF_MOD 0x01 /* page is modified */ 294 #define PVF_REF 0x02 /* page is referenced */ 295 #define PVF_WIRED 0x04 /* mapping is wired */ 296 #define PVF_WRITE 0x08 /* mapping is writable */ 297 #define PVF_EXEC 0x10 /* mapping is executable */ 298 #ifdef PMAP_CACHE_VIVT 299 #define PVF_UNC 0x20 /* mapping is 'user' non-cacheable */ 300 #define PVF_KNC 0x40 /* mapping is 'kernel' non-cacheable */ 301 #define PVF_NC (PVF_UNC|PVF_KNC) 302 #endif 303 #ifdef PMAP_CACHE_VIPT 304 #define PVF_NC 0x20 /* mapping is 'kernel' non-cacheable */ 305 #define PVF_MULTCLR 0x40 /* mapping is multi-colored */ 306 #endif 307 #define PVF_COLORED 0x80 /* page has or had a color */ 308 #define PVF_KENTRY 0x0100 /* page entered via pmap_kenter_pa */ 309 #define PVF_KMPAGE 0x0200 /* page is used for kmem */ 310 #define PVF_DIRTY 0x0400 /* page may have dirty cache lines */ 311 #define PVF_KMOD 0x0800 /* unmanaged page is modified */ 312 #define PVF_KWRITE (PVF_KENTRY|PVF_WRITE) 313 #define PVF_DMOD (PVF_MOD|PVF_KMOD|PVF_KMPAGE) 314 315 /* 316 * Commonly referenced structures 317 */ 318 extern int pmap_debug_level; /* Only exists if PMAP_DEBUG */ 319 extern int arm_poolpage_vmfreelist; 320 321 /* 322 * Macros that we need to export 323 */ 324 #define pmap_resident_count(pmap) ((pmap)->pm_stats.resident_count) 325 #define pmap_wired_count(pmap) ((pmap)->pm_stats.wired_count) 326 327 #define pmap_is_modified(pg) \ 328 (((pg)->mdpage.pvh_attrs & PVF_MOD) != 0) 329 #define pmap_is_referenced(pg) \ 330 (((pg)->mdpage.pvh_attrs & PVF_REF) != 0) 331 #define pmap_is_page_colored_p(md) \ 332 (((md)->pvh_attrs & PVF_COLORED) != 0) 333 334 #define pmap_copy(dp, sp, da, l, sa) /* nothing */ 335 336 #define pmap_phys_address(ppn) (arm_ptob((ppn))) 337 u_int arm32_mmap_flags(paddr_t); 338 #define ARM32_MMAP_WRITECOMBINE 0x40000000 339 #define ARM32_MMAP_CACHEABLE 0x20000000 340 #define pmap_mmap_flags(ppn) arm32_mmap_flags(ppn) 341 342 #define PMAP_PTE 0x10000000 /* kenter_pa */ 343 344 /* 345 * Functions that we need to export 346 */ 347 void pmap_procwr(struct proc *, vaddr_t, int); 348 void pmap_remove_all(pmap_t); 349 bool pmap_extract(pmap_t, vaddr_t, paddr_t *); 350 351 #define PMAP_NEED_PROCWR 352 #define PMAP_GROWKERNEL /* turn on pmap_growkernel interface */ 353 #define PMAP_ENABLE_PMAP_KMPAGE /* enable the PMAP_KMPAGE flag */ 354 355 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 356 #define PMAP_PREFER(hint, vap, sz, td) pmap_prefer((hint), (vap), (td)) 357 void pmap_prefer(vaddr_t, vaddr_t *, int); 358 #endif 359 360 void pmap_icache_sync_range(pmap_t, vaddr_t, vaddr_t); 361 362 /* Functions we use internally. */ 363 #ifdef PMAP_STEAL_MEMORY 364 void pmap_boot_pagealloc(psize_t, psize_t, psize_t, pv_addr_t *); 365 void pmap_boot_pageadd(pv_addr_t *); 366 vaddr_t pmap_steal_memory(vsize_t, vaddr_t *, vaddr_t *); 367 #endif 368 void pmap_bootstrap(vaddr_t, vaddr_t); 369 370 void pmap_do_remove(pmap_t, vaddr_t, vaddr_t, int); 371 int pmap_fault_fixup(pmap_t, vaddr_t, vm_prot_t, int); 372 int pmap_prefetchabt_fixup(void *); 373 bool pmap_get_pde_pte(pmap_t, vaddr_t, pd_entry_t **, pt_entry_t **); 374 bool pmap_get_pde(pmap_t, vaddr_t, pd_entry_t **); 375 struct pcb; 376 void pmap_set_pcb_pagedir(pmap_t, struct pcb *); 377 378 void pmap_debug(int); 379 void pmap_postinit(void); 380 381 void vector_page_setprot(int); 382 383 const struct pmap_devmap *pmap_devmap_find_pa(paddr_t, psize_t); 384 const struct pmap_devmap *pmap_devmap_find_va(vaddr_t, vsize_t); 385 386 /* Bootstrapping routines. */ 387 void pmap_map_section(vaddr_t, vaddr_t, paddr_t, int, int); 388 void pmap_map_entry(vaddr_t, vaddr_t, paddr_t, int, int); 389 vsize_t pmap_map_chunk(vaddr_t, vaddr_t, paddr_t, vsize_t, int, int); 390 void pmap_link_l2pt(vaddr_t, vaddr_t, pv_addr_t *); 391 void pmap_devmap_bootstrap(vaddr_t, const struct pmap_devmap *); 392 void pmap_devmap_register(const struct pmap_devmap *); 393 394 /* 395 * Special page zero routine for use by the idle loop (no cache cleans). 396 */ 397 bool pmap_pageidlezero(paddr_t); 398 #define PMAP_PAGEIDLEZERO(pa) pmap_pageidlezero((pa)) 399 400 /* 401 * used by dumpsys to record the PA of the L1 table 402 */ 403 uint32_t pmap_kernel_L1_addr(void); 404 /* 405 * The current top of kernel VM 406 */ 407 extern vaddr_t pmap_curmaxkvaddr; 408 409 /* 410 * Useful macros and constants 411 */ 412 413 /* Virtual address to page table entry */ 414 static inline pt_entry_t * 415 vtopte(vaddr_t va) 416 { 417 pd_entry_t *pdep; 418 pt_entry_t *ptep; 419 420 KASSERT(trunc_page(va) == va); 421 422 if (pmap_get_pde_pte(pmap_kernel(), va, &pdep, &ptep) == false) 423 return (NULL); 424 return (ptep); 425 } 426 427 /* 428 * Virtual address to physical address 429 */ 430 static inline paddr_t 431 vtophys(vaddr_t va) 432 { 433 paddr_t pa; 434 435 if (pmap_extract(pmap_kernel(), va, &pa) == false) 436 return (0); /* XXXSCW: Panic? */ 437 438 return (pa); 439 } 440 441 /* 442 * The new pmap ensures that page-tables are always mapping Write-Thru. 443 * Thus, on some platforms we can run fast and loose and avoid syncing PTEs 444 * on every change. 445 * 446 * Unfortunately, not all CPUs have a write-through cache mode. So we 447 * define PMAP_NEEDS_PTE_SYNC for C code to conditionally do PTE syncs, 448 * and if there is the chance for PTE syncs to be needed, we define 449 * PMAP_INCLUDE_PTE_SYNC so e.g. assembly code can include (and run) 450 * the code. 451 */ 452 extern int pmap_needs_pte_sync; 453 #if defined(_KERNEL_OPT) 454 /* 455 * StrongARM SA-1 caches do not have a write-through mode. So, on these, 456 * we need to do PTE syncs. If only SA-1 is configured, then evaluate 457 * this at compile time. 458 */ 459 #if (ARM_MMU_SA1 + ARM_MMU_V6 != 0) && (ARM_NMMUS == 1) 460 #define PMAP_INCLUDE_PTE_SYNC 461 #if (ARM_MMU_V6 > 0) 462 #define PMAP_NEEDS_PTE_SYNC 1 463 #elif (ARM_MMU_SA1 == 0) 464 #define PMAP_NEEDS_PTE_SYNC 0 465 #endif 466 #endif 467 #endif /* _KERNEL_OPT */ 468 469 /* 470 * Provide a fallback in case we were not able to determine it at 471 * compile-time. 472 */ 473 #ifndef PMAP_NEEDS_PTE_SYNC 474 #define PMAP_NEEDS_PTE_SYNC pmap_needs_pte_sync 475 #define PMAP_INCLUDE_PTE_SYNC 476 #endif 477 478 static inline void 479 pmap_ptesync(pt_entry_t *ptep, size_t cnt) 480 { 481 if (PMAP_NEEDS_PTE_SYNC) 482 cpu_dcache_wb_range((vaddr_t)ptep, cnt * sizeof(pt_entry_t)); 483 #if ARM_MMU_V7 > 0 484 __asm("dsb"); 485 #endif 486 } 487 488 #define PDE_SYNC(pdep) pmap_ptesync((pdep), 1) 489 #define PDE_SYNC_RANGE(pdep, cnt) pmap_ptesync((pdep), (cnt)) 490 #define PTE_SYNC(ptep) pmap_ptesync((ptep), PAGE_SIZE / L2_S_SIZE) 491 #define PTE_SYNC_RANGE(ptep, cnt) pmap_ptesync((ptep), (cnt)) 492 493 #define l1pte_valid_p(pde) ((pde) != 0) 494 #define l1pte_section_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_S) 495 #define l1pte_supersection_p(pde) (l1pte_section_p(pde) \ 496 && ((pde) & L1_S_V6_SUPER) != 0) 497 #define l1pte_page_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_C) 498 #define l1pte_fpage_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_F) 499 #define l1pte_pa(pde) ((pde) & L1_C_ADDR_MASK) 500 #define l1pte_index(v) ((vaddr_t)(v) >> L1_S_SHIFT) 501 #define l1pte_pgindex(v) l1pte_index((v) & L1_ADDR_BITS \ 502 & ~(PAGE_SIZE * PAGE_SIZE / sizeof(pt_entry_t) - 1)) 503 504 static inline void 505 l1pte_setone(pt_entry_t *pdep, pt_entry_t pde) 506 { 507 *pdep = pde; 508 } 509 510 static inline void 511 l1pte_set(pt_entry_t *pdep, pt_entry_t pde) 512 { 513 *pdep = pde; 514 if (l1pte_page_p(pde)) { 515 KASSERTMSG((((uintptr_t)pdep / sizeof(pde)) & (PAGE_SIZE / L2_T_SIZE - 1)) == 0, "%p", pdep); 516 for (size_t k = 1; k < PAGE_SIZE / L2_T_SIZE; k++) { 517 pde += L2_T_SIZE; 518 pdep[k] = pde; 519 } 520 } else if (l1pte_supersection_p(pde)) { 521 KASSERTMSG((((uintptr_t)pdep / sizeof(pde)) & (L1_SS_SIZE / L1_S_SIZE - 1)) == 0, "%p", pdep); 522 for (size_t k = 1; k < L1_SS_SIZE / L1_S_SIZE; k++) { 523 pdep[k] = pde; 524 } 525 } 526 } 527 528 #define l2pte_index(v) ((((v) & L2_ADDR_BITS) >> PGSHIFT) << (PGSHIFT-L2_S_SHIFT)) 529 #define l2pte_valid_p(pte) (((pte) & L2_TYPE_MASK) != L2_TYPE_INV) 530 #define l2pte_pa(pte) ((pte) & L2_S_FRAME) 531 #define l1pte_lpage_p(pte) (((pte) & L2_TYPE_MASK) == L2_TYPE_L) 532 #define l2pte_minidata_p(pte) (((pte) & \ 533 (L2_B | L2_C | L2_XS_T_TEX(TEX_XSCALE_X)))\ 534 == (L2_C | L2_XS_T_TEX(TEX_XSCALE_X))) 535 536 static inline void 537 l2pte_set(pt_entry_t *ptep, pt_entry_t pte, pt_entry_t opte) 538 { 539 for (size_t k = 0; k < PAGE_SIZE / L2_S_SIZE; k++) { 540 KASSERTMSG(*ptep == opte, "%#x [*%p] != %#x", *ptep, ptep, opte); 541 *ptep++ = pte; 542 pte += L2_S_SIZE; 543 if (opte) 544 opte += L2_S_SIZE; 545 } 546 } 547 548 static inline void 549 l2pte_reset(pt_entry_t *ptep) 550 { 551 *ptep = 0; 552 for (vsize_t k = 1; k < PAGE_SIZE / L2_S_SIZE; k++) { 553 ptep[k] = 0; 554 } 555 } 556 557 /* L1 and L2 page table macros */ 558 #define pmap_pde_v(pde) l1pte_valid(*(pde)) 559 #define pmap_pde_section(pde) l1pte_section_p(*(pde)) 560 #define pmap_pde_supersection(pde) l1pte_supersection_p(*(pde)) 561 #define pmap_pde_page(pde) l1pte_page_p(*(pde)) 562 #define pmap_pde_fpage(pde) l1pte_fpage_p(*(pde)) 563 564 #define pmap_pte_v(pte) l2pte_valid_p(*(pte)) 565 #define pmap_pte_pa(pte) l2pte_pa(*(pte)) 566 567 /* Size of the kernel part of the L1 page table */ 568 #define KERNEL_PD_SIZE \ 569 (L1_TABLE_SIZE - (KERNEL_BASE >> L1_S_SHIFT) * sizeof(pd_entry_t)) 570 571 void bzero_page(vaddr_t); 572 void bcopy_page(vaddr_t, vaddr_t); 573 574 #ifdef FPU_VFP 575 void bzero_page_vfp(vaddr_t); 576 void bcopy_page_vfp(vaddr_t, vaddr_t); 577 #endif 578 579 /************************* ARM MMU configuration *****************************/ 580 581 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 582 void pmap_copy_page_generic(paddr_t, paddr_t); 583 void pmap_zero_page_generic(paddr_t); 584 585 void pmap_pte_init_generic(void); 586 #if defined(CPU_ARM8) 587 void pmap_pte_init_arm8(void); 588 #endif 589 #if defined(CPU_ARM9) 590 void pmap_pte_init_arm9(void); 591 #endif /* CPU_ARM9 */ 592 #if defined(CPU_ARM10) 593 void pmap_pte_init_arm10(void); 594 #endif /* CPU_ARM10 */ 595 #if defined(CPU_ARM11) /* ARM_MMU_V6 */ 596 void pmap_pte_init_arm11(void); 597 #endif /* CPU_ARM11 */ 598 #if defined(CPU_ARM11MPCORE) /* ARM_MMU_V6 */ 599 void pmap_pte_init_arm11mpcore(void); 600 #endif 601 #if ARM_MMU_V7 == 1 602 void pmap_pte_init_armv7(void); 603 #endif /* ARM_MMU_V7 */ 604 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */ 605 606 #if ARM_MMU_SA1 == 1 607 void pmap_pte_init_sa1(void); 608 #endif /* ARM_MMU_SA1 == 1 */ 609 610 #if ARM_MMU_XSCALE == 1 611 void pmap_copy_page_xscale(paddr_t, paddr_t); 612 void pmap_zero_page_xscale(paddr_t); 613 614 void pmap_pte_init_xscale(void); 615 616 void xscale_setup_minidata(vaddr_t, vaddr_t, paddr_t); 617 618 #define PMAP_UAREA(va) pmap_uarea(va) 619 void pmap_uarea(vaddr_t); 620 #endif /* ARM_MMU_XSCALE == 1 */ 621 622 extern pt_entry_t pte_l1_s_cache_mode; 623 extern pt_entry_t pte_l1_s_cache_mask; 624 625 extern pt_entry_t pte_l2_l_cache_mode; 626 extern pt_entry_t pte_l2_l_cache_mask; 627 628 extern pt_entry_t pte_l2_s_cache_mode; 629 extern pt_entry_t pte_l2_s_cache_mask; 630 631 extern pt_entry_t pte_l1_s_cache_mode_pt; 632 extern pt_entry_t pte_l2_l_cache_mode_pt; 633 extern pt_entry_t pte_l2_s_cache_mode_pt; 634 635 extern pt_entry_t pte_l1_s_wc_mode; 636 extern pt_entry_t pte_l2_l_wc_mode; 637 extern pt_entry_t pte_l2_s_wc_mode; 638 639 extern pt_entry_t pte_l1_s_prot_u; 640 extern pt_entry_t pte_l1_s_prot_w; 641 extern pt_entry_t pte_l1_s_prot_ro; 642 extern pt_entry_t pte_l1_s_prot_mask; 643 644 extern pt_entry_t pte_l2_s_prot_u; 645 extern pt_entry_t pte_l2_s_prot_w; 646 extern pt_entry_t pte_l2_s_prot_ro; 647 extern pt_entry_t pte_l2_s_prot_mask; 648 649 extern pt_entry_t pte_l2_l_prot_u; 650 extern pt_entry_t pte_l2_l_prot_w; 651 extern pt_entry_t pte_l2_l_prot_ro; 652 extern pt_entry_t pte_l2_l_prot_mask; 653 654 extern pt_entry_t pte_l1_ss_proto; 655 extern pt_entry_t pte_l1_s_proto; 656 extern pt_entry_t pte_l1_c_proto; 657 extern pt_entry_t pte_l2_s_proto; 658 659 extern void (*pmap_copy_page_func)(paddr_t, paddr_t); 660 extern void (*pmap_zero_page_func)(paddr_t); 661 662 #endif /* !_LOCORE */ 663 664 /*****************************************************************************/ 665 666 #define KERNEL_PID 0 /* The kernel uses ASID 0 */ 667 668 /* 669 * Definitions for MMU domains 670 */ 671 #define PMAP_DOMAINS 15 /* 15 'user' domains (1-15) */ 672 #define PMAP_DOMAIN_KERNEL 0 /* The kernel pmap uses domain #0 */ 673 #ifdef ARM_MMU_EXTENDED 674 #define PMAP_DOMAIN_USER 1 /* User pmaps use domain #1 */ 675 #endif 676 677 /* 678 * These macros define the various bit masks in the PTE. 679 * 680 * We use these macros since we use different bits on different processor 681 * models. 682 */ 683 #define L1_S_PROT_U_generic (L1_S_AP(AP_U)) 684 #define L1_S_PROT_W_generic (L1_S_AP(AP_W)) 685 #define L1_S_PROT_RO_generic (0) 686 #define L1_S_PROT_MASK_generic (L1_S_PROT_U|L1_S_PROT_W|L1_S_PROT_RO) 687 688 #define L1_S_PROT_U_xscale (L1_S_AP(AP_U)) 689 #define L1_S_PROT_W_xscale (L1_S_AP(AP_W)) 690 #define L1_S_PROT_RO_xscale (0) 691 #define L1_S_PROT_MASK_xscale (L1_S_PROT_U|L1_S_PROT_W|L1_S_PROT_RO) 692 693 #define L1_S_PROT_U_armv6 (L1_S_AP(AP_R) | L1_S_AP(AP_U)) 694 #define L1_S_PROT_W_armv6 (L1_S_AP(AP_W)) 695 #define L1_S_PROT_RO_armv6 (L1_S_AP(AP_R) | L1_S_AP(AP_RO)) 696 #define L1_S_PROT_MASK_armv6 (L1_S_PROT_U|L1_S_PROT_W|L1_S_PROT_RO) 697 698 #define L1_S_PROT_U_armv7 (L1_S_AP(AP_R) | L1_S_AP(AP_U)) 699 #define L1_S_PROT_W_armv7 (L1_S_AP(AP_W)) 700 #define L1_S_PROT_RO_armv7 (L1_S_AP(AP_R) | L1_S_AP(AP_RO)) 701 #define L1_S_PROT_MASK_armv7 (L1_S_PROT_U|L1_S_PROT_W|L1_S_PROT_RO) 702 703 #define L1_S_CACHE_MASK_generic (L1_S_B|L1_S_C) 704 #define L1_S_CACHE_MASK_xscale (L1_S_B|L1_S_C|L1_S_XS_TEX(TEX_XSCALE_X)) 705 #define L1_S_CACHE_MASK_armv6 (L1_S_B|L1_S_C|L1_S_XS_TEX(TEX_ARMV6_TEX)) 706 #define L1_S_CACHE_MASK_armv7 (L1_S_B|L1_S_C|L1_S_XS_TEX(TEX_ARMV6_TEX)|L1_S_V6_S) 707 708 #define L2_L_PROT_U_generic (L2_AP(AP_U)) 709 #define L2_L_PROT_W_generic (L2_AP(AP_W)) 710 #define L2_L_PROT_RO_generic (0) 711 #define L2_L_PROT_MASK_generic (L2_L_PROT_U|L2_L_PROT_W|L2_L_PROT_RO) 712 713 #define L2_L_PROT_U_xscale (L2_AP(AP_U)) 714 #define L2_L_PROT_W_xscale (L2_AP(AP_W)) 715 #define L2_L_PROT_RO_xscale (0) 716 #define L2_L_PROT_MASK_xscale (L2_L_PROT_U|L2_L_PROT_W|L2_L_PROT_RO) 717 718 #define L2_L_PROT_U_armv6n (L2_AP0(AP_R) | L2_AP0(AP_U)) 719 #define L2_L_PROT_W_armv6n (L2_AP0(AP_W)) 720 #define L2_L_PROT_RO_armv6n (L2_AP0(AP_R) | L2_AP0(AP_RO)) 721 #define L2_L_PROT_MASK_armv6n (L2_L_PROT_U|L2_L_PROT_W|L2_L_PROT_RO) 722 723 #define L2_L_PROT_U_armv7 (L2_AP0(AP_R) | L2_AP0(AP_U)) 724 #define L2_L_PROT_W_armv7 (L2_AP0(AP_W)) 725 #define L2_L_PROT_RO_armv7 (L2_AP0(AP_R) | L2_AP0(AP_RO)) 726 #define L2_L_PROT_MASK_armv7 (L2_L_PROT_U|L2_L_PROT_W|L2_L_PROT_RO) 727 728 #define L2_L_CACHE_MASK_generic (L2_B|L2_C) 729 #define L2_L_CACHE_MASK_xscale (L2_B|L2_C|L2_XS_L_TEX(TEX_XSCALE_X)) 730 #define L2_L_CACHE_MASK_armv6 (L2_B|L2_C|L2_V6_L_TEX(TEX_ARMV6_TEX)) 731 #define L2_L_CACHE_MASK_armv7 (L2_B|L2_C|L2_V6_L_TEX(TEX_ARMV6_TEX)|L2_XS_S) 732 733 #define L2_S_PROT_U_generic (L2_AP(AP_U)) 734 #define L2_S_PROT_W_generic (L2_AP(AP_W)) 735 #define L2_S_PROT_RO_generic (0) 736 #define L2_S_PROT_MASK_generic (L2_S_PROT_U|L2_S_PROT_W|L2_S_PROT_RO) 737 738 #define L2_S_PROT_U_xscale (L2_AP0(AP_U)) 739 #define L2_S_PROT_W_xscale (L2_AP0(AP_W)) 740 #define L2_S_PROT_RO_xscale (0) 741 #define L2_S_PROT_MASK_xscale (L2_S_PROT_U|L2_S_PROT_W|L2_S_PROT_RO) 742 743 #define L2_S_PROT_U_armv6n (L2_AP0(AP_R) | L2_AP0(AP_U)) 744 #define L2_S_PROT_W_armv6n (L2_AP0(AP_W)) 745 #define L2_S_PROT_RO_armv6n (L2_AP0(AP_R) | L2_AP0(AP_RO)) 746 #define L2_S_PROT_MASK_armv6n (L2_S_PROT_U|L2_S_PROT_W|L2_S_PROT_RO) 747 748 #define L2_S_PROT_U_armv7 (L2_AP0(AP_R) | L2_AP0(AP_U)) 749 #define L2_S_PROT_W_armv7 (L2_AP0(AP_W)) 750 #define L2_S_PROT_RO_armv7 (L2_AP0(AP_R) | L2_AP0(AP_RO)) 751 #define L2_S_PROT_MASK_armv7 (L2_S_PROT_U|L2_S_PROT_W|L2_S_PROT_RO) 752 753 #define L2_S_CACHE_MASK_generic (L2_B|L2_C) 754 #define L2_S_CACHE_MASK_xscale (L2_B|L2_C|L2_XS_T_TEX(TEX_XSCALE_X)) 755 #define L2_XS_CACHE_MASK_armv6 (L2_B|L2_C|L2_V6_XS_TEX(TEX_ARMV6_TEX)) 756 #define L2_S_CACHE_MASK_armv6n L2_XS_CACHE_MASK_armv6 757 #ifdef ARMV6_EXTENDED_SMALL_PAGE 758 #define L2_S_CACHE_MASK_armv6c L2_XS_CACHE_MASK_armv6 759 #else 760 #define L2_S_CACHE_MASK_armv6c L2_S_CACHE_MASK_generic 761 #endif 762 #define L2_S_CACHE_MASK_armv7 (L2_B|L2_C|L2_V6_XS_TEX(TEX_ARMV6_TEX)|L2_XS_S) 763 764 765 #define L1_S_PROTO_generic (L1_TYPE_S | L1_S_IMP) 766 #define L1_S_PROTO_xscale (L1_TYPE_S) 767 #define L1_S_PROTO_armv6 (L1_TYPE_S) 768 #define L1_S_PROTO_armv7 (L1_TYPE_S) 769 770 #define L1_SS_PROTO_generic 0 771 #define L1_SS_PROTO_xscale 0 772 #define L1_SS_PROTO_armv6 (L1_TYPE_S | L1_S_V6_SS) 773 #define L1_SS_PROTO_armv7 (L1_TYPE_S | L1_S_V6_SS) 774 775 #define L1_C_PROTO_generic (L1_TYPE_C | L1_C_IMP2) 776 #define L1_C_PROTO_xscale (L1_TYPE_C) 777 #define L1_C_PROTO_armv6 (L1_TYPE_C) 778 #define L1_C_PROTO_armv7 (L1_TYPE_C) 779 780 #define L2_L_PROTO (L2_TYPE_L) 781 782 #define L2_S_PROTO_generic (L2_TYPE_S) 783 #define L2_S_PROTO_xscale (L2_TYPE_XS) 784 #ifdef ARMV6_EXTENDED_SMALL_PAGE 785 #define L2_S_PROTO_armv6c (L2_TYPE_XS) /* XP=0, extended small page */ 786 #else 787 #define L2_S_PROTO_armv6c (L2_TYPE_S) /* XP=0, subpage APs */ 788 #endif 789 #define L2_S_PROTO_armv6n (L2_TYPE_S) /* with XP=1 */ 790 #ifdef ARM_MMU_EXTENDED 791 #define L2_S_PROTO_armv7 (L2_TYPE_S|L2_XS_XN) 792 #else 793 #define L2_S_PROTO_armv7 (L2_TYPE_S) 794 #endif 795 796 /* 797 * User-visible names for the ones that vary with MMU class. 798 */ 799 800 #if ARM_NMMUS > 1 801 /* More than one MMU class configured; use variables. */ 802 #define L1_S_PROT_U pte_l1_s_prot_u 803 #define L1_S_PROT_W pte_l1_s_prot_w 804 #define L1_S_PROT_RO pte_l1_s_prot_ro 805 #define L1_S_PROT_MASK pte_l1_s_prot_mask 806 807 #define L2_S_PROT_U pte_l2_s_prot_u 808 #define L2_S_PROT_W pte_l2_s_prot_w 809 #define L2_S_PROT_RO pte_l2_s_prot_ro 810 #define L2_S_PROT_MASK pte_l2_s_prot_mask 811 812 #define L2_L_PROT_U pte_l2_l_prot_u 813 #define L2_L_PROT_W pte_l2_l_prot_w 814 #define L2_L_PROT_RO pte_l2_l_prot_ro 815 #define L2_L_PROT_MASK pte_l2_l_prot_mask 816 817 #define L1_S_CACHE_MASK pte_l1_s_cache_mask 818 #define L2_L_CACHE_MASK pte_l2_l_cache_mask 819 #define L2_S_CACHE_MASK pte_l2_s_cache_mask 820 821 #define L1_SS_PROTO pte_l1_ss_proto 822 #define L1_S_PROTO pte_l1_s_proto 823 #define L1_C_PROTO pte_l1_c_proto 824 #define L2_S_PROTO pte_l2_s_proto 825 826 #define pmap_copy_page(s, d) (*pmap_copy_page_func)((s), (d)) 827 #define pmap_zero_page(d) (*pmap_zero_page_func)((d)) 828 #elif (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 829 #define L1_S_PROT_U L1_S_PROT_U_generic 830 #define L1_S_PROT_W L1_S_PROT_W_generic 831 #define L1_S_PROT_RO L1_S_PROT_RO_generic 832 #define L1_S_PROT_MASK L1_S_PROT_MASK_generic 833 834 #define L2_S_PROT_U L2_S_PROT_U_generic 835 #define L2_S_PROT_W L2_S_PROT_W_generic 836 #define L2_S_PROT_RO L2_S_PROT_RO_generic 837 #define L2_S_PROT_MASK L2_S_PROT_MASK_generic 838 839 #define L2_L_PROT_U L2_L_PROT_U_generic 840 #define L2_L_PROT_W L2_L_PROT_W_generic 841 #define L2_L_PROT_RO L2_L_PROT_RO_generic 842 #define L2_L_PROT_MASK L2_L_PROT_MASK_generic 843 844 #define L1_S_CACHE_MASK L1_S_CACHE_MASK_generic 845 #define L2_L_CACHE_MASK L2_L_CACHE_MASK_generic 846 #define L2_S_CACHE_MASK L2_S_CACHE_MASK_generic 847 848 #define L1_SS_PROTO L1_SS_PROTO_generic 849 #define L1_S_PROTO L1_S_PROTO_generic 850 #define L1_C_PROTO L1_C_PROTO_generic 851 #define L2_S_PROTO L2_S_PROTO_generic 852 853 #define pmap_copy_page(s, d) pmap_copy_page_generic((s), (d)) 854 #define pmap_zero_page(d) pmap_zero_page_generic((d)) 855 #elif ARM_MMU_V6N != 0 856 #define L1_S_PROT_U L1_S_PROT_U_armv6 857 #define L1_S_PROT_W L1_S_PROT_W_armv6 858 #define L1_S_PROT_RO L1_S_PROT_RO_armv6 859 #define L1_S_PROT_MASK L1_S_PROT_MASK_armv6 860 861 #define L2_S_PROT_U L2_S_PROT_U_armv6n 862 #define L2_S_PROT_W L2_S_PROT_W_armv6n 863 #define L2_S_PROT_RO L2_S_PROT_RO_armv6n 864 #define L2_S_PROT_MASK L2_S_PROT_MASK_armv6n 865 866 #define L2_L_PROT_U L2_L_PROT_U_armv6n 867 #define L2_L_PROT_W L2_L_PROT_W_armv6n 868 #define L2_L_PROT_RO L2_L_PROT_RO_armv6n 869 #define L2_L_PROT_MASK L2_L_PROT_MASK_armv6n 870 871 #define L1_S_CACHE_MASK L1_S_CACHE_MASK_armv6 872 #define L2_L_CACHE_MASK L2_L_CACHE_MASK_armv6 873 #define L2_S_CACHE_MASK L2_S_CACHE_MASK_armv6n 874 875 /* These prototypes make writeable mappings, while the other MMU types 876 * make read-only mappings. */ 877 #define L1_SS_PROTO L1_SS_PROTO_armv6 878 #define L1_S_PROTO L1_S_PROTO_armv6 879 #define L1_C_PROTO L1_C_PROTO_armv6 880 #define L2_S_PROTO L2_S_PROTO_armv6n 881 882 #define pmap_copy_page(s, d) pmap_copy_page_generic((s), (d)) 883 #define pmap_zero_page(d) pmap_zero_page_generic((d)) 884 #elif ARM_MMU_V6C != 0 885 #define L1_S_PROT_U L1_S_PROT_U_generic 886 #define L1_S_PROT_W L1_S_PROT_W_generic 887 #define L1_S_PROT_RO L1_S_PROT_RO_generic 888 #define L1_S_PROT_MASK L1_S_PROT_MASK_generic 889 890 #define L2_S_PROT_U L2_S_PROT_U_generic 891 #define L2_S_PROT_W L2_S_PROT_W_generic 892 #define L2_S_PROT_RO L2_S_PROT_RO_generic 893 #define L2_S_PROT_MASK L2_S_PROT_MASK_generic 894 895 #define L2_L_PROT_U L2_L_PROT_U_generic 896 #define L2_L_PROT_W L2_L_PROT_W_generic 897 #define L2_L_PROT_RO L2_L_PROT_RO_generic 898 #define L2_L_PROT_MASK L2_L_PROT_MASK_generic 899 900 #define L1_S_CACHE_MASK L1_S_CACHE_MASK_generic 901 #define L2_L_CACHE_MASK L2_L_CACHE_MASK_generic 902 #define L2_S_CACHE_MASK L2_S_CACHE_MASK_generic 903 904 #define L1_SS_PROTO L1_SS_PROTO_generic 905 #define L1_S_PROTO L1_S_PROTO_generic 906 #define L1_C_PROTO L1_C_PROTO_generic 907 #define L2_S_PROTO L2_S_PROTO_generic 908 909 #define pmap_copy_page(s, d) pmap_copy_page_generic((s), (d)) 910 #define pmap_zero_page(d) pmap_zero_page_generic((d)) 911 #elif ARM_MMU_XSCALE == 1 912 #define L1_S_PROT_U L1_S_PROT_U_generic 913 #define L1_S_PROT_W L1_S_PROT_W_generic 914 #define L1_S_PROT_RO L1_S_PROT_RO_generic 915 #define L1_S_PROT_MASK L1_S_PROT_MASK_generic 916 917 #define L2_S_PROT_U L2_S_PROT_U_xscale 918 #define L2_S_PROT_W L2_S_PROT_W_xscale 919 #define L2_S_PROT_RO L2_S_PROT_RO_xscale 920 #define L2_S_PROT_MASK L2_S_PROT_MASK_xscale 921 922 #define L2_L_PROT_U L2_L_PROT_U_generic 923 #define L2_L_PROT_W L2_L_PROT_W_generic 924 #define L2_L_PROT_RO L2_L_PROT_RO_generic 925 #define L2_L_PROT_MASK L2_L_PROT_MASK_generic 926 927 #define L1_S_CACHE_MASK L1_S_CACHE_MASK_xscale 928 #define L2_L_CACHE_MASK L2_L_CACHE_MASK_xscale 929 #define L2_S_CACHE_MASK L2_S_CACHE_MASK_xscale 930 931 #define L1_SS_PROTO L1_SS_PROTO_xscale 932 #define L1_S_PROTO L1_S_PROTO_xscale 933 #define L1_C_PROTO L1_C_PROTO_xscale 934 #define L2_S_PROTO L2_S_PROTO_xscale 935 936 #define pmap_copy_page(s, d) pmap_copy_page_xscale((s), (d)) 937 #define pmap_zero_page(d) pmap_zero_page_xscale((d)) 938 #elif ARM_MMU_V7 == 1 939 #define L1_S_PROT_U L1_S_PROT_U_armv7 940 #define L1_S_PROT_W L1_S_PROT_W_armv7 941 #define L1_S_PROT_RO L1_S_PROT_RO_armv7 942 #define L1_S_PROT_MASK L1_S_PROT_MASK_armv7 943 944 #define L2_S_PROT_U L2_S_PROT_U_armv7 945 #define L2_S_PROT_W L2_S_PROT_W_armv7 946 #define L2_S_PROT_RO L2_S_PROT_RO_armv7 947 #define L2_S_PROT_MASK L2_S_PROT_MASK_armv7 948 949 #define L2_L_PROT_U L2_L_PROT_U_armv7 950 #define L2_L_PROT_W L2_L_PROT_W_armv7 951 #define L2_L_PROT_RO L2_L_PROT_RO_armv7 952 #define L2_L_PROT_MASK L2_L_PROT_MASK_armv7 953 954 #define L1_S_CACHE_MASK L1_S_CACHE_MASK_armv7 955 #define L2_L_CACHE_MASK L2_L_CACHE_MASK_armv7 956 #define L2_S_CACHE_MASK L2_S_CACHE_MASK_armv7 957 958 /* These prototypes make writeable mappings, while the other MMU types 959 * make read-only mappings. */ 960 #define L1_SS_PROTO L1_SS_PROTO_armv7 961 #define L1_S_PROTO L1_S_PROTO_armv7 962 #define L1_C_PROTO L1_C_PROTO_armv7 963 #define L2_S_PROTO L2_S_PROTO_armv7 964 965 #define pmap_copy_page(s, d) pmap_copy_page_generic((s), (d)) 966 #define pmap_zero_page(d) pmap_zero_page_generic((d)) 967 #endif /* ARM_NMMUS > 1 */ 968 969 /* 970 * Macros to set and query the write permission on page descriptors. 971 */ 972 #define l1pte_set_writable(pte) (((pte) & ~L1_S_PROT_RO) | L1_S_PROT_W) 973 #define l1pte_set_readonly(pte) (((pte) & ~L1_S_PROT_W) | L1_S_PROT_RO) 974 #define l2pte_set_writable(pte) (((pte) & ~L2_S_PROT_RO) | L2_S_PROT_W) 975 #define l2pte_set_readonly(pte) (((pte) & ~L2_S_PROT_W) | L2_S_PROT_RO) 976 977 #define l2pte_writable_p(pte) (((pte) & L2_S_PROT_W) == L2_S_PROT_W && \ 978 (L2_S_PROT_RO == 0 || \ 979 ((pte) & L2_S_PROT_RO) != L2_S_PROT_RO)) 980 981 /* 982 * These macros return various bits based on kernel/user and protection. 983 * Note that the compiler will usually fold these at compile time. 984 */ 985 #define L1_S_PROT(ku, pr) ((((ku) == PTE_USER) ? L1_S_PROT_U : 0) | \ 986 (((pr) & VM_PROT_WRITE) ? L1_S_PROT_W : L1_S_PROT_RO)) 987 988 #define L2_L_PROT(ku, pr) ((((ku) == PTE_USER) ? L2_L_PROT_U : 0) | \ 989 (((pr) & VM_PROT_WRITE) ? L2_L_PROT_W : L2_L_PROT_RO)) 990 991 #define L2_S_PROT(ku, pr) ((((ku) == PTE_USER) ? L2_S_PROT_U : 0) | \ 992 (((pr) & VM_PROT_WRITE) ? L2_S_PROT_W : L2_S_PROT_RO)) 993 994 /* 995 * Macros to test if a mapping is mappable with an L1 SuperSection, 996 * L1 Section, or an L2 Large Page mapping. 997 */ 998 #define L1_SS_MAPPABLE_P(va, pa, size) \ 999 ((((va) | (pa)) & L1_SS_OFFSET) == 0 && (size) >= L1_SS_SIZE) 1000 1001 #define L1_S_MAPPABLE_P(va, pa, size) \ 1002 ((((va) | (pa)) & L1_S_OFFSET) == 0 && (size) >= L1_S_SIZE) 1003 1004 #define L2_L_MAPPABLE_P(va, pa, size) \ 1005 ((((va) | (pa)) & L2_L_OFFSET) == 0 && (size) >= L2_L_SIZE) 1006 1007 #ifndef _LOCORE 1008 /* 1009 * Hooks for the pool allocator. 1010 */ 1011 #define POOL_VTOPHYS(va) vtophys((vaddr_t) (va)) 1012 extern paddr_t physical_start, physical_end; 1013 #ifdef PMAP_NEED_ALLOC_POOLPAGE 1014 struct vm_page *arm_pmap_alloc_poolpage(int); 1015 #define PMAP_ALLOC_POOLPAGE arm_pmap_alloc_poolpage 1016 #endif 1017 #if defined(PMAP_NEED_ALLOC_POOLPAGE) || defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) 1018 #define PMAP_MAP_POOLPAGE(pa) \ 1019 ((vaddr_t)((paddr_t)(pa) - physical_start + KERNEL_BASE)) 1020 #define PMAP_UNMAP_POOLPAGE(va) \ 1021 ((paddr_t)((vaddr_t)(va) - KERNEL_BASE + physical_start)) 1022 #endif 1023 1024 /* 1025 * pmap-specific data store in the vm_page structure. 1026 */ 1027 #define __HAVE_VM_PAGE_MD 1028 struct vm_page_md { 1029 SLIST_HEAD(,pv_entry) pvh_list; /* pv_entry list */ 1030 int pvh_attrs; /* page attributes */ 1031 u_int uro_mappings; 1032 u_int urw_mappings; 1033 union { 1034 u_short s_mappings[2]; /* Assume kernel count <= 65535 */ 1035 u_int i_mappings; 1036 } k_u; 1037 #define kro_mappings k_u.s_mappings[0] 1038 #define krw_mappings k_u.s_mappings[1] 1039 #define k_mappings k_u.i_mappings 1040 }; 1041 1042 /* 1043 * Set the default color of each page. 1044 */ 1045 #if ARM_MMU_V6 > 0 1046 #define VM_MDPAGE_PVH_ATTRS_INIT(pg) \ 1047 (pg)->mdpage.pvh_attrs = (pg)->phys_addr & arm_cache_prefer_mask 1048 #else 1049 #define VM_MDPAGE_PVH_ATTRS_INIT(pg) \ 1050 (pg)->mdpage.pvh_attrs = 0 1051 #endif 1052 1053 #define VM_MDPAGE_INIT(pg) \ 1054 do { \ 1055 SLIST_INIT(&(pg)->mdpage.pvh_list); \ 1056 VM_MDPAGE_PVH_ATTRS_INIT(pg); \ 1057 (pg)->mdpage.uro_mappings = 0; \ 1058 (pg)->mdpage.urw_mappings = 0; \ 1059 (pg)->mdpage.k_mappings = 0; \ 1060 } while (/*CONSTCOND*/0) 1061 1062 #endif /* !_LOCORE */ 1063 1064 #endif /* _KERNEL */ 1065 1066 #endif /* _ARM32_PMAP_H_ */ 1067
Indexes created Thu Sep 25 16:09:42 GMT 2025