pmap.h revision 1.137
1 /* $NetBSD: pmap.h,v 1.137 2014/11/08 17:18:22 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2002, 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe & Steve C. Woodford for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Copyright (c) 1994,1995 Mark Brinicombe. 40 * All rights reserved. 41 * 42 * Redistribution and use in source and binary forms, with or without 43 * modification, are permitted provided that the following conditions 44 * are met: 45 * 1. Redistributions of source code must retain the above copyright 46 * notice, this list of conditions and the following disclaimer. 47 * 2. Redistributions in binary form must reproduce the above copyright 48 * notice, this list of conditions and the following disclaimer in the 49 * documentation and/or other materials provided with the distribution. 50 * 3. All advertising materials mentioning features or use of this software 51 * must display the following acknowledgement: 52 * This product includes software developed by Mark Brinicombe 53 * 4. The name of the author may not be used to endorse or promote products 54 * derived from this software without specific prior written permission. 55 * 56 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 57 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 58 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 59 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 60 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 61 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 62 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 63 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 64 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 65 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 #ifndef _ARM32_PMAP_H_ 69 #define _ARM32_PMAP_H_ 70 71 #ifdef _KERNEL 72 73 #include <arm/cpuconf.h> 74 #include <arm/arm32/pte.h> 75 #ifndef _LOCORE 76 #if defined(_KERNEL_OPT) 77 #include "opt_arm32_pmap.h" 78 #include "opt_multiprocessor.h" 79 #endif 80 #include <arm/cpufunc.h> 81 #include <uvm/uvm_object.h> 82 #endif 83 84 #ifdef ARM_MMU_EXTENDED 85 #define PMAP_TLB_MAX 1 86 #define PMAP_TLB_HWPAGEWALKER 1 87 #if PMAP_TLB_MAX > 1 88 #define PMAP_NEED_TLB_SHOOTDOWN 1 89 #endif 90 #define PMAP_TLB_FLUSH_ASID_ON_RESET (arm_has_tlbiasid_p) 91 #define PMAP_TLB_NUM_PIDS 256 92 #define cpu_set_tlb_info(ci, ti) ((void)((ci)->ci_tlb_info = (ti))) 93 #if PMAP_TLB_MAX > 1 94 #define cpu_tlb_info(ci) ((ci)->ci_tlb_info) 95 #else 96 #define cpu_tlb_info(ci) (&pmap_tlb0_info) 97 #endif 98 #define pmap_md_tlb_asid_max() (PMAP_TLB_NUM_PIDS - 1) 99 #include <uvm/pmap/tlb.h> 100 #include <uvm/pmap/pmap_tlb.h> 101 102 /* 103 * If we have an EXTENDED MMU and the address space is split evenly between 104 * user and kernel, we can use the TTBR0/TTBR1 to have separate L1 tables for 105 * user and kernel address spaces. 106 */ 107 #if (KERNEL_BASE & 0x80000000) == 0 108 #error ARMv6 or later systems must have a KERNEL_BASE >= 0x80000000 109 #endif 110 #endif /* ARM_MMU_EXTENDED */ 111 112 /* 113 * a pmap describes a processes' 4GB virtual address space. this 114 * virtual address space can be broken up into 4096 1MB regions which 115 * are described by L1 PTEs in the L1 table. 116 * 117 * There is a line drawn at KERNEL_BASE. Everything below that line 118 * changes when the VM context is switched. Everything above that line 119 * is the same no matter which VM context is running. This is achieved 120 * by making the L1 PTEs for those slots above KERNEL_BASE reference 121 * kernel L2 tables. 122 * 123 * The basic layout of the virtual address space thus looks like this: 124 * 125 * 0xffffffff 126 * . 127 * . 128 * . 129 * KERNEL_BASE 130 * -------------------- 131 * . 132 * . 133 * . 134 * 0x00000000 135 */ 136 137 /* 138 * The number of L2 descriptor tables which can be tracked by an l2_dtable. 139 * A bucket size of 16 provides for 16MB of contiguous virtual address 140 * space per l2_dtable. Most processes will, therefore, require only two or 141 * three of these to map their whole working set. 142 */ 143 #define L2_BUCKET_XLOG2 (L1_S_SHIFT) 144 #define L2_BUCKET_XSIZE (1 << L2_BUCKET_XLOG2) 145 #define L2_BUCKET_LOG2 4 146 #define L2_BUCKET_SIZE (1 << L2_BUCKET_LOG2) 147 148 /* 149 * Given the above "L2-descriptors-per-l2_dtable" constant, the number 150 * of l2_dtable structures required to track all possible page descriptors 151 * mappable by an L1 translation table is given by the following constants: 152 */ 153 #define L2_LOG2 (32 - (L2_BUCKET_XLOG2 + L2_BUCKET_LOG2)) 154 #define L2_SIZE (1 << L2_LOG2) 155 156 /* 157 * tell MI code that the cache is virtually-indexed. 158 * ARMv6 is physically-tagged but all others are virtually-tagged. 159 */ 160 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 161 #define PMAP_CACHE_VIPT 162 #else 163 #define PMAP_CACHE_VIVT 164 #endif 165 166 #ifndef _LOCORE 167 168 #ifndef PMAP_MMU_EXTENDED 169 struct l1_ttable; 170 struct l2_dtable; 171 172 /* 173 * Track cache/tlb occupancy using the following structure 174 */ 175 union pmap_cache_state { 176 struct { 177 union { 178 uint8_t csu_cache_b[2]; 179 uint16_t csu_cache; 180 } cs_cache_u; 181 182 union { 183 uint8_t csu_tlb_b[2]; 184 uint16_t csu_tlb; 185 } cs_tlb_u; 186 } cs_s; 187 uint32_t cs_all; 188 }; 189 #define cs_cache_id cs_s.cs_cache_u.csu_cache_b[0] 190 #define cs_cache_d cs_s.cs_cache_u.csu_cache_b[1] 191 #define cs_cache cs_s.cs_cache_u.csu_cache 192 #define cs_tlb_id cs_s.cs_tlb_u.csu_tlb_b[0] 193 #define cs_tlb_d cs_s.cs_tlb_u.csu_tlb_b[1] 194 #define cs_tlb cs_s.cs_tlb_u.csu_tlb 195 196 /* 197 * Assigned to cs_all to force cacheops to work for a particular pmap 198 */ 199 #define PMAP_CACHE_STATE_ALL 0xffffffffu 200 #endif /* !ARM_MMU_EXTENDED */ 201 202 /* 203 * This structure is used by machine-dependent code to describe 204 * static mappings of devices, created at bootstrap time. 205 */ 206 struct pmap_devmap { 207 vaddr_t pd_va; /* virtual address */ 208 paddr_t pd_pa; /* physical address */ 209 psize_t pd_size; /* size of region */ 210 vm_prot_t pd_prot; /* protection code */ 211 int pd_cache; /* cache attributes */ 212 }; 213 214 /* 215 * The pmap structure itself 216 */ 217 struct pmap { 218 struct uvm_object pm_obj; 219 kmutex_t pm_obj_lock; 220 #define pm_lock pm_obj.vmobjlock 221 #ifndef ARM_HAS_VBAR 222 pd_entry_t *pm_pl1vec; 223 pd_entry_t pm_l1vec; 224 #endif 225 struct l2_dtable *pm_l2[L2_SIZE]; 226 struct pmap_statistics pm_stats; 227 LIST_ENTRY(pmap) pm_list; 228 #ifdef ARM_MMU_EXTENDED 229 pd_entry_t *pm_l1; 230 paddr_t pm_l1_pa; 231 bool pm_remove_all; 232 #ifdef MULTIPROCESSOR 233 kcpuset_t *pm_onproc; 234 kcpuset_t *pm_active; 235 #if PMAP_TLB_MAX > 1 236 u_int pm_shootdown_pending; 237 #endif 238 #endif 239 struct pmap_asid_info pm_pai[PMAP_TLB_MAX]; 240 #else 241 struct l1_ttable *pm_l1; 242 union pmap_cache_state pm_cstate; 243 uint8_t pm_domain; 244 bool pm_activated; 245 bool pm_remove_all; 246 #endif 247 }; 248 249 struct pmap_kernel { 250 struct pmap kernel_pmap; 251 }; 252 253 /* 254 * Physical / virtual address structure. In a number of places (particularly 255 * during bootstrapping) we need to keep track of the physical and virtual 256 * addresses of various pages 257 */ 258 typedef struct pv_addr { 259 SLIST_ENTRY(pv_addr) pv_list; 260 paddr_t pv_pa; 261 vaddr_t pv_va; 262 vsize_t pv_size; 263 uint8_t pv_cache; 264 uint8_t pv_prot; 265 } pv_addr_t; 266 typedef SLIST_HEAD(, pv_addr) pv_addrqh_t; 267 268 extern pv_addrqh_t pmap_freeq; 269 extern pv_addr_t kernelstack; 270 extern pv_addr_t abtstack; 271 extern pv_addr_t fiqstack; 272 extern pv_addr_t irqstack; 273 extern pv_addr_t undstack; 274 extern pv_addr_t idlestack; 275 extern pv_addr_t systempage; 276 extern pv_addr_t kernel_l1pt; 277 278 #ifdef ARM_MMU_EXTENDED 279 extern bool arm_has_tlbiasid_p; /* also in <arm/locore.h> */ 280 #endif 281 282 /* 283 * Determine various modes for PTEs (user vs. kernel, cacheable 284 * vs. non-cacheable). 285 */ 286 #define PTE_KERNEL 0 287 #define PTE_USER 1 288 #define PTE_NOCACHE 0 289 #define PTE_CACHE 1 290 #define PTE_PAGETABLE 2 291 292 /* 293 * Flags that indicate attributes of pages or mappings of pages. 294 * 295 * The PVF_MOD and PVF_REF flags are stored in the mdpage for each 296 * page. PVF_WIRED, PVF_WRITE, and PVF_NC are kept in individual 297 * pv_entry's for each page. They live in the same "namespace" so 298 * that we can clear multiple attributes at a time. 299 * 300 * Note the "non-cacheable" flag generally means the page has 301 * multiple mappings in a given address space. 302 */ 303 #define PVF_MOD 0x01 /* page is modified */ 304 #define PVF_REF 0x02 /* page is referenced */ 305 #define PVF_WIRED 0x04 /* mapping is wired */ 306 #define PVF_WRITE 0x08 /* mapping is writable */ 307 #define PVF_EXEC 0x10 /* mapping is executable */ 308 #ifdef PMAP_CACHE_VIVT 309 #define PVF_UNC 0x20 /* mapping is 'user' non-cacheable */ 310 #define PVF_KNC 0x40 /* mapping is 'kernel' non-cacheable */ 311 #define PVF_NC (PVF_UNC|PVF_KNC) 312 #endif 313 #ifdef PMAP_CACHE_VIPT 314 #define PVF_NC 0x20 /* mapping is 'kernel' non-cacheable */ 315 #define PVF_MULTCLR 0x40 /* mapping is multi-colored */ 316 #endif 317 #define PVF_COLORED 0x80 /* page has or had a color */ 318 #define PVF_KENTRY 0x0100 /* page entered via pmap_kenter_pa */ 319 #define PVF_KMPAGE 0x0200 /* page is used for kmem */ 320 #define PVF_DIRTY 0x0400 /* page may have dirty cache lines */ 321 #define PVF_KMOD 0x0800 /* unmanaged page is modified */ 322 #define PVF_KWRITE (PVF_KENTRY|PVF_WRITE) 323 #define PVF_DMOD (PVF_MOD|PVF_KMOD|PVF_KMPAGE) 324 325 /* 326 * Commonly referenced structures 327 */ 328 extern int pmap_debug_level; /* Only exists if PMAP_DEBUG */ 329 extern int arm_poolpage_vmfreelist; 330 331 /* 332 * Macros that we need to export 333 */ 334 #define pmap_resident_count(pmap) ((pmap)->pm_stats.resident_count) 335 #define pmap_wired_count(pmap) ((pmap)->pm_stats.wired_count) 336 337 #define pmap_is_modified(pg) \ 338 (((pg)->mdpage.pvh_attrs & PVF_MOD) != 0) 339 #define pmap_is_referenced(pg) \ 340 (((pg)->mdpage.pvh_attrs & PVF_REF) != 0) 341 #define pmap_is_page_colored_p(md) \ 342 (((md)->pvh_attrs & PVF_COLORED) != 0) 343 344 #define pmap_copy(dp, sp, da, l, sa) /* nothing */ 345 346 #define pmap_phys_address(ppn) (arm_ptob((ppn))) 347 u_int arm32_mmap_flags(paddr_t); 348 #define ARM32_MMAP_WRITECOMBINE 0x40000000 349 #define ARM32_MMAP_CACHEABLE 0x20000000 350 #define pmap_mmap_flags(ppn) arm32_mmap_flags(ppn) 351 352 #define PMAP_PTE 0x10000000 /* kenter_pa */ 353 354 /* 355 * Functions that we need to export 356 */ 357 void pmap_procwr(struct proc *, vaddr_t, int); 358 void pmap_remove_all(pmap_t); 359 bool pmap_extract(pmap_t, vaddr_t, paddr_t *); 360 361 #define PMAP_NEED_PROCWR 362 #define PMAP_GROWKERNEL /* turn on pmap_growkernel interface */ 363 #define PMAP_ENABLE_PMAP_KMPAGE /* enable the PMAP_KMPAGE flag */ 364 365 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 366 #define PMAP_PREFER(hint, vap, sz, td) pmap_prefer((hint), (vap), (td)) 367 void pmap_prefer(vaddr_t, vaddr_t *, int); 368 #endif 369 370 void pmap_icache_sync_range(pmap_t, vaddr_t, vaddr_t); 371 372 /* Functions we use internally. */ 373 #ifdef PMAP_STEAL_MEMORY 374 void pmap_boot_pagealloc(psize_t, psize_t, psize_t, pv_addr_t *); 375 void pmap_boot_pageadd(pv_addr_t *); 376 vaddr_t pmap_steal_memory(vsize_t, vaddr_t *, vaddr_t *); 377 #endif 378 void pmap_bootstrap(vaddr_t, vaddr_t); 379 380 void pmap_do_remove(pmap_t, vaddr_t, vaddr_t, int); 381 int pmap_fault_fixup(pmap_t, vaddr_t, vm_prot_t, int); 382 int pmap_prefetchabt_fixup(void *); 383 bool pmap_get_pde_pte(pmap_t, vaddr_t, pd_entry_t **, pt_entry_t **); 384 bool pmap_get_pde(pmap_t, vaddr_t, pd_entry_t **); 385 struct pcb; 386 void pmap_set_pcb_pagedir(pmap_t, struct pcb *); 387 388 void pmap_debug(int); 389 void pmap_postinit(void); 390 391 void vector_page_setprot(int); 392 393 const struct pmap_devmap *pmap_devmap_find_pa(paddr_t, psize_t); 394 const struct pmap_devmap *pmap_devmap_find_va(vaddr_t, vsize_t); 395 396 /* Bootstrapping routines. */ 397 void pmap_map_section(vaddr_t, vaddr_t, paddr_t, int, int); 398 void pmap_map_entry(vaddr_t, vaddr_t, paddr_t, int, int); 399 vsize_t pmap_map_chunk(vaddr_t, vaddr_t, paddr_t, vsize_t, int, int); 400 void pmap_link_l2pt(vaddr_t, vaddr_t, pv_addr_t *); 401 void pmap_devmap_bootstrap(vaddr_t, const struct pmap_devmap *); 402 void pmap_devmap_register(const struct pmap_devmap *); 403 404 /* 405 * Special page zero routine for use by the idle loop (no cache cleans). 406 */ 407 bool pmap_pageidlezero(paddr_t); 408 #define PMAP_PAGEIDLEZERO(pa) pmap_pageidlezero((pa)) 409 410 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 411 /* 412 * For the pmap, this is a more useful way to map a direct mapped page. 413 * It returns either the direct-mapped VA or the VA supplied if it can't 414 * be direct mapped. 415 */ 416 vaddr_t pmap_direct_mapped_phys(paddr_t, bool *, vaddr_t); 417 #endif 418 419 /* 420 * used by dumpsys to record the PA of the L1 table 421 */ 422 uint32_t pmap_kernel_L1_addr(void); 423 /* 424 * The current top of kernel VM 425 */ 426 extern vaddr_t pmap_curmaxkvaddr; 427 428 #if defined(ARM_MMU_EXTENDED) && defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) 429 /* 430 * Starting VA of direct mapped memory (usually KERNEL_BASE). 431 */ 432 extern vaddr_t pmap_directbase; 433 #endif 434 435 /* 436 * Useful macros and constants 437 */ 438 439 /* Virtual address to page table entry */ 440 static inline pt_entry_t * 441 vtopte(vaddr_t va) 442 { 443 pd_entry_t *pdep; 444 pt_entry_t *ptep; 445 446 KASSERT(trunc_page(va) == va); 447 448 if (pmap_get_pde_pte(pmap_kernel(), va, &pdep, &ptep) == false) 449 return (NULL); 450 return (ptep); 451 } 452 453 /* 454 * Virtual address to physical address 455 */ 456 static inline paddr_t 457 vtophys(vaddr_t va) 458 { 459 paddr_t pa; 460 461 if (pmap_extract(pmap_kernel(), va, &pa) == false) 462 return (0); /* XXXSCW: Panic? */ 463 464 return (pa); 465 } 466 467 /* 468 * The new pmap ensures that page-tables are always mapping Write-Thru. 469 * Thus, on some platforms we can run fast and loose and avoid syncing PTEs 470 * on every change. 471 * 472 * Unfortunately, not all CPUs have a write-through cache mode. So we 473 * define PMAP_NEEDS_PTE_SYNC for C code to conditionally do PTE syncs, 474 * and if there is the chance for PTE syncs to be needed, we define 475 * PMAP_INCLUDE_PTE_SYNC so e.g. assembly code can include (and run) 476 * the code. 477 */ 478 extern int pmap_needs_pte_sync; 479 #if defined(_KERNEL_OPT) 480 /* 481 * StrongARM SA-1 caches do not have a write-through mode. So, on these, 482 * we need to do PTE syncs. If only SA-1 is configured, then evaluate 483 * this at compile time. 484 */ 485 #if (ARM_MMU_SA1 + ARM_MMU_V6 != 0) && (ARM_NMMUS == 1) 486 #define PMAP_INCLUDE_PTE_SYNC 487 #if (ARM_MMU_V6 > 0) 488 #define PMAP_NEEDS_PTE_SYNC 1 489 #elif (ARM_MMU_SA1 == 0) 490 #define PMAP_NEEDS_PTE_SYNC 0 491 #endif 492 #endif 493 #endif /* _KERNEL_OPT */ 494 495 /* 496 * Provide a fallback in case we were not able to determine it at 497 * compile-time. 498 */ 499 #ifndef PMAP_NEEDS_PTE_SYNC 500 #define PMAP_NEEDS_PTE_SYNC pmap_needs_pte_sync 501 #define PMAP_INCLUDE_PTE_SYNC 502 #endif 503 504 static inline void 505 pmap_ptesync(pt_entry_t *ptep, size_t cnt) 506 { 507 if (PMAP_NEEDS_PTE_SYNC) { 508 cpu_dcache_wb_range((vaddr_t)ptep, cnt * sizeof(pt_entry_t)); 509 #ifdef SHEEVA_L2_CACHE 510 cpu_sdcache_wb_range((vaddr_t)ptep, -1, 511 cnt * sizeof(pt_entry_t)); 512 #endif 513 } 514 #if ARM_MMU_V7 > 0 515 __asm("dsb"); 516 #endif 517 } 518 519 #define PDE_SYNC(pdep) pmap_ptesync((pdep), 1) 520 #define PDE_SYNC_RANGE(pdep, cnt) pmap_ptesync((pdep), (cnt)) 521 #define PTE_SYNC(ptep) pmap_ptesync((ptep), PAGE_SIZE / L2_S_SIZE) 522 #define PTE_SYNC_RANGE(ptep, cnt) pmap_ptesync((ptep), (cnt)) 523 524 #define l1pte_valid_p(pde) ((pde) != 0) 525 #define l1pte_section_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_S) 526 #define l1pte_supersection_p(pde) (l1pte_section_p(pde) \ 527 && ((pde) & L1_S_V6_SUPER) != 0) 528 #define l1pte_page_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_C) 529 #define l1pte_fpage_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_F) 530 #define l1pte_pa(pde) ((pde) & L1_C_ADDR_MASK) 531 #define l1pte_index(v) ((vaddr_t)(v) >> L1_S_SHIFT) 532 #define l1pte_pgindex(v) l1pte_index((v) & L1_ADDR_BITS \ 533 & ~(PAGE_SIZE * PAGE_SIZE / sizeof(pt_entry_t) - 1)) 534 535 static inline void 536 l1pte_setone(pt_entry_t *pdep, pt_entry_t pde) 537 { 538 *pdep = pde; 539 } 540 541 static inline void 542 l1pte_set(pt_entry_t *pdep, pt_entry_t pde) 543 { 544 *pdep = pde; 545 if (l1pte_page_p(pde)) { 546 KASSERTMSG((((uintptr_t)pdep / sizeof(pde)) & (PAGE_SIZE / L2_T_SIZE - 1)) == 0, "%p", pdep); 547 for (size_t k = 1; k < PAGE_SIZE / L2_T_SIZE; k++) { 548 pde += L2_T_SIZE; 549 pdep[k] = pde; 550 } 551 } else if (l1pte_supersection_p(pde)) { 552 KASSERTMSG((((uintptr_t)pdep / sizeof(pde)) & (L1_SS_SIZE / L1_S_SIZE - 1)) == 0, "%p", pdep); 553 for (size_t k = 1; k < L1_SS_SIZE / L1_S_SIZE; k++) { 554 pdep[k] = pde; 555 } 556 } 557 } 558 559 #define l2pte_index(v) ((((v) & L2_ADDR_BITS) >> PGSHIFT) << (PGSHIFT-L2_S_SHIFT)) 560 #define l2pte_valid_p(pte) (((pte) & L2_TYPE_MASK) != L2_TYPE_INV) 561 #define l2pte_pa(pte) ((pte) & L2_S_FRAME) 562 #define l1pte_lpage_p(pte) (((pte) & L2_TYPE_MASK) == L2_TYPE_L) 563 #define l2pte_minidata_p(pte) (((pte) & \ 564 (L2_B | L2_C | L2_XS_T_TEX(TEX_XSCALE_X)))\ 565 == (L2_C | L2_XS_T_TEX(TEX_XSCALE_X))) 566 567 static inline void 568 l2pte_set(pt_entry_t *ptep, pt_entry_t pte, pt_entry_t opte) 569 { 570 if (l1pte_lpage_p(pte)) { 571 for (size_t k = 0; k < L2_L_SIZE / L2_S_SIZE; k++) { 572 *ptep++ = pte; 573 } 574 } else { 575 for (size_t k = 0; k < PAGE_SIZE / L2_S_SIZE; k++) { 576 KASSERTMSG(*ptep == opte, "%#x [*%p] != %#x", *ptep, ptep, opte); 577 *ptep++ = pte; 578 pte += L2_S_SIZE; 579 if (opte) 580 opte += L2_S_SIZE; 581 } 582 } 583 } 584 585 static inline void 586 l2pte_reset(pt_entry_t *ptep) 587 { 588 *ptep = 0; 589 for (vsize_t k = 1; k < PAGE_SIZE / L2_S_SIZE; k++) { 590 ptep[k] = 0; 591 } 592 } 593 594 /* L1 and L2 page table macros */ 595 #define pmap_pde_v(pde) l1pte_valid(*(pde)) 596 #define pmap_pde_section(pde) l1pte_section_p(*(pde)) 597 #define pmap_pde_supersection(pde) l1pte_supersection_p(*(pde)) 598 #define pmap_pde_page(pde) l1pte_page_p(*(pde)) 599 #define pmap_pde_fpage(pde) l1pte_fpage_p(*(pde)) 600 601 #define pmap_pte_v(pte) l2pte_valid_p(*(pte)) 602 #define pmap_pte_pa(pte) l2pte_pa(*(pte)) 603 604 /* Size of the kernel part of the L1 page table */ 605 #define KERNEL_PD_SIZE \ 606 (L1_TABLE_SIZE - (KERNEL_BASE >> L1_S_SHIFT) * sizeof(pd_entry_t)) 607 608 void bzero_page(vaddr_t); 609 void bcopy_page(vaddr_t, vaddr_t); 610 611 #ifdef FPU_VFP 612 void bzero_page_vfp(vaddr_t); 613 void bcopy_page_vfp(vaddr_t, vaddr_t); 614 #endif 615 616 /************************* ARM MMU configuration *****************************/ 617 618 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 619 void pmap_copy_page_generic(paddr_t, paddr_t); 620 void pmap_zero_page_generic(paddr_t); 621 622 void pmap_pte_init_generic(void); 623 #if defined(CPU_ARM8) 624 void pmap_pte_init_arm8(void); 625 #endif 626 #if defined(CPU_ARM9) 627 void pmap_pte_init_arm9(void); 628 #endif /* CPU_ARM9 */ 629 #if defined(CPU_ARM10) 630 void pmap_pte_init_arm10(void); 631 #endif /* CPU_ARM10 */ 632 #if defined(CPU_ARM11) /* ARM_MMU_V6 */ 633 void pmap_pte_init_arm11(void); 634 #endif /* CPU_ARM11 */ 635 #if defined(CPU_ARM11MPCORE) /* ARM_MMU_V6 */ 636 void pmap_pte_init_arm11mpcore(void); 637 #endif 638 #if ARM_MMU_V7 == 1 639 void pmap_pte_init_armv7(void); 640 #endif /* ARM_MMU_V7 */ 641 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */ 642 643 #if ARM_MMU_SA1 == 1 644 void pmap_pte_init_sa1(void); 645 #endif /* ARM_MMU_SA1 == 1 */ 646 647 #if ARM_MMU_XSCALE == 1 648 void pmap_copy_page_xscale(paddr_t, paddr_t); 649 void pmap_zero_page_xscale(paddr_t); 650 651 void pmap_pte_init_xscale(void); 652 653 void xscale_setup_minidata(vaddr_t, vaddr_t, paddr_t); 654 655 #define PMAP_UAREA(va) pmap_uarea(va) 656 void pmap_uarea(vaddr_t); 657 #endif /* ARM_MMU_XSCALE == 1 */ 658 659 extern pt_entry_t pte_l1_s_cache_mode; 660 extern pt_entry_t pte_l1_s_cache_mask; 661 662 extern pt_entry_t pte_l2_l_cache_mode; 663 extern pt_entry_t pte_l2_l_cache_mask; 664 665 extern pt_entry_t pte_l2_s_cache_mode; 666 extern pt_entry_t pte_l2_s_cache_mask; 667 668 extern pt_entry_t pte_l1_s_cache_mode_pt; 669 extern pt_entry_t pte_l2_l_cache_mode_pt; 670 extern pt_entry_t pte_l2_s_cache_mode_pt; 671 672 extern pt_entry_t pte_l1_s_wc_mode; 673 extern pt_entry_t pte_l2_l_wc_mode; 674 extern pt_entry_t pte_l2_s_wc_mode; 675 676 extern pt_entry_t pte_l1_s_prot_u; 677 extern pt_entry_t pte_l1_s_prot_w; 678 extern pt_entry_t pte_l1_s_prot_ro; 679 extern pt_entry_t pte_l1_s_prot_mask; 680 681 extern pt_entry_t pte_l2_s_prot_u; 682 extern pt_entry_t pte_l2_s_prot_w; 683 extern pt_entry_t pte_l2_s_prot_ro; 684 extern pt_entry_t pte_l2_s_prot_mask; 685 686 extern pt_entry_t pte_l2_l_prot_u; 687 extern pt_entry_t pte_l2_l_prot_w; 688 extern pt_entry_t pte_l2_l_prot_ro; 689 extern pt_entry_t pte_l2_l_prot_mask; 690 691 extern pt_entry_t pte_l1_ss_proto; 692 extern pt_entry_t pte_l1_s_proto; 693 extern pt_entry_t pte_l1_c_proto; 694 extern pt_entry_t pte_l2_s_proto; 695 696 extern void (*pmap_copy_page_func)(paddr_t, paddr_t); 697 extern void (*pmap_zero_page_func)(paddr_t); 698 699 #endif /* !_LOCORE */ 700 701 /*****************************************************************************/ 702 703 #define KERNEL_PID 0 /* The kernel uses ASID 0 */ 704 705 /* 706 * Definitions for MMU domains 707 */ 708 #define PMAP_DOMAINS 15 /* 15 'user' domains (1-15) */ 709 #define PMAP_DOMAIN_KERNEL 0 /* The kernel pmap uses domain #0 */ 710 #ifdef ARM_MMU_EXTENDED 711 #define PMAP_DOMAIN_USER 1 /* User pmaps use domain #1 */ 712 #endif 713 714 /* 715 * These macros define the various bit masks in the PTE. 716 * 717 * We use these macros since we use different bits on different processor 718 * models. 719 */ 720 #define L1_S_PROT_U_generic (L1_S_AP(AP_U)) 721 #define L1_S_PROT_W_generic (L1_S_AP(AP_W)) 722 #define L1_S_PROT_RO_generic (0) 723 #define L1_S_PROT_MASK_generic (L1_S_PROT_U|L1_S_PROT_W|L1_S_PROT_RO) 724 725 #define L1_S_PROT_U_xscale (L1_S_AP(AP_U)) 726 #define L1_S_PROT_W_xscale (L1_S_AP(AP_W)) 727 #define L1_S_PROT_RO_xscale (0) 728 #define L1_S_PROT_MASK_xscale (L1_S_PROT_U|L1_S_PROT_W|L1_S_PROT_RO) 729 730 #define L1_S_PROT_U_armv6 (L1_S_AP(AP_R) | L1_S_AP(AP_U)) 731 #define L1_S_PROT_W_armv6 (L1_S_AP(AP_W)) 732 #define L1_S_PROT_RO_armv6 (L1_S_AP(AP_R) | L1_S_AP(AP_RO)) 733 #define L1_S_PROT_MASK_armv6 (L1_S_PROT_U|L1_S_PROT_W|L1_S_PROT_RO) 734 735 #define L1_S_PROT_U_armv7 (L1_S_AP(AP_R) | L1_S_AP(AP_U)) 736 #define L1_S_PROT_W_armv7 (L1_S_AP(AP_W)) 737 #define L1_S_PROT_RO_armv7 (L1_S_AP(AP_R) | L1_S_AP(AP_RO)) 738 #define L1_S_PROT_MASK_armv7 (L1_S_PROT_U|L1_S_PROT_W|L1_S_PROT_RO) 739 740 #define L1_S_CACHE_MASK_generic (L1_S_B|L1_S_C) 741 #define L1_S_CACHE_MASK_xscale (L1_S_B|L1_S_C|L1_S_XS_TEX(TEX_XSCALE_X)) 742 #define L1_S_CACHE_MASK_armv6 (L1_S_B|L1_S_C|L1_S_XS_TEX(TEX_ARMV6_TEX)) 743 #define L1_S_CACHE_MASK_armv6n (L1_S_B|L1_S_C|L1_S_XS_TEX(TEX_ARMV6_TEX)|L1_S_V6_S) 744 #define L1_S_CACHE_MASK_armv7 (L1_S_B|L1_S_C|L1_S_XS_TEX(TEX_ARMV6_TEX)|L1_S_V6_S) 745 746 #define L2_L_PROT_U_generic (L2_AP(AP_U)) 747 #define L2_L_PROT_W_generic (L2_AP(AP_W)) 748 #define L2_L_PROT_RO_generic (0) 749 #define L2_L_PROT_MASK_generic (L2_L_PROT_U|L2_L_PROT_W|L2_L_PROT_RO) 750 751 #define L2_L_PROT_U_xscale (L2_AP(AP_U)) 752 #define L2_L_PROT_W_xscale (L2_AP(AP_W)) 753 #define L2_L_PROT_RO_xscale (0) 754 #define L2_L_PROT_MASK_xscale (L2_L_PROT_U|L2_L_PROT_W|L2_L_PROT_RO) 755 756 #define L2_L_PROT_U_armv6n (L2_AP0(AP_R) | L2_AP0(AP_U)) 757 #define L2_L_PROT_W_armv6n (L2_AP0(AP_W)) 758 #define L2_L_PROT_RO_armv6n (L2_AP0(AP_R) | L2_AP0(AP_RO)) 759 #define L2_L_PROT_MASK_armv6n (L2_L_PROT_U|L2_L_PROT_W|L2_L_PROT_RO) 760 761 #define L2_L_PROT_U_armv7 (L2_AP0(AP_R) | L2_AP0(AP_U)) 762 #define L2_L_PROT_W_armv7 (L2_AP0(AP_W)) 763 #define L2_L_PROT_RO_armv7 (L2_AP0(AP_R) | L2_AP0(AP_RO)) 764 #define L2_L_PROT_MASK_armv7 (L2_L_PROT_U|L2_L_PROT_W|L2_L_PROT_RO) 765 766 #define L2_L_CACHE_MASK_generic (L2_B|L2_C) 767 #define L2_L_CACHE_MASK_xscale (L2_B|L2_C|L2_XS_L_TEX(TEX_XSCALE_X)) 768 #define L2_L_CACHE_MASK_armv6 (L2_B|L2_C|L2_V6_L_TEX(TEX_ARMV6_TEX)) 769 #define L2_L_CACHE_MASK_armv6n (L2_B|L2_C|L2_V6_L_TEX(TEX_ARMV6_TEX)|L2_XS_S) 770 #define L2_L_CACHE_MASK_armv7 (L2_B|L2_C|L2_V6_L_TEX(TEX_ARMV6_TEX)|L2_XS_S) 771 772 #define L2_S_PROT_U_generic (L2_AP(AP_U)) 773 #define L2_S_PROT_W_generic (L2_AP(AP_W)) 774 #define L2_S_PROT_RO_generic (0) 775 #define L2_S_PROT_MASK_generic (L2_S_PROT_U|L2_S_PROT_W|L2_S_PROT_RO) 776 777 #define L2_S_PROT_U_xscale (L2_AP0(AP_U)) 778 #define L2_S_PROT_W_xscale (L2_AP0(AP_W)) 779 #define L2_S_PROT_RO_xscale (0) 780 #define L2_S_PROT_MASK_xscale (L2_S_PROT_U|L2_S_PROT_W|L2_S_PROT_RO) 781 782 #define L2_S_PROT_U_armv6n (L2_AP0(AP_R) | L2_AP0(AP_U)) 783 #define L2_S_PROT_W_armv6n (L2_AP0(AP_W)) 784 #define L2_S_PROT_RO_armv6n (L2_AP0(AP_R) | L2_AP0(AP_RO)) 785 #define L2_S_PROT_MASK_armv6n (L2_S_PROT_U|L2_S_PROT_W|L2_S_PROT_RO) 786 787 #define L2_S_PROT_U_armv7 (L2_AP0(AP_R) | L2_AP0(AP_U)) 788 #define L2_S_PROT_W_armv7 (L2_AP0(AP_W)) 789 #define L2_S_PROT_RO_armv7 (L2_AP0(AP_R) | L2_AP0(AP_RO)) 790 #define L2_S_PROT_MASK_armv7 (L2_S_PROT_U|L2_S_PROT_W|L2_S_PROT_RO) 791 792 #define L2_S_CACHE_MASK_generic (L2_B|L2_C) 793 #define L2_S_CACHE_MASK_xscale (L2_B|L2_C|L2_XS_T_TEX(TEX_XSCALE_X)) 794 #define L2_XS_CACHE_MASK_armv6 (L2_B|L2_C|L2_V6_XS_TEX(TEX_ARMV6_TEX)) 795 #define L2_S_CACHE_MASK_armv6n L2_XS_CACHE_MASK_armv6 796 #ifdef ARMV6_EXTENDED_SMALL_PAGE 797 #define L2_S_CACHE_MASK_armv6c L2_XS_CACHE_MASK_armv6 798 #else 799 #define L2_S_CACHE_MASK_armv6c L2_S_CACHE_MASK_generic 800 #endif 801 #define L2_S_CACHE_MASK_armv7 (L2_B|L2_C|L2_V6_XS_TEX(TEX_ARMV6_TEX)|L2_XS_S) 802 803 804 #define L1_S_PROTO_generic (L1_TYPE_S | L1_S_IMP) 805 #define L1_S_PROTO_xscale (L1_TYPE_S) 806 #define L1_S_PROTO_armv6 (L1_TYPE_S) 807 #define L1_S_PROTO_armv7 (L1_TYPE_S) 808 809 #define L1_SS_PROTO_generic 0 810 #define L1_SS_PROTO_xscale 0 811 #define L1_SS_PROTO_armv6 (L1_TYPE_S | L1_S_V6_SS) 812 #define L1_SS_PROTO_armv7 (L1_TYPE_S | L1_S_V6_SS) 813 814 #define L1_C_PROTO_generic (L1_TYPE_C | L1_C_IMP2) 815 #define L1_C_PROTO_xscale (L1_TYPE_C) 816 #define L1_C_PROTO_armv6 (L1_TYPE_C) 817 #define L1_C_PROTO_armv7 (L1_TYPE_C) 818 819 #define L2_L_PROTO (L2_TYPE_L) 820 821 #define L2_S_PROTO_generic (L2_TYPE_S) 822 #define L2_S_PROTO_xscale (L2_TYPE_XS) 823 #ifdef ARMV6_EXTENDED_SMALL_PAGE 824 #define L2_S_PROTO_armv6c (L2_TYPE_XS) /* XP=0, extended small page */ 825 #else 826 #define L2_S_PROTO_armv6c (L2_TYPE_S) /* XP=0, subpage APs */ 827 #endif 828 #ifdef ARM_MMU_EXTENDED 829 #define L2_S_PROTO_armv6n (L2_TYPE_S|L2_XS_XN) 830 #else 831 #define L2_S_PROTO_armv6n (L2_TYPE_S) /* with XP=1 */ 832 #endif 833 #ifdef ARM_MMU_EXTENDED 834 #define L2_S_PROTO_armv7 (L2_TYPE_S|L2_XS_XN) 835 #else 836 #define L2_S_PROTO_armv7 (L2_TYPE_S) 837 #endif 838 839 /* 840 * User-visible names for the ones that vary with MMU class. 841 */ 842 843 #if ARM_NMMUS > 1 844 /* More than one MMU class configured; use variables. */ 845 #define L1_S_PROT_U pte_l1_s_prot_u 846 #define L1_S_PROT_W pte_l1_s_prot_w 847 #define L1_S_PROT_RO pte_l1_s_prot_ro 848 #define L1_S_PROT_MASK pte_l1_s_prot_mask 849 850 #define L2_S_PROT_U pte_l2_s_prot_u 851 #define L2_S_PROT_W pte_l2_s_prot_w 852 #define L2_S_PROT_RO pte_l2_s_prot_ro 853 #define L2_S_PROT_MASK pte_l2_s_prot_mask 854 855 #define L2_L_PROT_U pte_l2_l_prot_u 856 #define L2_L_PROT_W pte_l2_l_prot_w 857 #define L2_L_PROT_RO pte_l2_l_prot_ro 858 #define L2_L_PROT_MASK pte_l2_l_prot_mask 859 860 #define L1_S_CACHE_MASK pte_l1_s_cache_mask 861 #define L2_L_CACHE_MASK pte_l2_l_cache_mask 862 #define L2_S_CACHE_MASK pte_l2_s_cache_mask 863 864 #define L1_SS_PROTO pte_l1_ss_proto 865 #define L1_S_PROTO pte_l1_s_proto 866 #define L1_C_PROTO pte_l1_c_proto 867 #define L2_S_PROTO pte_l2_s_proto 868 869 #define pmap_copy_page(s, d) (*pmap_copy_page_func)((s), (d)) 870 #define pmap_zero_page(d) (*pmap_zero_page_func)((d)) 871 #elif (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 872 #define L1_S_PROT_U L1_S_PROT_U_generic 873 #define L1_S_PROT_W L1_S_PROT_W_generic 874 #define L1_S_PROT_RO L1_S_PROT_RO_generic 875 #define L1_S_PROT_MASK L1_S_PROT_MASK_generic 876 877 #define L2_S_PROT_U L2_S_PROT_U_generic 878 #define L2_S_PROT_W L2_S_PROT_W_generic 879 #define L2_S_PROT_RO L2_S_PROT_RO_generic 880 #define L2_S_PROT_MASK L2_S_PROT_MASK_generic 881 882 #define L2_L_PROT_U L2_L_PROT_U_generic 883 #define L2_L_PROT_W L2_L_PROT_W_generic 884 #define L2_L_PROT_RO L2_L_PROT_RO_generic 885 #define L2_L_PROT_MASK L2_L_PROT_MASK_generic 886 887 #define L1_S_CACHE_MASK L1_S_CACHE_MASK_generic 888 #define L2_L_CACHE_MASK L2_L_CACHE_MASK_generic 889 #define L2_S_CACHE_MASK L2_S_CACHE_MASK_generic 890 891 #define L1_SS_PROTO L1_SS_PROTO_generic 892 #define L1_S_PROTO L1_S_PROTO_generic 893 #define L1_C_PROTO L1_C_PROTO_generic 894 #define L2_S_PROTO L2_S_PROTO_generic 895 896 #define pmap_copy_page(s, d) pmap_copy_page_generic((s), (d)) 897 #define pmap_zero_page(d) pmap_zero_page_generic((d)) 898 #elif ARM_MMU_V6N != 0 899 #define L1_S_PROT_U L1_S_PROT_U_armv6 900 #define L1_S_PROT_W L1_S_PROT_W_armv6 901 #define L1_S_PROT_RO L1_S_PROT_RO_armv6 902 #define L1_S_PROT_MASK L1_S_PROT_MASK_armv6 903 904 #define L2_S_PROT_U L2_S_PROT_U_armv6n 905 #define L2_S_PROT_W L2_S_PROT_W_armv6n 906 #define L2_S_PROT_RO L2_S_PROT_RO_armv6n 907 #define L2_S_PROT_MASK L2_S_PROT_MASK_armv6n 908 909 #define L2_L_PROT_U L2_L_PROT_U_armv6n 910 #define L2_L_PROT_W L2_L_PROT_W_armv6n 911 #define L2_L_PROT_RO L2_L_PROT_RO_armv6n 912 #define L2_L_PROT_MASK L2_L_PROT_MASK_armv6n 913 914 #define L1_S_CACHE_MASK L1_S_CACHE_MASK_armv6n 915 #define L2_L_CACHE_MASK L2_L_CACHE_MASK_armv6n 916 #define L2_S_CACHE_MASK L2_S_CACHE_MASK_armv6n 917 918 /* These prototypes make writeable mappings, while the other MMU types 919 * make read-only mappings. */ 920 #define L1_SS_PROTO L1_SS_PROTO_armv6 921 #define L1_S_PROTO L1_S_PROTO_armv6 922 #define L1_C_PROTO L1_C_PROTO_armv6 923 #define L2_S_PROTO L2_S_PROTO_armv6n 924 925 #define pmap_copy_page(s, d) pmap_copy_page_generic((s), (d)) 926 #define pmap_zero_page(d) pmap_zero_page_generic((d)) 927 #elif ARM_MMU_V6C != 0 928 #define L1_S_PROT_U L1_S_PROT_U_generic 929 #define L1_S_PROT_W L1_S_PROT_W_generic 930 #define L1_S_PROT_RO L1_S_PROT_RO_generic 931 #define L1_S_PROT_MASK L1_S_PROT_MASK_generic 932 933 #define L2_S_PROT_U L2_S_PROT_U_generic 934 #define L2_S_PROT_W L2_S_PROT_W_generic 935 #define L2_S_PROT_RO L2_S_PROT_RO_generic 936 #define L2_S_PROT_MASK L2_S_PROT_MASK_generic 937 938 #define L2_L_PROT_U L2_L_PROT_U_generic 939 #define L2_L_PROT_W L2_L_PROT_W_generic 940 #define L2_L_PROT_RO L2_L_PROT_RO_generic 941 #define L2_L_PROT_MASK L2_L_PROT_MASK_generic 942 943 #define L1_S_CACHE_MASK L1_S_CACHE_MASK_generic 944 #define L2_L_CACHE_MASK L2_L_CACHE_MASK_generic 945 #define L2_S_CACHE_MASK L2_S_CACHE_MASK_generic 946 947 #define L1_SS_PROTO L1_SS_PROTO_armv6 948 #define L1_S_PROTO L1_S_PROTO_generic 949 #define L1_C_PROTO L1_C_PROTO_generic 950 #define L2_S_PROTO L2_S_PROTO_generic 951 952 #define pmap_copy_page(s, d) pmap_copy_page_generic((s), (d)) 953 #define pmap_zero_page(d) pmap_zero_page_generic((d)) 954 #elif ARM_MMU_XSCALE == 1 955 #define L1_S_PROT_U L1_S_PROT_U_generic 956 #define L1_S_PROT_W L1_S_PROT_W_generic 957 #define L1_S_PROT_RO L1_S_PROT_RO_generic 958 #define L1_S_PROT_MASK L1_S_PROT_MASK_generic 959 960 #define L2_S_PROT_U L2_S_PROT_U_xscale 961 #define L2_S_PROT_W L2_S_PROT_W_xscale 962 #define L2_S_PROT_RO L2_S_PROT_RO_xscale 963 #define L2_S_PROT_MASK L2_S_PROT_MASK_xscale 964 965 #define L2_L_PROT_U L2_L_PROT_U_generic 966 #define L2_L_PROT_W L2_L_PROT_W_generic 967 #define L2_L_PROT_RO L2_L_PROT_RO_generic 968 #define L2_L_PROT_MASK L2_L_PROT_MASK_generic 969 970 #define L1_S_CACHE_MASK L1_S_CACHE_MASK_xscale 971 #define L2_L_CACHE_MASK L2_L_CACHE_MASK_xscale 972 #define L2_S_CACHE_MASK L2_S_CACHE_MASK_xscale 973 974 #define L1_SS_PROTO L1_SS_PROTO_xscale 975 #define L1_S_PROTO L1_S_PROTO_xscale 976 #define L1_C_PROTO L1_C_PROTO_xscale 977 #define L2_S_PROTO L2_S_PROTO_xscale 978 979 #define pmap_copy_page(s, d) pmap_copy_page_xscale((s), (d)) 980 #define pmap_zero_page(d) pmap_zero_page_xscale((d)) 981 #elif ARM_MMU_V7 == 1 982 #define L1_S_PROT_U L1_S_PROT_U_armv7 983 #define L1_S_PROT_W L1_S_PROT_W_armv7 984 #define L1_S_PROT_RO L1_S_PROT_RO_armv7 985 #define L1_S_PROT_MASK L1_S_PROT_MASK_armv7 986 987 #define L2_S_PROT_U L2_S_PROT_U_armv7 988 #define L2_S_PROT_W L2_S_PROT_W_armv7 989 #define L2_S_PROT_RO L2_S_PROT_RO_armv7 990 #define L2_S_PROT_MASK L2_S_PROT_MASK_armv7 991 992 #define L2_L_PROT_U L2_L_PROT_U_armv7 993 #define L2_L_PROT_W L2_L_PROT_W_armv7 994 #define L2_L_PROT_RO L2_L_PROT_RO_armv7 995 #define L2_L_PROT_MASK L2_L_PROT_MASK_armv7 996 997 #define L1_S_CACHE_MASK L1_S_CACHE_MASK_armv7 998 #define L2_L_CACHE_MASK L2_L_CACHE_MASK_armv7 999 #define L2_S_CACHE_MASK L2_S_CACHE_MASK_armv7 1000 1001 /* These prototypes make writeable mappings, while the other MMU types 1002 * make read-only mappings. */ 1003 #define L1_SS_PROTO L1_SS_PROTO_armv7 1004 #define L1_S_PROTO L1_S_PROTO_armv7 1005 #define L1_C_PROTO L1_C_PROTO_armv7 1006 #define L2_S_PROTO L2_S_PROTO_armv7 1007 1008 #define pmap_copy_page(s, d) pmap_copy_page_generic((s), (d)) 1009 #define pmap_zero_page(d) pmap_zero_page_generic((d)) 1010 #endif /* ARM_NMMUS > 1 */ 1011 1012 /* 1013 * Macros to set and query the write permission on page descriptors. 1014 */ 1015 #define l1pte_set_writable(pte) (((pte) & ~L1_S_PROT_RO) | L1_S_PROT_W) 1016 #define l1pte_set_readonly(pte) (((pte) & ~L1_S_PROT_W) | L1_S_PROT_RO) 1017 #define l2pte_set_writable(pte) (((pte) & ~L2_S_PROT_RO) | L2_S_PROT_W) 1018 #define l2pte_set_readonly(pte) (((pte) & ~L2_S_PROT_W) | L2_S_PROT_RO) 1019 1020 #define l2pte_writable_p(pte) (((pte) & L2_S_PROT_W) == L2_S_PROT_W && \ 1021 (L2_S_PROT_RO == 0 || \ 1022 ((pte) & L2_S_PROT_RO) != L2_S_PROT_RO)) 1023 1024 /* 1025 * These macros return various bits based on kernel/user and protection. 1026 * Note that the compiler will usually fold these at compile time. 1027 */ 1028 #define L1_S_PROT(ku, pr) ((((ku) == PTE_USER) ? L1_S_PROT_U : 0) | \ 1029 (((pr) & VM_PROT_WRITE) ? L1_S_PROT_W : L1_S_PROT_RO)) 1030 1031 #define L2_L_PROT(ku, pr) ((((ku) == PTE_USER) ? L2_L_PROT_U : 0) | \ 1032 (((pr) & VM_PROT_WRITE) ? L2_L_PROT_W : L2_L_PROT_RO)) 1033 1034 #define L2_S_PROT(ku, pr) ((((ku) == PTE_USER) ? L2_S_PROT_U : 0) | \ 1035 (((pr) & VM_PROT_WRITE) ? L2_S_PROT_W : L2_S_PROT_RO)) 1036 1037 /* 1038 * Macros to test if a mapping is mappable with an L1 SuperSection, 1039 * L1 Section, or an L2 Large Page mapping. 1040 */ 1041 #define L1_SS_MAPPABLE_P(va, pa, size) \ 1042 ((((va) | (pa)) & L1_SS_OFFSET) == 0 && (size) >= L1_SS_SIZE) 1043 1044 #define L1_S_MAPPABLE_P(va, pa, size) \ 1045 ((((va) | (pa)) & L1_S_OFFSET) == 0 && (size) >= L1_S_SIZE) 1046 1047 #define L2_L_MAPPABLE_P(va, pa, size) \ 1048 ((((va) | (pa)) & L2_L_OFFSET) == 0 && (size) >= L2_L_SIZE) 1049 1050 #ifndef _LOCORE 1051 /* 1052 * Hooks for the pool allocator. 1053 */ 1054 #define POOL_VTOPHYS(va) vtophys((vaddr_t) (va)) 1055 extern paddr_t physical_start, physical_end; 1056 #ifdef PMAP_NEED_ALLOC_POOLPAGE 1057 struct vm_page *arm_pmap_alloc_poolpage(int); 1058 #define PMAP_ALLOC_POOLPAGE arm_pmap_alloc_poolpage 1059 #endif 1060 #if defined(PMAP_NEED_ALLOC_POOLPAGE) || defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) 1061 vaddr_t pmap_map_poolpage(paddr_t); 1062 paddr_t pmap_unmap_poolpage(vaddr_t); 1063 #define PMAP_MAP_POOLPAGE(pa) pmap_map_poolpage(pa) 1064 #define PMAP_UNMAP_POOLPAGE(va) pmap_unmap_poolpage(va) 1065 #endif 1066 1067 /* 1068 * pmap-specific data store in the vm_page structure. 1069 */ 1070 #define __HAVE_VM_PAGE_MD 1071 struct vm_page_md { 1072 SLIST_HEAD(,pv_entry) pvh_list; /* pv_entry list */ 1073 int pvh_attrs; /* page attributes */ 1074 u_int uro_mappings; 1075 u_int urw_mappings; 1076 union { 1077 u_short s_mappings[2]; /* Assume kernel count <= 65535 */ 1078 u_int i_mappings; 1079 } k_u; 1080 #define kro_mappings k_u.s_mappings[0] 1081 #define krw_mappings k_u.s_mappings[1] 1082 #define k_mappings k_u.i_mappings 1083 }; 1084 1085 /* 1086 * Set the default color of each page. 1087 */ 1088 #if ARM_MMU_V6 > 0 1089 #define VM_MDPAGE_PVH_ATTRS_INIT(pg) \ 1090 (pg)->mdpage.pvh_attrs = (pg)->phys_addr & arm_cache_prefer_mask 1091 #else 1092 #define VM_MDPAGE_PVH_ATTRS_INIT(pg) \ 1093 (pg)->mdpage.pvh_attrs = 0 1094 #endif 1095 1096 #define VM_MDPAGE_INIT(pg) \ 1097 do { \ 1098 SLIST_INIT(&(pg)->mdpage.pvh_list); \ 1099 VM_MDPAGE_PVH_ATTRS_INIT(pg); \ 1100 (pg)->mdpage.uro_mappings = 0; \ 1101 (pg)->mdpage.urw_mappings = 0; \ 1102 (pg)->mdpage.k_mappings = 0; \ 1103 } while (/*CONSTCOND*/0) 1104 1105 #endif /* !_LOCORE */ 1106 1107 #endif /* _KERNEL */ 1108 1109 #endif /* _ARM32_PMAP_H_ */ 1110
Indexes created Mon Sep 29 21:09:56 GMT 2025