pmap.h revision 1.165
1 /* $NetBSD: pmap.h,v 1.165 2020/03/29 09:01:32 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2002, 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe & Steve C. Woodford for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Copyright (c) 1994,1995 Mark Brinicombe. 40 * All rights reserved. 41 * 42 * Redistribution and use in source and binary forms, with or without 43 * modification, are permitted provided that the following conditions 44 * are met: 45 * 1. Redistributions of source code must retain the above copyright 46 * notice, this list of conditions and the following disclaimer. 47 * 2. Redistributions in binary form must reproduce the above copyright 48 * notice, this list of conditions and the following disclaimer in the 49 * documentation and/or other materials provided with the distribution. 50 * 3. All advertising materials mentioning features or use of this software 51 * must display the following acknowledgement: 52 * This product includes software developed by Mark Brinicombe 53 * 4. The name of the author may not be used to endorse or promote products 54 * derived from this software without specific prior written permission. 55 * 56 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 57 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 58 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 59 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 60 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 61 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 62 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 63 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 64 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 65 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 #ifndef _ARM32_PMAP_H_ 69 #define _ARM32_PMAP_H_ 70 71 #ifdef _KERNEL 72 73 #include <arm/cpuconf.h> 74 #include <arm/arm32/pte.h> 75 #ifndef _LOCORE 76 #if defined(_KERNEL_OPT) 77 #include "opt_arm32_pmap.h" 78 #include "opt_multiprocessor.h" 79 #endif 80 #include <arm/cpufunc.h> 81 #include <arm/locore.h> 82 #include <uvm/uvm_object.h> 83 #include <uvm/pmap/pmap_pvt.h> 84 #endif 85 86 #ifdef ARM_MMU_EXTENDED 87 #define PMAP_HWPAGEWALKER 1 88 #define PMAP_TLB_MAX 1 89 #if PMAP_TLB_MAX > 1 90 #define PMAP_TLB_NEED_SHOOTDOWN 1 91 #endif 92 #define PMAP_TLB_FLUSH_ASID_ON_RESET (arm_has_tlbiasid_p) 93 #define PMAP_TLB_NUM_PIDS 256 94 #define cpu_set_tlb_info(ci, ti) ((void)((ci)->ci_tlb_info = (ti))) 95 #if PMAP_TLB_MAX > 1 96 #define cpu_tlb_info(ci) ((ci)->ci_tlb_info) 97 #else 98 #define cpu_tlb_info(ci) (&pmap_tlb0_info) 99 #endif 100 #define pmap_md_tlb_asid_max() (PMAP_TLB_NUM_PIDS - 1) 101 #include <uvm/pmap/tlb.h> 102 #include <uvm/pmap/pmap_tlb.h> 103 104 /* 105 * If we have an EXTENDED MMU and the address space is split evenly between 106 * user and kernel, we can use the TTBR0/TTBR1 to have separate L1 tables for 107 * user and kernel address spaces. 108 */ 109 #if (KERNEL_BASE & 0x80000000) == 0 110 #error ARMv6 or later systems must have a KERNEL_BASE >= 0x80000000 111 #endif 112 #endif /* ARM_MMU_EXTENDED */ 113 114 /* 115 * a pmap describes a processes' 4GB virtual address space. this 116 * virtual address space can be broken up into 4096 1MB regions which 117 * are described by L1 PTEs in the L1 table. 118 * 119 * There is a line drawn at KERNEL_BASE. Everything below that line 120 * changes when the VM context is switched. Everything above that line 121 * is the same no matter which VM context is running. This is achieved 122 * by making the L1 PTEs for those slots above KERNEL_BASE reference 123 * kernel L2 tables. 124 * 125 * The basic layout of the virtual address space thus looks like this: 126 * 127 * 0xffffffff 128 * . 129 * . 130 * . 131 * KERNEL_BASE 132 * -------------------- 133 * . 134 * . 135 * . 136 * 0x00000000 137 */ 138 139 /* 140 * The number of L2 descriptor tables which can be tracked by an l2_dtable. 141 * A bucket size of 16 provides for 16MB of contiguous virtual address 142 * space per l2_dtable. Most processes will, therefore, require only two or 143 * three of these to map their whole working set. 144 */ 145 #define L2_BUCKET_XLOG2 (L1_S_SHIFT) 146 #define L2_BUCKET_XSIZE (1 << L2_BUCKET_XLOG2) 147 #define L2_BUCKET_LOG2 4 148 #define L2_BUCKET_SIZE (1 << L2_BUCKET_LOG2) 149 150 /* 151 * Given the above "L2-descriptors-per-l2_dtable" constant, the number 152 * of l2_dtable structures required to track all possible page descriptors 153 * mappable by an L1 translation table is given by the following constants: 154 */ 155 #define L2_LOG2 (32 - (L2_BUCKET_XLOG2 + L2_BUCKET_LOG2)) 156 #define L2_SIZE (1 << L2_LOG2) 157 158 /* 159 * tell MI code that the cache is virtually-indexed. 160 * ARMv6 is physically-tagged but all others are virtually-tagged. 161 */ 162 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 163 #define PMAP_CACHE_VIPT 164 #else 165 #define PMAP_CACHE_VIVT 166 #endif 167 168 #ifndef _LOCORE 169 170 #ifndef ARM_MMU_EXTENDED 171 struct l1_ttable; 172 struct l2_dtable; 173 174 /* 175 * Track cache/tlb occupancy using the following structure 176 */ 177 union pmap_cache_state { 178 struct { 179 union { 180 uint8_t csu_cache_b[2]; 181 uint16_t csu_cache; 182 } cs_cache_u; 183 184 union { 185 uint8_t csu_tlb_b[2]; 186 uint16_t csu_tlb; 187 } cs_tlb_u; 188 } cs_s; 189 uint32_t cs_all; 190 }; 191 #define cs_cache_id cs_s.cs_cache_u.csu_cache_b[0] 192 #define cs_cache_d cs_s.cs_cache_u.csu_cache_b[1] 193 #define cs_cache cs_s.cs_cache_u.csu_cache 194 #define cs_tlb_id cs_s.cs_tlb_u.csu_tlb_b[0] 195 #define cs_tlb_d cs_s.cs_tlb_u.csu_tlb_b[1] 196 #define cs_tlb cs_s.cs_tlb_u.csu_tlb 197 198 /* 199 * Assigned to cs_all to force cacheops to work for a particular pmap 200 */ 201 #define PMAP_CACHE_STATE_ALL 0xffffffffu 202 #endif /* !ARM_MMU_EXTENDED */ 203 204 /* 205 * This structure is used by machine-dependent code to describe 206 * static mappings of devices, created at bootstrap time. 207 */ 208 struct pmap_devmap { 209 vaddr_t pd_va; /* virtual address */ 210 paddr_t pd_pa; /* physical address */ 211 psize_t pd_size; /* size of region */ 212 vm_prot_t pd_prot; /* protection code */ 213 int pd_cache; /* cache attributes */ 214 }; 215 216 #define DEVMAP_ALIGN(a) ((a) & ~L1_S_OFFSET) 217 #define DEVMAP_SIZE(s) roundup2((s), L1_S_SIZE) 218 #define DEVMAP_ENTRY(va, pa, sz) \ 219 { \ 220 .pd_va = DEVMAP_ALIGN(va), \ 221 .pd_pa = DEVMAP_ALIGN(pa), \ 222 .pd_size = DEVMAP_SIZE(sz), \ 223 .pd_prot = VM_PROT_READ|VM_PROT_WRITE, \ 224 .pd_cache = PTE_DEV \ 225 } 226 #define DEVMAP_ENTRY_END { 0 } 227 228 /* 229 * The pmap structure itself 230 */ 231 struct pmap { 232 kmutex_t pm_lock; 233 u_int pm_refs; 234 #ifndef ARM_HAS_VBAR 235 pd_entry_t *pm_pl1vec; 236 pd_entry_t pm_l1vec; 237 #endif 238 struct l2_dtable *pm_l2[L2_SIZE]; 239 struct pmap_statistics pm_stats; 240 LIST_ENTRY(pmap) pm_list; 241 #ifdef ARM_MMU_EXTENDED 242 pd_entry_t *pm_l1; 243 paddr_t pm_l1_pa; 244 bool pm_remove_all; 245 #ifdef MULTIPROCESSOR 246 kcpuset_t *pm_onproc; 247 kcpuset_t *pm_active; 248 #if PMAP_TLB_MAX > 1 249 u_int pm_shootdown_pending; 250 #endif 251 #endif 252 struct pmap_asid_info pm_pai[PMAP_TLB_MAX]; 253 #else 254 struct l1_ttable *pm_l1; 255 union pmap_cache_state pm_cstate; 256 uint8_t pm_domain; 257 bool pm_activated; 258 bool pm_remove_all; 259 #endif 260 }; 261 262 struct pmap_kernel { 263 struct pmap kernel_pmap; 264 }; 265 266 /* 267 * Physical / virtual address structure. In a number of places (particularly 268 * during bootstrapping) we need to keep track of the physical and virtual 269 * addresses of various pages 270 */ 271 typedef struct pv_addr { 272 SLIST_ENTRY(pv_addr) pv_list; 273 paddr_t pv_pa; 274 vaddr_t pv_va; 275 vsize_t pv_size; 276 uint8_t pv_cache; 277 uint8_t pv_prot; 278 } pv_addr_t; 279 typedef SLIST_HEAD(, pv_addr) pv_addrqh_t; 280 281 extern pv_addrqh_t pmap_freeq; 282 extern pv_addr_t kernelstack; 283 extern pv_addr_t abtstack; 284 extern pv_addr_t fiqstack; 285 extern pv_addr_t irqstack; 286 extern pv_addr_t undstack; 287 extern pv_addr_t idlestack; 288 extern pv_addr_t systempage; 289 extern pv_addr_t kernel_l1pt; 290 291 #ifdef ARM_MMU_EXTENDED 292 extern bool arm_has_tlbiasid_p; /* also in <arm/locore.h> */ 293 #endif 294 295 /* 296 * Determine various modes for PTEs (user vs. kernel, cacheable 297 * vs. non-cacheable). 298 */ 299 #define PTE_KERNEL 0 300 #define PTE_USER 1 301 #define PTE_NOCACHE 0 302 #define PTE_CACHE 1 303 #define PTE_PAGETABLE 2 304 #define PTE_DEV 3 305 306 /* 307 * Flags that indicate attributes of pages or mappings of pages. 308 * 309 * The PVF_MOD and PVF_REF flags are stored in the mdpage for each 310 * page. PVF_WIRED, PVF_WRITE, and PVF_NC are kept in individual 311 * pv_entry's for each page. They live in the same "namespace" so 312 * that we can clear multiple attributes at a time. 313 * 314 * Note the "non-cacheable" flag generally means the page has 315 * multiple mappings in a given address space. 316 */ 317 #define PVF_MOD 0x01 /* page is modified */ 318 #define PVF_REF 0x02 /* page is referenced */ 319 #define PVF_WIRED 0x04 /* mapping is wired */ 320 #define PVF_WRITE 0x08 /* mapping is writable */ 321 #define PVF_EXEC 0x10 /* mapping is executable */ 322 #ifdef PMAP_CACHE_VIVT 323 #define PVF_UNC 0x20 /* mapping is 'user' non-cacheable */ 324 #define PVF_KNC 0x40 /* mapping is 'kernel' non-cacheable */ 325 #define PVF_NC (PVF_UNC|PVF_KNC) 326 #endif 327 #ifdef PMAP_CACHE_VIPT 328 #define PVF_NC 0x20 /* mapping is 'kernel' non-cacheable */ 329 #define PVF_MULTCLR 0x40 /* mapping is multi-colored */ 330 #endif 331 #define PVF_COLORED 0x80 /* page has or had a color */ 332 #define PVF_KENTRY 0x0100 /* page entered via pmap_kenter_pa */ 333 #define PVF_KMPAGE 0x0200 /* page is used for kmem */ 334 #define PVF_DIRTY 0x0400 /* page may have dirty cache lines */ 335 #define PVF_KMOD 0x0800 /* unmanaged page is modified */ 336 #define PVF_KWRITE (PVF_KENTRY|PVF_WRITE) 337 #define PVF_DMOD (PVF_MOD|PVF_KMOD|PVF_KMPAGE) 338 339 /* 340 * Commonly referenced structures 341 */ 342 extern int pmap_debug_level; /* Only exists if PMAP_DEBUG */ 343 extern int arm_poolpage_vmfreelist; 344 345 /* 346 * Macros that we need to export 347 */ 348 #define pmap_resident_count(pmap) ((pmap)->pm_stats.resident_count) 349 #define pmap_wired_count(pmap) ((pmap)->pm_stats.wired_count) 350 351 #define pmap_is_modified(pg) \ 352 (((pg)->mdpage.pvh_attrs & PVF_MOD) != 0) 353 #define pmap_is_referenced(pg) \ 354 (((pg)->mdpage.pvh_attrs & PVF_REF) != 0) 355 #define pmap_is_page_colored_p(md) \ 356 (((md)->pvh_attrs & PVF_COLORED) != 0) 357 358 #define pmap_copy(dp, sp, da, l, sa) /* nothing */ 359 360 #define pmap_phys_address(ppn) (arm_ptob((ppn))) 361 u_int arm32_mmap_flags(paddr_t); 362 #define ARM32_MMAP_WRITECOMBINE 0x40000000 363 #define ARM32_MMAP_CACHEABLE 0x20000000 364 #define ARM_MMAP_WRITECOMBINE ARM32_MMAP_WRITECOMBINE 365 #define ARM_MMAP_CACHEABLE ARM32_MMAP_CACHEABLE 366 #define pmap_mmap_flags(ppn) arm32_mmap_flags(ppn) 367 368 #define PMAP_PTE 0x10000000 /* kenter_pa */ 369 #define PMAP_DEV 0x20000000 /* kenter_pa */ 370 #define PMAP_DEV_SO 0x40000000 /* kenter_pa */ 371 #define PMAP_DEV_MASK (PMAP_DEV | PMAP_DEV_SO) 372 373 /* 374 * Functions that we need to export 375 */ 376 void pmap_procwr(struct proc *, vaddr_t, int); 377 bool pmap_remove_all(pmap_t); 378 bool pmap_extract(pmap_t, vaddr_t, paddr_t *); 379 380 #define PMAP_NEED_PROCWR 381 #define PMAP_GROWKERNEL /* turn on pmap_growkernel interface */ 382 #define PMAP_ENABLE_PMAP_KMPAGE /* enable the PMAP_KMPAGE flag */ 383 384 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 385 #define PMAP_PREFER(hint, vap, sz, td) pmap_prefer((hint), (vap), (td)) 386 void pmap_prefer(vaddr_t, vaddr_t *, int); 387 #endif 388 389 #ifdef ARM_MMU_EXTENDED 390 int pmap_maxproc_set(int); 391 #endif 392 393 void pmap_icache_sync_range(pmap_t, vaddr_t, vaddr_t); 394 395 /* Functions we use internally. */ 396 #ifdef PMAP_STEAL_MEMORY 397 void pmap_boot_pagealloc(psize_t, psize_t, psize_t, pv_addr_t *); 398 void pmap_boot_pageadd(pv_addr_t *); 399 vaddr_t pmap_steal_memory(vsize_t, vaddr_t *, vaddr_t *); 400 #endif 401 void pmap_bootstrap(vaddr_t, vaddr_t); 402 403 void pmap_do_remove(pmap_t, vaddr_t, vaddr_t, int); 404 int pmap_fault_fixup(pmap_t, vaddr_t, vm_prot_t, int); 405 int pmap_prefetchabt_fixup(void *); 406 bool pmap_get_pde_pte(pmap_t, vaddr_t, pd_entry_t **, pt_entry_t **); 407 bool pmap_get_pde(pmap_t, vaddr_t, pd_entry_t **); 408 bool pmap_extract_coherency(pmap_t, vaddr_t, paddr_t *, bool *); 409 410 void pmap_debug(int); 411 void pmap_postinit(void); 412 413 void vector_page_setprot(int); 414 415 const struct pmap_devmap *pmap_devmap_find_pa(paddr_t, psize_t); 416 const struct pmap_devmap *pmap_devmap_find_va(vaddr_t, vsize_t); 417 418 /* Bootstrapping routines. */ 419 void pmap_map_section(vaddr_t, vaddr_t, paddr_t, int, int); 420 void pmap_map_entry(vaddr_t, vaddr_t, paddr_t, int, int); 421 vsize_t pmap_map_chunk(vaddr_t, vaddr_t, paddr_t, vsize_t, int, int); 422 void pmap_unmap_chunk(vaddr_t, vaddr_t, vsize_t); 423 void pmap_link_l2pt(vaddr_t, vaddr_t, pv_addr_t *); 424 void pmap_devmap_bootstrap(vaddr_t, const struct pmap_devmap *); 425 void pmap_devmap_register(const struct pmap_devmap *); 426 427 /* 428 * Special page zero routine for use by the idle loop (no cache cleans). 429 */ 430 bool pmap_pageidlezero(paddr_t); 431 #define PMAP_PAGEIDLEZERO(pa) pmap_pageidlezero((pa)) 432 433 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 434 /* 435 * For the pmap, this is a more useful way to map a direct mapped page. 436 * It returns either the direct-mapped VA or the VA supplied if it can't 437 * be direct mapped. 438 */ 439 vaddr_t pmap_direct_mapped_phys(paddr_t, bool *, vaddr_t); 440 #endif 441 442 /* 443 * used by dumpsys to record the PA of the L1 table 444 */ 445 uint32_t pmap_kernel_L1_addr(void); 446 /* 447 * The current top of kernel VM 448 */ 449 extern vaddr_t pmap_curmaxkvaddr; 450 451 #if defined(ARM_MMU_EXTENDED) && defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) 452 /* 453 * Ending VA of direct mapped memory (usually KERNEL_VM_BASE). 454 */ 455 extern vaddr_t pmap_directlimit; 456 #endif 457 458 /* 459 * Useful macros and constants 460 */ 461 462 /* Virtual address to page table entry */ 463 static inline pt_entry_t * 464 vtopte(vaddr_t va) 465 { 466 pd_entry_t *pdep; 467 pt_entry_t *ptep; 468 469 KASSERT(trunc_page(va) == va); 470 471 if (pmap_get_pde_pte(pmap_kernel(), va, &pdep, &ptep) == false) 472 return (NULL); 473 return (ptep); 474 } 475 476 /* 477 * Virtual address to physical address 478 */ 479 static inline paddr_t 480 vtophys(vaddr_t va) 481 { 482 paddr_t pa; 483 484 if (pmap_extract(pmap_kernel(), va, &pa) == false) 485 return (0); /* XXXSCW: Panic? */ 486 487 return (pa); 488 } 489 490 /* 491 * The new pmap ensures that page-tables are always mapping Write-Thru. 492 * Thus, on some platforms we can run fast and loose and avoid syncing PTEs 493 * on every change. 494 * 495 * Unfortunately, not all CPUs have a write-through cache mode. So we 496 * define PMAP_NEEDS_PTE_SYNC for C code to conditionally do PTE syncs, 497 * and if there is the chance for PTE syncs to be needed, we define 498 * PMAP_INCLUDE_PTE_SYNC so e.g. assembly code can include (and run) 499 * the code. 500 */ 501 extern int pmap_needs_pte_sync; 502 #if defined(_KERNEL_OPT) 503 /* 504 * Perform compile time evaluation of PMAP_NEEDS_PTE_SYNC when only a 505 * single MMU type is selected. 506 * 507 * StrongARM SA-1 caches do not have a write-through mode. So, on these, 508 * we need to do PTE syncs. Additionally, V6 MMUs also need PTE syncs. 509 * Finally, MEMC, GENERIC and XSCALE MMUs do not need PTE syncs. 510 * 511 * Use run time evaluation for all other cases. 512 * 513 */ 514 #if (ARM_NMMUS == 1) 515 #if (ARM_MMU_SA1 + ARM_MMU_V6 != 0) 516 #define PMAP_INCLUDE_PTE_SYNC 517 #define PMAP_NEEDS_PTE_SYNC 1 518 #elif (ARM_MMU_MEMC + ARM_MMU_GENERIC + ARM_MMU_XSCALE != 0) 519 #define PMAP_NEEDS_PTE_SYNC 0 520 #endif 521 #endif 522 #endif /* _KERNEL_OPT */ 523 524 /* 525 * Provide a fallback in case we were not able to determine it at 526 * compile-time. 527 */ 528 #ifndef PMAP_NEEDS_PTE_SYNC 529 #define PMAP_NEEDS_PTE_SYNC pmap_needs_pte_sync 530 #define PMAP_INCLUDE_PTE_SYNC 531 #endif 532 533 static inline void 534 pmap_ptesync(pt_entry_t *ptep, size_t cnt) 535 { 536 if (PMAP_NEEDS_PTE_SYNC) { 537 cpu_dcache_wb_range((vaddr_t)ptep, cnt * sizeof(pt_entry_t)); 538 #ifdef SHEEVA_L2_CACHE 539 cpu_sdcache_wb_range((vaddr_t)ptep, -1, 540 cnt * sizeof(pt_entry_t)); 541 #endif 542 } 543 arm_dsb(); 544 } 545 546 #define PDE_SYNC(pdep) pmap_ptesync((pdep), 1) 547 #define PDE_SYNC_RANGE(pdep, cnt) pmap_ptesync((pdep), (cnt)) 548 #define PTE_SYNC(ptep) pmap_ptesync((ptep), PAGE_SIZE / L2_S_SIZE) 549 #define PTE_SYNC_RANGE(ptep, cnt) pmap_ptesync((ptep), (cnt)) 550 551 #define l1pte_valid_p(pde) ((pde) != 0) 552 #define l1pte_section_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_S) 553 #define l1pte_supersection_p(pde) (l1pte_section_p(pde) \ 554 && ((pde) & L1_S_V6_SUPER) != 0) 555 #define l1pte_page_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_C) 556 #define l1pte_fpage_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_F) 557 #define l1pte_pa(pde) ((pde) & L1_C_ADDR_MASK) 558 #define l1pte_index(v) ((vaddr_t)(v) >> L1_S_SHIFT) 559 560 static inline void 561 l1pte_setone(pt_entry_t *pdep, pt_entry_t pde) 562 { 563 *pdep = pde; 564 } 565 566 static inline void 567 l1pte_set(pt_entry_t *pdep, pt_entry_t pde) 568 { 569 *pdep = pde; 570 if (l1pte_page_p(pde)) { 571 KASSERTMSG((((uintptr_t)pdep / sizeof(pde)) & (PAGE_SIZE / L2_T_SIZE - 1)) == 0, "%p", pdep); 572 for (int k = 1; k < PAGE_SIZE / L2_T_SIZE; k++) { 573 pde += L2_T_SIZE; 574 pdep[k] = pde; 575 } 576 } else if (l1pte_supersection_p(pde)) { 577 KASSERTMSG((((uintptr_t)pdep / sizeof(pde)) & (L1_SS_SIZE / L1_S_SIZE - 1)) == 0, "%p", pdep); 578 for (int k = 1; k < L1_SS_SIZE / L1_S_SIZE; k++) { 579 pdep[k] = pde; 580 } 581 } 582 } 583 584 #define l2pte_index(v) ((((v) & L2_ADDR_BITS) >> PGSHIFT) << (PGSHIFT-L2_S_SHIFT)) 585 #define l2pte_valid_p(pte) (((pte) & L2_TYPE_MASK) != L2_TYPE_INV) 586 #define l2pte_pa(pte) ((pte) & L2_S_FRAME) 587 #define l1pte_lpage_p(pte) (((pte) & L2_TYPE_MASK) == L2_TYPE_L) 588 #define l2pte_minidata_p(pte) (((pte) & \ 589 (L2_B | L2_C | L2_XS_T_TEX(TEX_XSCALE_X)))\ 590 == (L2_C | L2_XS_T_TEX(TEX_XSCALE_X))) 591 592 static inline void 593 l2pte_set(pt_entry_t *ptep, pt_entry_t pte, pt_entry_t opte) 594 { 595 if (l1pte_lpage_p(pte)) { 596 KASSERTMSG((((uintptr_t)ptep / sizeof(pte)) & (L2_L_SIZE / L2_S_SIZE - 1)) == 0, "%p", ptep); 597 for (int k = 0; k < L2_L_SIZE / L2_S_SIZE; k++) { 598 *ptep++ = pte; 599 } 600 } else { 601 KASSERTMSG((((uintptr_t)ptep / sizeof(pte)) & (PAGE_SIZE / L2_S_SIZE - 1)) == 0, "%p", ptep); 602 for (int k = 0; k < PAGE_SIZE / L2_S_SIZE; k++) { 603 KASSERTMSG(*ptep == opte, "%#x [*%p] != %#x", *ptep, ptep, opte); 604 *ptep++ = pte; 605 pte += L2_S_SIZE; 606 if (opte) 607 opte += L2_S_SIZE; 608 } 609 } 610 } 611 612 static inline void 613 l2pte_reset(pt_entry_t *ptep) 614 { 615 KASSERTMSG((((uintptr_t)ptep / sizeof(*ptep)) & (PAGE_SIZE / L2_S_SIZE - 1)) == 0, "%p", ptep); 616 *ptep = 0; 617 for (int k = 1; k < PAGE_SIZE / L2_S_SIZE; k++) { 618 ptep[k] = 0; 619 } 620 } 621 622 /* L1 and L2 page table macros */ 623 #define pmap_pde_v(pde) l1pte_valid(*(pde)) 624 #define pmap_pde_section(pde) l1pte_section_p(*(pde)) 625 #define pmap_pde_supersection(pde) l1pte_supersection_p(*(pde)) 626 #define pmap_pde_page(pde) l1pte_page_p(*(pde)) 627 #define pmap_pde_fpage(pde) l1pte_fpage_p(*(pde)) 628 629 #define pmap_pte_v(pte) l2pte_valid_p(*(pte)) 630 #define pmap_pte_pa(pte) l2pte_pa(*(pte)) 631 632 /* Size of the kernel part of the L1 page table */ 633 #define KERNEL_PD_SIZE \ 634 (L1_TABLE_SIZE - (KERNEL_BASE >> L1_S_SHIFT) * sizeof(pd_entry_t)) 635 636 void bzero_page(vaddr_t); 637 void bcopy_page(vaddr_t, vaddr_t); 638 639 #ifdef FPU_VFP 640 void bzero_page_vfp(vaddr_t); 641 void bcopy_page_vfp(vaddr_t, vaddr_t); 642 #endif 643 644 /************************* ARM MMU configuration *****************************/ 645 646 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 647 void pmap_copy_page_generic(paddr_t, paddr_t); 648 void pmap_zero_page_generic(paddr_t); 649 650 void pmap_pte_init_generic(void); 651 #if defined(CPU_ARM8) 652 void pmap_pte_init_arm8(void); 653 #endif 654 #if defined(CPU_ARM9) 655 void pmap_pte_init_arm9(void); 656 #endif /* CPU_ARM9 */ 657 #if defined(CPU_ARM10) 658 void pmap_pte_init_arm10(void); 659 #endif /* CPU_ARM10 */ 660 #if defined(CPU_ARM11) /* ARM_MMU_V6 */ 661 void pmap_pte_init_arm11(void); 662 #endif /* CPU_ARM11 */ 663 #if defined(CPU_ARM11MPCORE) /* ARM_MMU_V6 */ 664 void pmap_pte_init_arm11mpcore(void); 665 #endif 666 #if ARM_MMU_V6 == 1 667 void pmap_pte_init_armv6(void); 668 #endif /* ARM_MMU_V6 */ 669 #if ARM_MMU_V7 == 1 670 void pmap_pte_init_armv7(void); 671 #endif /* ARM_MMU_V7 */ 672 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */ 673 674 #if ARM_MMU_SA1 == 1 675 void pmap_pte_init_sa1(void); 676 #endif /* ARM_MMU_SA1 == 1 */ 677 678 #if ARM_MMU_XSCALE == 1 679 void pmap_copy_page_xscale(paddr_t, paddr_t); 680 void pmap_zero_page_xscale(paddr_t); 681 682 void pmap_pte_init_xscale(void); 683 684 void xscale_setup_minidata(vaddr_t, vaddr_t, paddr_t); 685 686 #define PMAP_UAREA(va) pmap_uarea(va) 687 void pmap_uarea(vaddr_t); 688 #endif /* ARM_MMU_XSCALE == 1 */ 689 690 extern pt_entry_t pte_l1_s_nocache_mode; 691 extern pt_entry_t pte_l2_l_nocache_mode; 692 extern pt_entry_t pte_l2_s_nocache_mode; 693 694 extern pt_entry_t pte_l1_s_cache_mode; 695 extern pt_entry_t pte_l2_l_cache_mode; 696 extern pt_entry_t pte_l2_s_cache_mode; 697 698 extern pt_entry_t pte_l1_s_cache_mode_pt; 699 extern pt_entry_t pte_l2_l_cache_mode_pt; 700 extern pt_entry_t pte_l2_s_cache_mode_pt; 701 702 extern pt_entry_t pte_l1_s_wc_mode; 703 extern pt_entry_t pte_l2_l_wc_mode; 704 extern pt_entry_t pte_l2_s_wc_mode; 705 706 extern pt_entry_t pte_l1_s_cache_mask; 707 extern pt_entry_t pte_l2_l_cache_mask; 708 extern pt_entry_t pte_l2_s_cache_mask; 709 710 extern pt_entry_t pte_l1_s_prot_u; 711 extern pt_entry_t pte_l1_s_prot_w; 712 extern pt_entry_t pte_l1_s_prot_ro; 713 extern pt_entry_t pte_l1_s_prot_mask; 714 715 extern pt_entry_t pte_l2_s_prot_u; 716 extern pt_entry_t pte_l2_s_prot_w; 717 extern pt_entry_t pte_l2_s_prot_ro; 718 extern pt_entry_t pte_l2_s_prot_mask; 719 720 extern pt_entry_t pte_l2_l_prot_u; 721 extern pt_entry_t pte_l2_l_prot_w; 722 extern pt_entry_t pte_l2_l_prot_ro; 723 extern pt_entry_t pte_l2_l_prot_mask; 724 725 extern pt_entry_t pte_l1_ss_proto; 726 extern pt_entry_t pte_l1_s_proto; 727 extern pt_entry_t pte_l1_c_proto; 728 extern pt_entry_t pte_l2_s_proto; 729 730 extern void (*pmap_copy_page_func)(paddr_t, paddr_t); 731 extern void (*pmap_zero_page_func)(paddr_t); 732 733 #endif /* !_LOCORE */ 734 735 /*****************************************************************************/ 736 737 #define KERNEL_PID 0 /* The kernel uses ASID 0 */ 738 739 /* 740 * Definitions for MMU domains 741 */ 742 #define PMAP_DOMAINS 15 /* 15 'user' domains (1-15) */ 743 #define PMAP_DOMAIN_KERNEL 0 /* The kernel pmap uses domain #0 */ 744 745 #ifdef ARM_MMU_EXTENDED 746 #define PMAP_DOMAIN_USER 1 /* User pmaps use domain #1 */ 747 #define DOMAIN_DEFAULT ((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | (DOMAIN_CLIENT << (PMAP_DOMAIN_USER*2))) 748 #else 749 #define DOMAIN_DEFAULT ((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2))) 750 #endif 751 752 /* 753 * These macros define the various bit masks in the PTE. 754 * 755 * We use these macros since we use different bits on different processor 756 * models. 757 */ 758 #define L1_S_PROT_U_generic (L1_S_AP(AP_U)) 759 #define L1_S_PROT_W_generic (L1_S_AP(AP_W)) 760 #define L1_S_PROT_RO_generic (0) 761 #define L1_S_PROT_MASK_generic (L1_S_PROT_U|L1_S_PROT_W|L1_S_PROT_RO) 762 763 #define L1_S_PROT_U_xscale (L1_S_AP(AP_U)) 764 #define L1_S_PROT_W_xscale (L1_S_AP(AP_W)) 765 #define L1_S_PROT_RO_xscale (0) 766 #define L1_S_PROT_MASK_xscale (L1_S_PROT_U|L1_S_PROT_W|L1_S_PROT_RO) 767 768 #define L1_S_PROT_U_armv6 (L1_S_AP(AP_R) | L1_S_AP(AP_U)) 769 #define L1_S_PROT_W_armv6 (L1_S_AP(AP_W)) 770 #define L1_S_PROT_RO_armv6 (L1_S_AP(AP_R) | L1_S_AP(AP_RO)) 771 #define L1_S_PROT_MASK_armv6 (L1_S_PROT_U|L1_S_PROT_W|L1_S_PROT_RO) 772 773 #define L1_S_PROT_U_armv7 (L1_S_AP(AP_R) | L1_S_AP(AP_U)) 774 #define L1_S_PROT_W_armv7 (L1_S_AP(AP_W)) 775 #define L1_S_PROT_RO_armv7 (L1_S_AP(AP_R) | L1_S_AP(AP_RO)) 776 #define L1_S_PROT_MASK_armv7 (L1_S_PROT_U|L1_S_PROT_W|L1_S_PROT_RO) 777 778 #define L1_S_CACHE_MASK_generic (L1_S_B|L1_S_C) 779 #define L1_S_CACHE_MASK_xscale (L1_S_B|L1_S_C|L1_S_XS_TEX(TEX_XSCALE_X)) 780 #define L1_S_CACHE_MASK_armv6 (L1_S_B|L1_S_C|L1_S_XS_TEX(TEX_ARMV6_TEX)) 781 #define L1_S_CACHE_MASK_armv6n (L1_S_B|L1_S_C|L1_S_XS_TEX(TEX_ARMV6_TEX)|L1_S_V6_S) 782 #define L1_S_CACHE_MASK_armv7 (L1_S_B|L1_S_C|L1_S_XS_TEX(TEX_ARMV6_TEX)|L1_S_V6_S) 783 784 #define L2_L_PROT_U_generic (L2_AP(AP_U)) 785 #define L2_L_PROT_W_generic (L2_AP(AP_W)) 786 #define L2_L_PROT_RO_generic (0) 787 #define L2_L_PROT_MASK_generic (L2_L_PROT_U|L2_L_PROT_W|L2_L_PROT_RO) 788 789 #define L2_L_PROT_U_xscale (L2_AP(AP_U)) 790 #define L2_L_PROT_W_xscale (L2_AP(AP_W)) 791 #define L2_L_PROT_RO_xscale (0) 792 #define L2_L_PROT_MASK_xscale (L2_L_PROT_U|L2_L_PROT_W|L2_L_PROT_RO) 793 794 #define L2_L_PROT_U_armv6n (L2_AP0(AP_R) | L2_AP0(AP_U)) 795 #define L2_L_PROT_W_armv6n (L2_AP0(AP_W)) 796 #define L2_L_PROT_RO_armv6n (L2_AP0(AP_R) | L2_AP0(AP_RO)) 797 #define L2_L_PROT_MASK_armv6n (L2_L_PROT_U|L2_L_PROT_W|L2_L_PROT_RO) 798 799 #define L2_L_PROT_U_armv7 (L2_AP0(AP_R) | L2_AP0(AP_U)) 800 #define L2_L_PROT_W_armv7 (L2_AP0(AP_W)) 801 #define L2_L_PROT_RO_armv7 (L2_AP0(AP_R) | L2_AP0(AP_RO)) 802 #define L2_L_PROT_MASK_armv7 (L2_L_PROT_U|L2_L_PROT_W|L2_L_PROT_RO) 803 804 #define L2_L_CACHE_MASK_generic (L2_B|L2_C) 805 #define L2_L_CACHE_MASK_xscale (L2_B|L2_C|L2_XS_L_TEX(TEX_XSCALE_X)) 806 #define L2_L_CACHE_MASK_armv6 (L2_B|L2_C|L2_V6_L_TEX(TEX_ARMV6_TEX)) 807 #define L2_L_CACHE_MASK_armv6n (L2_B|L2_C|L2_V6_L_TEX(TEX_ARMV6_TEX)|L2_XS_S) 808 #define L2_L_CACHE_MASK_armv7 (L2_B|L2_C|L2_V6_L_TEX(TEX_ARMV6_TEX)|L2_XS_S) 809 810 #define L2_S_PROT_U_generic (L2_AP(AP_U)) 811 #define L2_S_PROT_W_generic (L2_AP(AP_W)) 812 #define L2_S_PROT_RO_generic (0) 813 #define L2_S_PROT_MASK_generic (L2_S_PROT_U|L2_S_PROT_W|L2_S_PROT_RO) 814 815 #define L2_S_PROT_U_xscale (L2_AP0(AP_U)) 816 #define L2_S_PROT_W_xscale (L2_AP0(AP_W)) 817 #define L2_S_PROT_RO_xscale (0) 818 #define L2_S_PROT_MASK_xscale (L2_S_PROT_U|L2_S_PROT_W|L2_S_PROT_RO) 819 820 #define L2_S_PROT_U_armv6n (L2_AP0(AP_R) | L2_AP0(AP_U)) 821 #define L2_S_PROT_W_armv6n (L2_AP0(AP_W)) 822 #define L2_S_PROT_RO_armv6n (L2_AP0(AP_R) | L2_AP0(AP_RO)) 823 #define L2_S_PROT_MASK_armv6n (L2_S_PROT_U|L2_S_PROT_W|L2_S_PROT_RO) 824 825 #define L2_S_PROT_U_armv7 (L2_AP0(AP_R) | L2_AP0(AP_U)) 826 #define L2_S_PROT_W_armv7 (L2_AP0(AP_W)) 827 #define L2_S_PROT_RO_armv7 (L2_AP0(AP_R) | L2_AP0(AP_RO)) 828 #define L2_S_PROT_MASK_armv7 (L2_S_PROT_U|L2_S_PROT_W|L2_S_PROT_RO) 829 830 #define L2_S_CACHE_MASK_generic (L2_B|L2_C) 831 #define L2_S_CACHE_MASK_xscale (L2_B|L2_C|L2_XS_T_TEX(TEX_XSCALE_X)) 832 #define L2_XS_CACHE_MASK_armv6 (L2_B|L2_C|L2_V6_XS_TEX(TEX_ARMV6_TEX)) 833 #ifdef ARMV6_EXTENDED_SMALL_PAGE 834 #define L2_S_CACHE_MASK_armv6c L2_XS_CACHE_MASK_armv6 835 #else 836 #define L2_S_CACHE_MASK_armv6c L2_S_CACHE_MASK_generic 837 #endif 838 #define L2_S_CACHE_MASK_armv6n (L2_B|L2_C|L2_V6_XS_TEX(TEX_ARMV6_TEX)|L2_XS_S) 839 #define L2_S_CACHE_MASK_armv7 (L2_B|L2_C|L2_V6_XS_TEX(TEX_ARMV6_TEX)|L2_XS_S) 840 841 842 #define L1_S_PROTO_generic (L1_TYPE_S | L1_S_IMP) 843 #define L1_S_PROTO_xscale (L1_TYPE_S) 844 #define L1_S_PROTO_armv6 (L1_TYPE_S) 845 #define L1_S_PROTO_armv7 (L1_TYPE_S) 846 847 #define L1_SS_PROTO_generic 0 848 #define L1_SS_PROTO_xscale 0 849 #define L1_SS_PROTO_armv6 (L1_TYPE_S | L1_S_V6_SS) 850 #define L1_SS_PROTO_armv7 (L1_TYPE_S | L1_S_V6_SS) 851 852 #define L1_C_PROTO_generic (L1_TYPE_C | L1_C_IMP2) 853 #define L1_C_PROTO_xscale (L1_TYPE_C) 854 #define L1_C_PROTO_armv6 (L1_TYPE_C) 855 #define L1_C_PROTO_armv7 (L1_TYPE_C) 856 857 #define L2_L_PROTO (L2_TYPE_L) 858 859 #define L2_S_PROTO_generic (L2_TYPE_S) 860 #define L2_S_PROTO_xscale (L2_TYPE_XS) 861 #ifdef ARMV6_EXTENDED_SMALL_PAGE 862 #define L2_S_PROTO_armv6c (L2_TYPE_XS) /* XP=0, extended small page */ 863 #else 864 #define L2_S_PROTO_armv6c (L2_TYPE_S) /* XP=0, subpage APs */ 865 #endif 866 #ifdef ARM_MMU_EXTENDED 867 #define L2_S_PROTO_armv6n (L2_TYPE_S|L2_XS_XN) 868 #else 869 #define L2_S_PROTO_armv6n (L2_TYPE_S) /* with XP=1 */ 870 #endif 871 #ifdef ARM_MMU_EXTENDED 872 #define L2_S_PROTO_armv7 (L2_TYPE_S|L2_XS_XN) 873 #else 874 #define L2_S_PROTO_armv7 (L2_TYPE_S) 875 #endif 876 877 /* 878 * User-visible names for the ones that vary with MMU class. 879 */ 880 881 #if ARM_NMMUS > 1 882 /* More than one MMU class configured; use variables. */ 883 #define L1_S_PROT_U pte_l1_s_prot_u 884 #define L1_S_PROT_W pte_l1_s_prot_w 885 #define L1_S_PROT_RO pte_l1_s_prot_ro 886 #define L1_S_PROT_MASK pte_l1_s_prot_mask 887 888 #define L2_S_PROT_U pte_l2_s_prot_u 889 #define L2_S_PROT_W pte_l2_s_prot_w 890 #define L2_S_PROT_RO pte_l2_s_prot_ro 891 #define L2_S_PROT_MASK pte_l2_s_prot_mask 892 893 #define L2_L_PROT_U pte_l2_l_prot_u 894 #define L2_L_PROT_W pte_l2_l_prot_w 895 #define L2_L_PROT_RO pte_l2_l_prot_ro 896 #define L2_L_PROT_MASK pte_l2_l_prot_mask 897 898 #define L1_S_CACHE_MASK pte_l1_s_cache_mask 899 #define L2_L_CACHE_MASK pte_l2_l_cache_mask 900 #define L2_S_CACHE_MASK pte_l2_s_cache_mask 901 902 #define L1_SS_PROTO pte_l1_ss_proto 903 #define L1_S_PROTO pte_l1_s_proto 904 #define L1_C_PROTO pte_l1_c_proto 905 #define L2_S_PROTO pte_l2_s_proto 906 907 #define pmap_copy_page(s, d) (*pmap_copy_page_func)((s), (d)) 908 #define pmap_zero_page(d) (*pmap_zero_page_func)((d)) 909 #elif (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 910 #define L1_S_PROT_U L1_S_PROT_U_generic 911 #define L1_S_PROT_W L1_S_PROT_W_generic 912 #define L1_S_PROT_RO L1_S_PROT_RO_generic 913 #define L1_S_PROT_MASK L1_S_PROT_MASK_generic 914 915 #define L2_S_PROT_U L2_S_PROT_U_generic 916 #define L2_S_PROT_W L2_S_PROT_W_generic 917 #define L2_S_PROT_RO L2_S_PROT_RO_generic 918 #define L2_S_PROT_MASK L2_S_PROT_MASK_generic 919 920 #define L2_L_PROT_U L2_L_PROT_U_generic 921 #define L2_L_PROT_W L2_L_PROT_W_generic 922 #define L2_L_PROT_RO L2_L_PROT_RO_generic 923 #define L2_L_PROT_MASK L2_L_PROT_MASK_generic 924 925 #define L1_S_CACHE_MASK L1_S_CACHE_MASK_generic 926 #define L2_L_CACHE_MASK L2_L_CACHE_MASK_generic 927 #define L2_S_CACHE_MASK L2_S_CACHE_MASK_generic 928 929 #define L1_SS_PROTO L1_SS_PROTO_generic 930 #define L1_S_PROTO L1_S_PROTO_generic 931 #define L1_C_PROTO L1_C_PROTO_generic 932 #define L2_S_PROTO L2_S_PROTO_generic 933 934 #define pmap_copy_page(s, d) pmap_copy_page_generic((s), (d)) 935 #define pmap_zero_page(d) pmap_zero_page_generic((d)) 936 #elif ARM_MMU_V6N != 0 937 #define L1_S_PROT_U L1_S_PROT_U_armv6 938 #define L1_S_PROT_W L1_S_PROT_W_armv6 939 #define L1_S_PROT_RO L1_S_PROT_RO_armv6 940 #define L1_S_PROT_MASK L1_S_PROT_MASK_armv6 941 942 #define L2_S_PROT_U L2_S_PROT_U_armv6n 943 #define L2_S_PROT_W L2_S_PROT_W_armv6n 944 #define L2_S_PROT_RO L2_S_PROT_RO_armv6n 945 #define L2_S_PROT_MASK L2_S_PROT_MASK_armv6n 946 947 #define L2_L_PROT_U L2_L_PROT_U_armv6n 948 #define L2_L_PROT_W L2_L_PROT_W_armv6n 949 #define L2_L_PROT_RO L2_L_PROT_RO_armv6n 950 #define L2_L_PROT_MASK L2_L_PROT_MASK_armv6n 951 952 #define L1_S_CACHE_MASK L1_S_CACHE_MASK_armv6n 953 #define L2_L_CACHE_MASK L2_L_CACHE_MASK_armv6n 954 #define L2_S_CACHE_MASK L2_S_CACHE_MASK_armv6n 955 956 /* 957 * These prototypes make writeable mappings, while the other MMU types 958 * make read-only mappings. 959 */ 960 #define L1_SS_PROTO L1_SS_PROTO_armv6 961 #define L1_S_PROTO L1_S_PROTO_armv6 962 #define L1_C_PROTO L1_C_PROTO_armv6 963 #define L2_S_PROTO L2_S_PROTO_armv6n 964 965 #define pmap_copy_page(s, d) pmap_copy_page_generic((s), (d)) 966 #define pmap_zero_page(d) pmap_zero_page_generic((d)) 967 #elif ARM_MMU_V6C != 0 968 #define L1_S_PROT_U L1_S_PROT_U_generic 969 #define L1_S_PROT_W L1_S_PROT_W_generic 970 #define L1_S_PROT_RO L1_S_PROT_RO_generic 971 #define L1_S_PROT_MASK L1_S_PROT_MASK_generic 972 973 #define L2_S_PROT_U L2_S_PROT_U_generic 974 #define L2_S_PROT_W L2_S_PROT_W_generic 975 #define L2_S_PROT_RO L2_S_PROT_RO_generic 976 #define L2_S_PROT_MASK L2_S_PROT_MASK_generic 977 978 #define L2_L_PROT_U L2_L_PROT_U_generic 979 #define L2_L_PROT_W L2_L_PROT_W_generic 980 #define L2_L_PROT_RO L2_L_PROT_RO_generic 981 #define L2_L_PROT_MASK L2_L_PROT_MASK_generic 982 983 #define L1_S_CACHE_MASK L1_S_CACHE_MASK_generic 984 #define L2_L_CACHE_MASK L2_L_CACHE_MASK_generic 985 #define L2_S_CACHE_MASK L2_S_CACHE_MASK_generic 986 987 #define L1_SS_PROTO L1_SS_PROTO_armv6 988 #define L1_S_PROTO L1_S_PROTO_generic 989 #define L1_C_PROTO L1_C_PROTO_generic 990 #define L2_S_PROTO L2_S_PROTO_generic 991 992 #define pmap_copy_page(s, d) pmap_copy_page_generic((s), (d)) 993 #define pmap_zero_page(d) pmap_zero_page_generic((d)) 994 #elif ARM_MMU_XSCALE == 1 995 #define L1_S_PROT_U L1_S_PROT_U_generic 996 #define L1_S_PROT_W L1_S_PROT_W_generic 997 #define L1_S_PROT_RO L1_S_PROT_RO_generic 998 #define L1_S_PROT_MASK L1_S_PROT_MASK_generic 999 1000 #define L2_S_PROT_U L2_S_PROT_U_xscale 1001 #define L2_S_PROT_W L2_S_PROT_W_xscale 1002 #define L2_S_PROT_RO L2_S_PROT_RO_xscale 1003 #define L2_S_PROT_MASK L2_S_PROT_MASK_xscale 1004 1005 #define L2_L_PROT_U L2_L_PROT_U_generic 1006 #define L2_L_PROT_W L2_L_PROT_W_generic 1007 #define L2_L_PROT_RO L2_L_PROT_RO_generic 1008 #define L2_L_PROT_MASK L2_L_PROT_MASK_generic 1009 1010 #define L1_S_CACHE_MASK L1_S_CACHE_MASK_xscale 1011 #define L2_L_CACHE_MASK L2_L_CACHE_MASK_xscale 1012 #define L2_S_CACHE_MASK L2_S_CACHE_MASK_xscale 1013 1014 #define L1_SS_PROTO L1_SS_PROTO_xscale 1015 #define L1_S_PROTO L1_S_PROTO_xscale 1016 #define L1_C_PROTO L1_C_PROTO_xscale 1017 #define L2_S_PROTO L2_S_PROTO_xscale 1018 1019 #define pmap_copy_page(s, d) pmap_copy_page_xscale((s), (d)) 1020 #define pmap_zero_page(d) pmap_zero_page_xscale((d)) 1021 #elif ARM_MMU_V7 == 1 1022 #define L1_S_PROT_U L1_S_PROT_U_armv7 1023 #define L1_S_PROT_W L1_S_PROT_W_armv7 1024 #define L1_S_PROT_RO L1_S_PROT_RO_armv7 1025 #define L1_S_PROT_MASK L1_S_PROT_MASK_armv7 1026 1027 #define L2_S_PROT_U L2_S_PROT_U_armv7 1028 #define L2_S_PROT_W L2_S_PROT_W_armv7 1029 #define L2_S_PROT_RO L2_S_PROT_RO_armv7 1030 #define L2_S_PROT_MASK L2_S_PROT_MASK_armv7 1031 1032 #define L2_L_PROT_U L2_L_PROT_U_armv7 1033 #define L2_L_PROT_W L2_L_PROT_W_armv7 1034 #define L2_L_PROT_RO L2_L_PROT_RO_armv7 1035 #define L2_L_PROT_MASK L2_L_PROT_MASK_armv7 1036 1037 #define L1_S_CACHE_MASK L1_S_CACHE_MASK_armv7 1038 #define L2_L_CACHE_MASK L2_L_CACHE_MASK_armv7 1039 #define L2_S_CACHE_MASK L2_S_CACHE_MASK_armv7 1040 1041 /* 1042 * These prototypes make writeable mappings, while the other MMU types 1043 * make read-only mappings. 1044 */ 1045 #define L1_SS_PROTO L1_SS_PROTO_armv7 1046 #define L1_S_PROTO L1_S_PROTO_armv7 1047 #define L1_C_PROTO L1_C_PROTO_armv7 1048 #define L2_S_PROTO L2_S_PROTO_armv7 1049 1050 #define pmap_copy_page(s, d) pmap_copy_page_generic((s), (d)) 1051 #define pmap_zero_page(d) pmap_zero_page_generic((d)) 1052 #endif /* ARM_NMMUS > 1 */ 1053 1054 /* 1055 * Macros to set and query the write permission on page descriptors. 1056 */ 1057 #define l1pte_set_writable(pte) (((pte) & ~L1_S_PROT_RO) | L1_S_PROT_W) 1058 #define l1pte_set_readonly(pte) (((pte) & ~L1_S_PROT_W) | L1_S_PROT_RO) 1059 1060 #define l2pte_set_writable(pte) (((pte) & ~L2_S_PROT_RO) | L2_S_PROT_W) 1061 #define l2pte_set_readonly(pte) (((pte) & ~L2_S_PROT_W) | L2_S_PROT_RO) 1062 1063 #define l2pte_writable_p(pte) (((pte) & L2_S_PROT_W) == L2_S_PROT_W && \ 1064 (L2_S_PROT_RO == 0 || \ 1065 ((pte) & L2_S_PROT_RO) != L2_S_PROT_RO)) 1066 1067 /* 1068 * These macros return various bits based on kernel/user and protection. 1069 * Note that the compiler will usually fold these at compile time. 1070 */ 1071 1072 #define L1_S_PROT(ku, pr) ( \ 1073 (((ku) == PTE_USER) ? \ 1074 L1_S_PROT_U | (((pr) & VM_PROT_WRITE) ? L1_S_PROT_W : 0) \ 1075 : \ 1076 (((L1_S_PROT_RO && \ 1077 ((pr) & (VM_PROT_READ | VM_PROT_WRITE)) == VM_PROT_READ) ? \ 1078 L1_S_PROT_RO : L1_S_PROT_W))) \ 1079 ) 1080 1081 #define L2_L_PROT(ku, pr) ( \ 1082 (((ku) == PTE_USER) ? \ 1083 L2_L_PROT_U | (((pr) & VM_PROT_WRITE) ? L2_L_PROT_W : 0) \ 1084 : \ 1085 (((L2_L_PROT_RO && \ 1086 ((pr) & (VM_PROT_READ | VM_PROT_WRITE)) == VM_PROT_READ) ? \ 1087 L2_L_PROT_RO : L2_L_PROT_W))) \ 1088 ) 1089 1090 #define L2_S_PROT(ku, pr) ( \ 1091 (((ku) == PTE_USER) ? \ 1092 L2_S_PROT_U | (((pr) & VM_PROT_WRITE) ? L2_S_PROT_W : 0) \ 1093 : \ 1094 (((L2_S_PROT_RO && \ 1095 ((pr) & (VM_PROT_READ | VM_PROT_WRITE)) == VM_PROT_READ) ? \ 1096 L2_S_PROT_RO : L2_S_PROT_W))) \ 1097 ) 1098 1099 /* 1100 * Macros to test if a mapping is mappable with an L1 SuperSection, 1101 * L1 Section, or an L2 Large Page mapping. 1102 */ 1103 #define L1_SS_MAPPABLE_P(va, pa, size) \ 1104 ((((va) | (pa)) & L1_SS_OFFSET) == 0 && (size) >= L1_SS_SIZE) 1105 1106 #define L1_S_MAPPABLE_P(va, pa, size) \ 1107 ((((va) | (pa)) & L1_S_OFFSET) == 0 && (size) >= L1_S_SIZE) 1108 1109 #define L2_L_MAPPABLE_P(va, pa, size) \ 1110 ((((va) | (pa)) & L2_L_OFFSET) == 0 && (size) >= L2_L_SIZE) 1111 1112 #define PMAP_MAPSIZE1 L2_L_SIZE 1113 #define PMAP_MAPSIZE2 L1_S_SIZE 1114 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 1115 #define PMAP_MAPSIZE3 L1_SS_SIZE 1116 #endif 1117 1118 #ifndef _LOCORE 1119 /* 1120 * Hooks for the pool allocator. 1121 */ 1122 #define POOL_VTOPHYS(va) vtophys((vaddr_t) (va)) 1123 extern paddr_t physical_start, physical_end; 1124 #ifdef PMAP_NEED_ALLOC_POOLPAGE 1125 struct vm_page *arm_pmap_alloc_poolpage(int); 1126 #define PMAP_ALLOC_POOLPAGE arm_pmap_alloc_poolpage 1127 #endif 1128 #if defined(PMAP_NEED_ALLOC_POOLPAGE) || defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) 1129 vaddr_t pmap_map_poolpage(paddr_t); 1130 paddr_t pmap_unmap_poolpage(vaddr_t); 1131 #define PMAP_MAP_POOLPAGE(pa) pmap_map_poolpage(pa) 1132 #define PMAP_UNMAP_POOLPAGE(va) pmap_unmap_poolpage(va) 1133 #endif 1134 1135 #define __HAVE_PMAP_PV_TRACK 1 1136 1137 void pmap_pv_protect(paddr_t, vm_prot_t); 1138 1139 struct pmap_page { 1140 SLIST_HEAD(,pv_entry) pvh_list; /* pv_entry list */ 1141 int pvh_attrs; /* page attributes */ 1142 u_int uro_mappings; 1143 u_int urw_mappings; 1144 union { 1145 u_short s_mappings[2]; /* Assume kernel count <= 65535 */ 1146 u_int i_mappings; 1147 } k_u; 1148 }; 1149 1150 /* 1151 * pmap-specific data store in the vm_page structure. 1152 */ 1153 #define __HAVE_VM_PAGE_MD 1154 struct vm_page_md { 1155 struct pmap_page pp; 1156 #define pvh_list pp.pvh_list 1157 #define pvh_attrs pp.pvh_attrs 1158 #define uro_mappings pp.uro_mappings 1159 #define urw_mappings pp.urw_mappings 1160 #define kro_mappings pp.k_u.s_mappings[0] 1161 #define krw_mappings pp.k_u.s_mappings[1] 1162 #define k_mappings pp.k_u.i_mappings 1163 }; 1164 1165 #define PMAP_PAGE_TO_MD(ppage) container_of((ppage), struct vm_page_md, pp) 1166 1167 /* 1168 * Set the default color of each page. 1169 */ 1170 #if ARM_MMU_V6 > 0 1171 #define VM_MDPAGE_PVH_ATTRS_INIT(pg) \ 1172 (pg)->mdpage.pvh_attrs = VM_PAGE_TO_PHYS(pg) & arm_cache_prefer_mask 1173 #else 1174 #define VM_MDPAGE_PVH_ATTRS_INIT(pg) \ 1175 (pg)->mdpage.pvh_attrs = 0 1176 #endif 1177 1178 #define VM_MDPAGE_INIT(pg) \ 1179 do { \ 1180 SLIST_INIT(&(pg)->mdpage.pvh_list); \ 1181 VM_MDPAGE_PVH_ATTRS_INIT(pg); \ 1182 (pg)->mdpage.uro_mappings = 0; \ 1183 (pg)->mdpage.urw_mappings = 0; \ 1184 (pg)->mdpage.k_mappings = 0; \ 1185 } while (/*CONSTCOND*/0) 1186 1187 #endif /* !_LOCORE */ 1188 1189 #ifndef __BSD_PTENTRY_T__ 1190 #define __BSD_PTENTRY_T__ 1191 typedef uint32_t pt_entry_t; 1192 #define PRIxPTE PRIx32 1193 #endif 1194 1195 #endif /* _KERNEL */ 1196 1197 #endif /* _ARM32_PMAP_H_ */ 1198
Indexes created Mon Sep 29 18:09:42 GMT 2025