pmap.h revision 1.166.2.1
1 /* $NetBSD: pmap.h,v 1.166.2.1 2020/04/20 11:28:53 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 2002, 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe & Steve C. Woodford for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Copyright (c) 1994,1995 Mark Brinicombe. 40 * All rights reserved. 41 * 42 * Redistribution and use in source and binary forms, with or without 43 * modification, are permitted provided that the following conditions 44 * are met: 45 * 1. Redistributions of source code must retain the above copyright 46 * notice, this list of conditions and the following disclaimer. 47 * 2. Redistributions in binary form must reproduce the above copyright 48 * notice, this list of conditions and the following disclaimer in the 49 * documentation and/or other materials provided with the distribution. 50 * 3. All advertising materials mentioning features or use of this software 51 * must display the following acknowledgement: 52 * This product includes software developed by Mark Brinicombe 53 * 4. The name of the author may not be used to endorse or promote products 54 * derived from this software without specific prior written permission. 55 * 56 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 57 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 58 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 59 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 60 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 61 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 62 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 63 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 64 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 65 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 #ifndef _ARM32_PMAP_H_ 69 #define _ARM32_PMAP_H_ 70 71 #ifdef _KERNEL 72 73 #include <arm/cpuconf.h> 74 #include <arm/arm32/pte.h> 75 #ifndef _LOCORE 76 #if defined(_KERNEL_OPT) 77 #include "opt_arm32_pmap.h" 78 #include "opt_multiprocessor.h" 79 #endif 80 #include <arm/cpufunc.h> 81 #include <arm/locore.h> 82 #include <uvm/uvm_object.h> 83 #include <uvm/pmap/pmap_pvt.h> 84 #endif 85 86 #ifdef ARM_MMU_EXTENDED 87 #define PMAP_HWPAGEWALKER 1 88 #define PMAP_TLB_MAX 1 89 #if PMAP_TLB_MAX > 1 90 #define PMAP_TLB_NEED_SHOOTDOWN 1 91 #endif 92 #define PMAP_TLB_FLUSH_ASID_ON_RESET (arm_has_tlbiasid_p) 93 #define PMAP_TLB_NUM_PIDS 256 94 #define cpu_set_tlb_info(ci, ti) ((void)((ci)->ci_tlb_info = (ti))) 95 #if PMAP_TLB_MAX > 1 96 #define cpu_tlb_info(ci) ((ci)->ci_tlb_info) 97 #else 98 #define cpu_tlb_info(ci) (&pmap_tlb0_info) 99 #endif 100 #define pmap_md_tlb_asid_max() (PMAP_TLB_NUM_PIDS - 1) 101 #include <uvm/pmap/tlb.h> 102 #include <uvm/pmap/pmap_tlb.h> 103 104 /* 105 * If we have an EXTENDED MMU and the address space is split evenly between 106 * user and kernel, we can use the TTBR0/TTBR1 to have separate L1 tables for 107 * user and kernel address spaces. 108 */ 109 #if (KERNEL_BASE & 0x80000000) == 0 110 #error ARMv6 or later systems must have a KERNEL_BASE >= 0x80000000 111 #endif 112 #endif /* ARM_MMU_EXTENDED */ 113 114 /* 115 * a pmap describes a processes' 4GB virtual address space. this 116 * virtual address space can be broken up into 4096 1MB regions which 117 * are described by L1 PTEs in the L1 table. 118 * 119 * There is a line drawn at KERNEL_BASE. Everything below that line 120 * changes when the VM context is switched. Everything above that line 121 * is the same no matter which VM context is running. This is achieved 122 * by making the L1 PTEs for those slots above KERNEL_BASE reference 123 * kernel L2 tables. 124 * 125 * The basic layout of the virtual address space thus looks like this: 126 * 127 * 0xffffffff 128 * . 129 * . 130 * . 131 * KERNEL_BASE 132 * -------------------- 133 * . 134 * . 135 * . 136 * 0x00000000 137 */ 138 139 /* 140 * The number of L2 descriptor tables which can be tracked by an l2_dtable. 141 * A bucket size of 16 provides for 16MB of contiguous virtual address 142 * space per l2_dtable. Most processes will, therefore, require only two or 143 * three of these to map their whole working set. 144 */ 145 #define L2_BUCKET_XLOG2 (L1_S_SHIFT) 146 #define L2_BUCKET_XSIZE (1 << L2_BUCKET_XLOG2) 147 #define L2_BUCKET_LOG2 4 148 #define L2_BUCKET_SIZE (1 << L2_BUCKET_LOG2) 149 150 /* 151 * Given the above "L2-descriptors-per-l2_dtable" constant, the number 152 * of l2_dtable structures required to track all possible page descriptors 153 * mappable by an L1 translation table is given by the following constants: 154 */ 155 #define L2_LOG2 (32 - (L2_BUCKET_XLOG2 + L2_BUCKET_LOG2)) 156 #define L2_SIZE (1 << L2_LOG2) 157 158 /* 159 * tell MI code that the cache is virtually-indexed. 160 * ARMv6 is physically-tagged but all others are virtually-tagged. 161 */ 162 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 163 #define PMAP_CACHE_VIPT 164 #else 165 #define PMAP_CACHE_VIVT 166 #endif 167 168 #ifndef _LOCORE 169 170 #ifndef ARM_MMU_EXTENDED 171 struct l1_ttable; 172 struct l2_dtable; 173 174 /* 175 * Track cache/tlb occupancy using the following structure 176 */ 177 union pmap_cache_state { 178 struct { 179 union { 180 uint8_t csu_cache_b[2]; 181 uint16_t csu_cache; 182 } cs_cache_u; 183 184 union { 185 uint8_t csu_tlb_b[2]; 186 uint16_t csu_tlb; 187 } cs_tlb_u; 188 } cs_s; 189 uint32_t cs_all; 190 }; 191 #define cs_cache_id cs_s.cs_cache_u.csu_cache_b[0] 192 #define cs_cache_d cs_s.cs_cache_u.csu_cache_b[1] 193 #define cs_cache cs_s.cs_cache_u.csu_cache 194 #define cs_tlb_id cs_s.cs_tlb_u.csu_tlb_b[0] 195 #define cs_tlb_d cs_s.cs_tlb_u.csu_tlb_b[1] 196 #define cs_tlb cs_s.cs_tlb_u.csu_tlb 197 198 /* 199 * Assigned to cs_all to force cacheops to work for a particular pmap 200 */ 201 #define PMAP_CACHE_STATE_ALL 0xffffffffu 202 #endif /* !ARM_MMU_EXTENDED */ 203 204 /* 205 * This structure is used by machine-dependent code to describe 206 * static mappings of devices, created at bootstrap time. 207 */ 208 struct pmap_devmap { 209 vaddr_t pd_va; /* virtual address */ 210 paddr_t pd_pa; /* physical address */ 211 psize_t pd_size; /* size of region */ 212 vm_prot_t pd_prot; /* protection code */ 213 int pd_cache; /* cache attributes */ 214 }; 215 216 #define DEVMAP_ALIGN(a) ((a) & ~L1_S_OFFSET) 217 #define DEVMAP_SIZE(s) roundup2((s), L1_S_SIZE) 218 #define DEVMAP_ENTRY(va, pa, sz) \ 219 { \ 220 .pd_va = DEVMAP_ALIGN(va), \ 221 .pd_pa = DEVMAP_ALIGN(pa), \ 222 .pd_size = DEVMAP_SIZE(sz), \ 223 .pd_prot = VM_PROT_READ|VM_PROT_WRITE, \ 224 .pd_cache = PTE_DEV \ 225 } 226 #define DEVMAP_ENTRY_END { 0 } 227 228 /* 229 * The pmap structure itself 230 */ 231 struct pmap { 232 kmutex_t pm_lock; 233 u_int pm_refs; 234 #ifndef ARM_HAS_VBAR 235 pd_entry_t *pm_pl1vec; 236 pd_entry_t pm_l1vec; 237 #endif 238 struct l2_dtable *pm_l2[L2_SIZE]; 239 struct pmap_statistics pm_stats; 240 LIST_ENTRY(pmap) pm_list; 241 #ifdef ARM_MMU_EXTENDED 242 pd_entry_t *pm_l1; 243 paddr_t pm_l1_pa; 244 bool pm_remove_all; 245 #ifdef MULTIPROCESSOR 246 kcpuset_t *pm_onproc; 247 kcpuset_t *pm_active; 248 #if PMAP_TLB_MAX > 1 249 u_int pm_shootdown_pending; 250 #endif 251 #endif 252 struct pmap_asid_info pm_pai[PMAP_TLB_MAX]; 253 #else 254 struct l1_ttable *pm_l1; 255 union pmap_cache_state pm_cstate; 256 uint8_t pm_domain; 257 bool pm_activated; 258 bool pm_remove_all; 259 #endif 260 }; 261 262 struct pmap_kernel { 263 struct pmap kernel_pmap; 264 }; 265 266 /* 267 * Physical / virtual address structure. In a number of places (particularly 268 * during bootstrapping) we need to keep track of the physical and virtual 269 * addresses of various pages 270 */ 271 typedef struct pv_addr { 272 SLIST_ENTRY(pv_addr) pv_list; 273 paddr_t pv_pa; 274 vaddr_t pv_va; 275 vsize_t pv_size; 276 uint8_t pv_cache; 277 uint8_t pv_prot; 278 } pv_addr_t; 279 typedef SLIST_HEAD(, pv_addr) pv_addrqh_t; 280 281 extern pv_addrqh_t pmap_freeq; 282 extern pv_addr_t kernelstack; 283 extern pv_addr_t abtstack; 284 extern pv_addr_t fiqstack; 285 extern pv_addr_t irqstack; 286 extern pv_addr_t undstack; 287 extern pv_addr_t idlestack; 288 extern pv_addr_t systempage; 289 extern pv_addr_t kernel_l1pt; 290 291 #ifdef ARM_MMU_EXTENDED 292 extern bool arm_has_tlbiasid_p; /* also in <arm/locore.h> */ 293 #endif 294 295 /* 296 * Determine various modes for PTEs (user vs. kernel, cacheable 297 * vs. non-cacheable). 298 */ 299 #define PTE_KERNEL 0 300 #define PTE_USER 1 301 #define PTE_NOCACHE 0 302 #define PTE_CACHE 1 303 #define PTE_PAGETABLE 2 304 #define PTE_DEV 3 305 306 /* 307 * Flags that indicate attributes of pages or mappings of pages. 308 * 309 * The PVF_MOD and PVF_REF flags are stored in the mdpage for each 310 * page. PVF_WIRED, PVF_WRITE, and PVF_NC are kept in individual 311 * pv_entry's for each page. They live in the same "namespace" so 312 * that we can clear multiple attributes at a time. 313 * 314 * Note the "non-cacheable" flag generally means the page has 315 * multiple mappings in a given address space. 316 */ 317 #define PVF_MOD 0x01 /* page is modified */ 318 #define PVF_REF 0x02 /* page is referenced */ 319 #define PVF_WIRED 0x04 /* mapping is wired */ 320 #define PVF_WRITE 0x08 /* mapping is writable */ 321 #define PVF_EXEC 0x10 /* mapping is executable */ 322 #ifdef PMAP_CACHE_VIVT 323 #define PVF_UNC 0x20 /* mapping is 'user' non-cacheable */ 324 #define PVF_KNC 0x40 /* mapping is 'kernel' non-cacheable */ 325 #define PVF_NC (PVF_UNC|PVF_KNC) 326 #endif 327 #ifdef PMAP_CACHE_VIPT 328 #define PVF_NC 0x20 /* mapping is 'kernel' non-cacheable */ 329 #define PVF_MULTCLR 0x40 /* mapping is multi-colored */ 330 #endif 331 #define PVF_COLORED 0x80 /* page has or had a color */ 332 #define PVF_KENTRY 0x0100 /* page entered via pmap_kenter_pa */ 333 #define PVF_KMPAGE 0x0200 /* page is used for kmem */ 334 #define PVF_DIRTY 0x0400 /* page may have dirty cache lines */ 335 #define PVF_KMOD 0x0800 /* unmanaged page is modified */ 336 #define PVF_KWRITE (PVF_KENTRY|PVF_WRITE) 337 #define PVF_DMOD (PVF_MOD|PVF_KMOD|PVF_KMPAGE) 338 339 /* 340 * Commonly referenced structures 341 */ 342 extern int arm_poolpage_vmfreelist; 343 344 /* 345 * Macros that we need to export 346 */ 347 #define pmap_resident_count(pmap) ((pmap)->pm_stats.resident_count) 348 #define pmap_wired_count(pmap) ((pmap)->pm_stats.wired_count) 349 350 #define pmap_is_modified(pg) \ 351 (((pg)->mdpage.pvh_attrs & PVF_MOD) != 0) 352 #define pmap_is_referenced(pg) \ 353 (((pg)->mdpage.pvh_attrs & PVF_REF) != 0) 354 #define pmap_is_page_colored_p(md) \ 355 (((md)->pvh_attrs & PVF_COLORED) != 0) 356 357 #define pmap_copy(dp, sp, da, l, sa) /* nothing */ 358 359 #define pmap_phys_address(ppn) (arm_ptob((ppn))) 360 u_int arm32_mmap_flags(paddr_t); 361 #define ARM32_MMAP_WRITECOMBINE 0x40000000 362 #define ARM32_MMAP_CACHEABLE 0x20000000 363 #define ARM_MMAP_WRITECOMBINE ARM32_MMAP_WRITECOMBINE 364 #define ARM_MMAP_CACHEABLE ARM32_MMAP_CACHEABLE 365 #define pmap_mmap_flags(ppn) arm32_mmap_flags(ppn) 366 367 #define PMAP_PTE 0x10000000 /* kenter_pa */ 368 #define PMAP_DEV 0x20000000 /* kenter_pa */ 369 #define PMAP_DEV_SO 0x40000000 /* kenter_pa */ 370 #define PMAP_DEV_MASK (PMAP_DEV | PMAP_DEV_SO) 371 372 /* 373 * Functions that we need to export 374 */ 375 void pmap_procwr(struct proc *, vaddr_t, int); 376 bool pmap_remove_all(pmap_t); 377 bool pmap_extract(pmap_t, vaddr_t, paddr_t *); 378 379 #define PMAP_NEED_PROCWR 380 #define PMAP_GROWKERNEL /* turn on pmap_growkernel interface */ 381 #define PMAP_ENABLE_PMAP_KMPAGE /* enable the PMAP_KMPAGE flag */ 382 383 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 384 #define PMAP_PREFER(hint, vap, sz, td) pmap_prefer((hint), (vap), (td)) 385 void pmap_prefer(vaddr_t, vaddr_t *, int); 386 #endif 387 388 #ifdef ARM_MMU_EXTENDED 389 int pmap_maxproc_set(int); 390 #endif 391 392 void pmap_icache_sync_range(pmap_t, vaddr_t, vaddr_t); 393 394 /* Functions we use internally. */ 395 #ifdef PMAP_STEAL_MEMORY 396 void pmap_boot_pagealloc(psize_t, psize_t, psize_t, pv_addr_t *); 397 void pmap_boot_pageadd(pv_addr_t *); 398 vaddr_t pmap_steal_memory(vsize_t, vaddr_t *, vaddr_t *); 399 #endif 400 void pmap_bootstrap(vaddr_t, vaddr_t); 401 402 void pmap_do_remove(pmap_t, vaddr_t, vaddr_t, int); 403 int pmap_fault_fixup(pmap_t, vaddr_t, vm_prot_t, int); 404 int pmap_prefetchabt_fixup(void *); 405 bool pmap_get_pde_pte(pmap_t, vaddr_t, pd_entry_t **, pt_entry_t **); 406 bool pmap_get_pde(pmap_t, vaddr_t, pd_entry_t **); 407 bool pmap_extract_coherency(pmap_t, vaddr_t, paddr_t *, bool *); 408 409 void pmap_postinit(void); 410 411 void vector_page_setprot(int); 412 413 const struct pmap_devmap *pmap_devmap_find_pa(paddr_t, psize_t); 414 const struct pmap_devmap *pmap_devmap_find_va(vaddr_t, vsize_t); 415 416 /* Bootstrapping routines. */ 417 void pmap_map_section(vaddr_t, vaddr_t, paddr_t, int, int); 418 void pmap_map_entry(vaddr_t, vaddr_t, paddr_t, int, int); 419 vsize_t pmap_map_chunk(vaddr_t, vaddr_t, paddr_t, vsize_t, int, int); 420 void pmap_unmap_chunk(vaddr_t, vaddr_t, vsize_t); 421 void pmap_link_l2pt(vaddr_t, vaddr_t, pv_addr_t *); 422 void pmap_devmap_bootstrap(vaddr_t, const struct pmap_devmap *); 423 void pmap_devmap_register(const struct pmap_devmap *); 424 425 /* 426 * Special page zero routine for use by the idle loop (no cache cleans). 427 */ 428 bool pmap_pageidlezero(paddr_t); 429 #define PMAP_PAGEIDLEZERO(pa) pmap_pageidlezero((pa)) 430 431 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 432 /* 433 * For the pmap, this is a more useful way to map a direct mapped page. 434 * It returns either the direct-mapped VA or the VA supplied if it can't 435 * be direct mapped. 436 */ 437 vaddr_t pmap_direct_mapped_phys(paddr_t, bool *, vaddr_t); 438 #endif 439 440 /* 441 * used by dumpsys to record the PA of the L1 table 442 */ 443 uint32_t pmap_kernel_L1_addr(void); 444 /* 445 * The current top of kernel VM 446 */ 447 extern vaddr_t pmap_curmaxkvaddr; 448 449 #if defined(ARM_MMU_EXTENDED) && defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) 450 /* 451 * Ending VA of direct mapped memory (usually KERNEL_VM_BASE). 452 */ 453 extern vaddr_t pmap_directlimit; 454 #endif 455 456 /* 457 * Useful macros and constants 458 */ 459 460 /* Virtual address to page table entry */ 461 static inline pt_entry_t * 462 vtopte(vaddr_t va) 463 { 464 pd_entry_t *pdep; 465 pt_entry_t *ptep; 466 467 KASSERT(trunc_page(va) == va); 468 469 if (pmap_get_pde_pte(pmap_kernel(), va, &pdep, &ptep) == false) 470 return (NULL); 471 return (ptep); 472 } 473 474 /* 475 * Virtual address to physical address 476 */ 477 static inline paddr_t 478 vtophys(vaddr_t va) 479 { 480 paddr_t pa; 481 482 if (pmap_extract(pmap_kernel(), va, &pa) == false) 483 return (0); /* XXXSCW: Panic? */ 484 485 return (pa); 486 } 487 488 /* 489 * The new pmap ensures that page-tables are always mapping Write-Thru. 490 * Thus, on some platforms we can run fast and loose and avoid syncing PTEs 491 * on every change. 492 * 493 * Unfortunately, not all CPUs have a write-through cache mode. So we 494 * define PMAP_NEEDS_PTE_SYNC for C code to conditionally do PTE syncs, 495 * and if there is the chance for PTE syncs to be needed, we define 496 * PMAP_INCLUDE_PTE_SYNC so e.g. assembly code can include (and run) 497 * the code. 498 */ 499 extern int pmap_needs_pte_sync; 500 #if defined(_KERNEL_OPT) 501 /* 502 * Perform compile time evaluation of PMAP_NEEDS_PTE_SYNC when only a 503 * single MMU type is selected. 504 * 505 * StrongARM SA-1 caches do not have a write-through mode. So, on these, 506 * we need to do PTE syncs. Additionally, V6 MMUs also need PTE syncs. 507 * Finally, MEMC, GENERIC and XSCALE MMUs do not need PTE syncs. 508 * 509 * Use run time evaluation for all other cases. 510 * 511 */ 512 #if (ARM_NMMUS == 1) 513 #if (ARM_MMU_SA1 + ARM_MMU_V6 != 0) 514 #define PMAP_INCLUDE_PTE_SYNC 515 #define PMAP_NEEDS_PTE_SYNC 1 516 #elif (ARM_MMU_MEMC + ARM_MMU_GENERIC + ARM_MMU_XSCALE != 0) 517 #define PMAP_NEEDS_PTE_SYNC 0 518 #endif 519 #endif 520 #endif /* _KERNEL_OPT */ 521 522 /* 523 * Provide a fallback in case we were not able to determine it at 524 * compile-time. 525 */ 526 #ifndef PMAP_NEEDS_PTE_SYNC 527 #define PMAP_NEEDS_PTE_SYNC pmap_needs_pte_sync 528 #define PMAP_INCLUDE_PTE_SYNC 529 #endif 530 531 static inline void 532 pmap_ptesync(pt_entry_t *ptep, size_t cnt) 533 { 534 if (PMAP_NEEDS_PTE_SYNC) { 535 cpu_dcache_wb_range((vaddr_t)ptep, cnt * sizeof(pt_entry_t)); 536 #ifdef SHEEVA_L2_CACHE 537 cpu_sdcache_wb_range((vaddr_t)ptep, -1, 538 cnt * sizeof(pt_entry_t)); 539 #endif 540 } 541 arm_dsb(); 542 } 543 544 #define PDE_SYNC(pdep) pmap_ptesync((pdep), 1) 545 #define PDE_SYNC_RANGE(pdep, cnt) pmap_ptesync((pdep), (cnt)) 546 #define PTE_SYNC(ptep) pmap_ptesync((ptep), PAGE_SIZE / L2_S_SIZE) 547 #define PTE_SYNC_RANGE(ptep, cnt) pmap_ptesync((ptep), (cnt)) 548 549 #define l1pte_valid_p(pde) ((pde) != 0) 550 #define l1pte_section_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_S) 551 #define l1pte_supersection_p(pde) (l1pte_section_p(pde) \ 552 && ((pde) & L1_S_V6_SUPER) != 0) 553 #define l1pte_page_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_C) 554 #define l1pte_fpage_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_F) 555 #define l1pte_pa(pde) ((pde) & L1_C_ADDR_MASK) 556 #define l1pte_index(v) ((vaddr_t)(v) >> L1_S_SHIFT) 557 558 static inline void 559 l1pte_setone(pt_entry_t *pdep, pt_entry_t pde) 560 { 561 *pdep = pde; 562 } 563 564 static inline void 565 l1pte_set(pt_entry_t *pdep, pt_entry_t pde) 566 { 567 *pdep = pde; 568 if (l1pte_page_p(pde)) { 569 KASSERTMSG((((uintptr_t)pdep / sizeof(pde)) & (PAGE_SIZE / L2_T_SIZE - 1)) == 0, "%p", pdep); 570 for (int k = 1; k < PAGE_SIZE / L2_T_SIZE; k++) { 571 pde += L2_T_SIZE; 572 pdep[k] = pde; 573 } 574 } else if (l1pte_supersection_p(pde)) { 575 KASSERTMSG((((uintptr_t)pdep / sizeof(pde)) & (L1_SS_SIZE / L1_S_SIZE - 1)) == 0, "%p", pdep); 576 for (int k = 1; k < L1_SS_SIZE / L1_S_SIZE; k++) { 577 pdep[k] = pde; 578 } 579 } 580 } 581 582 #define l2pte_index(v) ((((v) & L2_ADDR_BITS) >> PGSHIFT) << (PGSHIFT-L2_S_SHIFT)) 583 #define l2pte_valid_p(pte) (((pte) & L2_TYPE_MASK) != L2_TYPE_INV) 584 #define l2pte_pa(pte) ((pte) & L2_S_FRAME) 585 #define l1pte_lpage_p(pte) (((pte) & L2_TYPE_MASK) == L2_TYPE_L) 586 #define l2pte_minidata_p(pte) (((pte) & \ 587 (L2_B | L2_C | L2_XS_T_TEX(TEX_XSCALE_X)))\ 588 == (L2_C | L2_XS_T_TEX(TEX_XSCALE_X))) 589 590 static inline void 591 l2pte_set(pt_entry_t *ptep, pt_entry_t pte, pt_entry_t opte) 592 { 593 if (l1pte_lpage_p(pte)) { 594 KASSERTMSG((((uintptr_t)ptep / sizeof(pte)) & (L2_L_SIZE / L2_S_SIZE - 1)) == 0, "%p", ptep); 595 for (int k = 0; k < L2_L_SIZE / L2_S_SIZE; k++) { 596 *ptep++ = pte; 597 } 598 } else { 599 KASSERTMSG((((uintptr_t)ptep / sizeof(pte)) & (PAGE_SIZE / L2_S_SIZE - 1)) == 0, "%p", ptep); 600 for (int k = 0; k < PAGE_SIZE / L2_S_SIZE; k++) { 601 KASSERTMSG(*ptep == opte, "%#x [*%p] != %#x", *ptep, ptep, opte); 602 *ptep++ = pte; 603 pte += L2_S_SIZE; 604 if (opte) 605 opte += L2_S_SIZE; 606 } 607 } 608 } 609 610 static inline void 611 l2pte_reset(pt_entry_t *ptep) 612 { 613 KASSERTMSG((((uintptr_t)ptep / sizeof(*ptep)) & (PAGE_SIZE / L2_S_SIZE - 1)) == 0, "%p", ptep); 614 *ptep = 0; 615 for (int k = 1; k < PAGE_SIZE / L2_S_SIZE; k++) { 616 ptep[k] = 0; 617 } 618 } 619 620 /* L1 and L2 page table macros */ 621 #define pmap_pde_v(pde) l1pte_valid(*(pde)) 622 #define pmap_pde_section(pde) l1pte_section_p(*(pde)) 623 #define pmap_pde_supersection(pde) l1pte_supersection_p(*(pde)) 624 #define pmap_pde_page(pde) l1pte_page_p(*(pde)) 625 #define pmap_pde_fpage(pde) l1pte_fpage_p(*(pde)) 626 627 #define pmap_pte_v(pte) l2pte_valid_p(*(pte)) 628 #define pmap_pte_pa(pte) l2pte_pa(*(pte)) 629 630 /* Size of the kernel part of the L1 page table */ 631 #define KERNEL_PD_SIZE \ 632 (L1_TABLE_SIZE - (KERNEL_BASE >> L1_S_SHIFT) * sizeof(pd_entry_t)) 633 634 void bzero_page(vaddr_t); 635 void bcopy_page(vaddr_t, vaddr_t); 636 637 #ifdef FPU_VFP 638 void bzero_page_vfp(vaddr_t); 639 void bcopy_page_vfp(vaddr_t, vaddr_t); 640 #endif 641 642 /************************* ARM MMU configuration *****************************/ 643 644 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 645 void pmap_copy_page_generic(paddr_t, paddr_t); 646 void pmap_zero_page_generic(paddr_t); 647 648 void pmap_pte_init_generic(void); 649 #if defined(CPU_ARM8) 650 void pmap_pte_init_arm8(void); 651 #endif 652 #if defined(CPU_ARM9) 653 void pmap_pte_init_arm9(void); 654 #endif /* CPU_ARM9 */ 655 #if defined(CPU_ARM10) 656 void pmap_pte_init_arm10(void); 657 #endif /* CPU_ARM10 */ 658 #if defined(CPU_ARM11) /* ARM_MMU_V6 */ 659 void pmap_pte_init_arm11(void); 660 #endif /* CPU_ARM11 */ 661 #if defined(CPU_ARM11MPCORE) /* ARM_MMU_V6 */ 662 void pmap_pte_init_arm11mpcore(void); 663 #endif 664 #if ARM_MMU_V6 == 1 665 void pmap_pte_init_armv6(void); 666 #endif /* ARM_MMU_V6 */ 667 #if ARM_MMU_V7 == 1 668 void pmap_pte_init_armv7(void); 669 #endif /* ARM_MMU_V7 */ 670 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */ 671 672 #if ARM_MMU_SA1 == 1 673 void pmap_pte_init_sa1(void); 674 #endif /* ARM_MMU_SA1 == 1 */ 675 676 #if ARM_MMU_XSCALE == 1 677 void pmap_copy_page_xscale(paddr_t, paddr_t); 678 void pmap_zero_page_xscale(paddr_t); 679 680 void pmap_pte_init_xscale(void); 681 682 void xscale_setup_minidata(vaddr_t, vaddr_t, paddr_t); 683 684 #define PMAP_UAREA(va) pmap_uarea(va) 685 void pmap_uarea(vaddr_t); 686 #endif /* ARM_MMU_XSCALE == 1 */ 687 688 extern pt_entry_t pte_l1_s_nocache_mode; 689 extern pt_entry_t pte_l2_l_nocache_mode; 690 extern pt_entry_t pte_l2_s_nocache_mode; 691 692 extern pt_entry_t pte_l1_s_cache_mode; 693 extern pt_entry_t pte_l2_l_cache_mode; 694 extern pt_entry_t pte_l2_s_cache_mode; 695 696 extern pt_entry_t pte_l1_s_cache_mode_pt; 697 extern pt_entry_t pte_l2_l_cache_mode_pt; 698 extern pt_entry_t pte_l2_s_cache_mode_pt; 699 700 extern pt_entry_t pte_l1_s_wc_mode; 701 extern pt_entry_t pte_l2_l_wc_mode; 702 extern pt_entry_t pte_l2_s_wc_mode; 703 704 extern pt_entry_t pte_l1_s_cache_mask; 705 extern pt_entry_t pte_l2_l_cache_mask; 706 extern pt_entry_t pte_l2_s_cache_mask; 707 708 extern pt_entry_t pte_l1_s_prot_u; 709 extern pt_entry_t pte_l1_s_prot_w; 710 extern pt_entry_t pte_l1_s_prot_ro; 711 extern pt_entry_t pte_l1_s_prot_mask; 712 713 extern pt_entry_t pte_l2_s_prot_u; 714 extern pt_entry_t pte_l2_s_prot_w; 715 extern pt_entry_t pte_l2_s_prot_ro; 716 extern pt_entry_t pte_l2_s_prot_mask; 717 718 extern pt_entry_t pte_l2_l_prot_u; 719 extern pt_entry_t pte_l2_l_prot_w; 720 extern pt_entry_t pte_l2_l_prot_ro; 721 extern pt_entry_t pte_l2_l_prot_mask; 722 723 extern pt_entry_t pte_l1_ss_proto; 724 extern pt_entry_t pte_l1_s_proto; 725 extern pt_entry_t pte_l1_c_proto; 726 extern pt_entry_t pte_l2_s_proto; 727 728 extern void (*pmap_copy_page_func)(paddr_t, paddr_t); 729 extern void (*pmap_zero_page_func)(paddr_t); 730 731 #endif /* !_LOCORE */ 732 733 /*****************************************************************************/ 734 735 #define KERNEL_PID 0 /* The kernel uses ASID 0 */ 736 737 /* 738 * Definitions for MMU domains 739 */ 740 #define PMAP_DOMAINS 15 /* 15 'user' domains (1-15) */ 741 #define PMAP_DOMAIN_KERNEL 0 /* The kernel pmap uses domain #0 */ 742 743 #ifdef ARM_MMU_EXTENDED 744 #define PMAP_DOMAIN_USER 1 /* User pmaps use domain #1 */ 745 #define DOMAIN_DEFAULT ((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | (DOMAIN_CLIENT << (PMAP_DOMAIN_USER*2))) 746 #else 747 #define DOMAIN_DEFAULT ((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2))) 748 #endif 749 750 /* 751 * These macros define the various bit masks in the PTE. 752 * 753 * We use these macros since we use different bits on different processor 754 * models. 755 */ 756 #define L1_S_PROT_U_generic (L1_S_AP(AP_U)) 757 #define L1_S_PROT_W_generic (L1_S_AP(AP_W)) 758 #define L1_S_PROT_RO_generic (0) 759 #define L1_S_PROT_MASK_generic (L1_S_PROT_U|L1_S_PROT_W|L1_S_PROT_RO) 760 761 #define L1_S_PROT_U_xscale (L1_S_AP(AP_U)) 762 #define L1_S_PROT_W_xscale (L1_S_AP(AP_W)) 763 #define L1_S_PROT_RO_xscale (0) 764 #define L1_S_PROT_MASK_xscale (L1_S_PROT_U|L1_S_PROT_W|L1_S_PROT_RO) 765 766 #define L1_S_PROT_U_armv6 (L1_S_AP(AP_R) | L1_S_AP(AP_U)) 767 #define L1_S_PROT_W_armv6 (L1_S_AP(AP_W)) 768 #define L1_S_PROT_RO_armv6 (L1_S_AP(AP_R) | L1_S_AP(AP_RO)) 769 #define L1_S_PROT_MASK_armv6 (L1_S_PROT_U|L1_S_PROT_W|L1_S_PROT_RO) 770 771 #define L1_S_PROT_U_armv7 (L1_S_AP(AP_R) | L1_S_AP(AP_U)) 772 #define L1_S_PROT_W_armv7 (L1_S_AP(AP_W)) 773 #define L1_S_PROT_RO_armv7 (L1_S_AP(AP_R) | L1_S_AP(AP_RO)) 774 #define L1_S_PROT_MASK_armv7 (L1_S_PROT_U|L1_S_PROT_W|L1_S_PROT_RO) 775 776 #define L1_S_CACHE_MASK_generic (L1_S_B|L1_S_C) 777 #define L1_S_CACHE_MASK_xscale (L1_S_B|L1_S_C|L1_S_XS_TEX(TEX_XSCALE_X)) 778 #define L1_S_CACHE_MASK_armv6 (L1_S_B|L1_S_C|L1_S_XS_TEX(TEX_ARMV6_TEX)) 779 #define L1_S_CACHE_MASK_armv6n (L1_S_B|L1_S_C|L1_S_XS_TEX(TEX_ARMV6_TEX)|L1_S_V6_S) 780 #define L1_S_CACHE_MASK_armv7 (L1_S_B|L1_S_C|L1_S_XS_TEX(TEX_ARMV6_TEX)|L1_S_V6_S) 781 782 #define L2_L_PROT_U_generic (L2_AP(AP_U)) 783 #define L2_L_PROT_W_generic (L2_AP(AP_W)) 784 #define L2_L_PROT_RO_generic (0) 785 #define L2_L_PROT_MASK_generic (L2_L_PROT_U|L2_L_PROT_W|L2_L_PROT_RO) 786 787 #define L2_L_PROT_U_xscale (L2_AP(AP_U)) 788 #define L2_L_PROT_W_xscale (L2_AP(AP_W)) 789 #define L2_L_PROT_RO_xscale (0) 790 #define L2_L_PROT_MASK_xscale (L2_L_PROT_U|L2_L_PROT_W|L2_L_PROT_RO) 791 792 #define L2_L_PROT_U_armv6n (L2_AP0(AP_R) | L2_AP0(AP_U)) 793 #define L2_L_PROT_W_armv6n (L2_AP0(AP_W)) 794 #define L2_L_PROT_RO_armv6n (L2_AP0(AP_R) | L2_AP0(AP_RO)) 795 #define L2_L_PROT_MASK_armv6n (L2_L_PROT_U|L2_L_PROT_W|L2_L_PROT_RO) 796 797 #define L2_L_PROT_U_armv7 (L2_AP0(AP_R) | L2_AP0(AP_U)) 798 #define L2_L_PROT_W_armv7 (L2_AP0(AP_W)) 799 #define L2_L_PROT_RO_armv7 (L2_AP0(AP_R) | L2_AP0(AP_RO)) 800 #define L2_L_PROT_MASK_armv7 (L2_L_PROT_U|L2_L_PROT_W|L2_L_PROT_RO) 801 802 #define L2_L_CACHE_MASK_generic (L2_B|L2_C) 803 #define L2_L_CACHE_MASK_xscale (L2_B|L2_C|L2_XS_L_TEX(TEX_XSCALE_X)) 804 #define L2_L_CACHE_MASK_armv6 (L2_B|L2_C|L2_V6_L_TEX(TEX_ARMV6_TEX)) 805 #define L2_L_CACHE_MASK_armv6n (L2_B|L2_C|L2_V6_L_TEX(TEX_ARMV6_TEX)|L2_XS_S) 806 #define L2_L_CACHE_MASK_armv7 (L2_B|L2_C|L2_V6_L_TEX(TEX_ARMV6_TEX)|L2_XS_S) 807 808 #define L2_S_PROT_U_generic (L2_AP(AP_U)) 809 #define L2_S_PROT_W_generic (L2_AP(AP_W)) 810 #define L2_S_PROT_RO_generic (0) 811 #define L2_S_PROT_MASK_generic (L2_S_PROT_U|L2_S_PROT_W|L2_S_PROT_RO) 812 813 #define L2_S_PROT_U_xscale (L2_AP0(AP_U)) 814 #define L2_S_PROT_W_xscale (L2_AP0(AP_W)) 815 #define L2_S_PROT_RO_xscale (0) 816 #define L2_S_PROT_MASK_xscale (L2_S_PROT_U|L2_S_PROT_W|L2_S_PROT_RO) 817 818 #define L2_S_PROT_U_armv6n (L2_AP0(AP_R) | L2_AP0(AP_U)) 819 #define L2_S_PROT_W_armv6n (L2_AP0(AP_W)) 820 #define L2_S_PROT_RO_armv6n (L2_AP0(AP_R) | L2_AP0(AP_RO)) 821 #define L2_S_PROT_MASK_armv6n (L2_S_PROT_U|L2_S_PROT_W|L2_S_PROT_RO) 822 823 #define L2_S_PROT_U_armv7 (L2_AP0(AP_R) | L2_AP0(AP_U)) 824 #define L2_S_PROT_W_armv7 (L2_AP0(AP_W)) 825 #define L2_S_PROT_RO_armv7 (L2_AP0(AP_R) | L2_AP0(AP_RO)) 826 #define L2_S_PROT_MASK_armv7 (L2_S_PROT_U|L2_S_PROT_W|L2_S_PROT_RO) 827 828 #define L2_S_CACHE_MASK_generic (L2_B|L2_C) 829 #define L2_S_CACHE_MASK_xscale (L2_B|L2_C|L2_XS_T_TEX(TEX_XSCALE_X)) 830 #define L2_XS_CACHE_MASK_armv6 (L2_B|L2_C|L2_V6_XS_TEX(TEX_ARMV6_TEX)) 831 #ifdef ARMV6_EXTENDED_SMALL_PAGE 832 #define L2_S_CACHE_MASK_armv6c L2_XS_CACHE_MASK_armv6 833 #else 834 #define L2_S_CACHE_MASK_armv6c L2_S_CACHE_MASK_generic 835 #endif 836 #define L2_S_CACHE_MASK_armv6n (L2_B|L2_C|L2_V6_XS_TEX(TEX_ARMV6_TEX)|L2_XS_S) 837 #define L2_S_CACHE_MASK_armv7 (L2_B|L2_C|L2_V6_XS_TEX(TEX_ARMV6_TEX)|L2_XS_S) 838 839 840 #define L1_S_PROTO_generic (L1_TYPE_S | L1_S_IMP) 841 #define L1_S_PROTO_xscale (L1_TYPE_S) 842 #define L1_S_PROTO_armv6 (L1_TYPE_S) 843 #define L1_S_PROTO_armv7 (L1_TYPE_S) 844 845 #define L1_SS_PROTO_generic 0 846 #define L1_SS_PROTO_xscale 0 847 #define L1_SS_PROTO_armv6 (L1_TYPE_S | L1_S_V6_SS) 848 #define L1_SS_PROTO_armv7 (L1_TYPE_S | L1_S_V6_SS) 849 850 #define L1_C_PROTO_generic (L1_TYPE_C | L1_C_IMP2) 851 #define L1_C_PROTO_xscale (L1_TYPE_C) 852 #define L1_C_PROTO_armv6 (L1_TYPE_C) 853 #define L1_C_PROTO_armv7 (L1_TYPE_C) 854 855 #define L2_L_PROTO (L2_TYPE_L) 856 857 #define L2_S_PROTO_generic (L2_TYPE_S) 858 #define L2_S_PROTO_xscale (L2_TYPE_XS) 859 #ifdef ARMV6_EXTENDED_SMALL_PAGE 860 #define L2_S_PROTO_armv6c (L2_TYPE_XS) /* XP=0, extended small page */ 861 #else 862 #define L2_S_PROTO_armv6c (L2_TYPE_S) /* XP=0, subpage APs */ 863 #endif 864 #ifdef ARM_MMU_EXTENDED 865 #define L2_S_PROTO_armv6n (L2_TYPE_S|L2_XS_XN) 866 #else 867 #define L2_S_PROTO_armv6n (L2_TYPE_S) /* with XP=1 */ 868 #endif 869 #ifdef ARM_MMU_EXTENDED 870 #define L2_S_PROTO_armv7 (L2_TYPE_S|L2_XS_XN) 871 #else 872 #define L2_S_PROTO_armv7 (L2_TYPE_S) 873 #endif 874 875 /* 876 * User-visible names for the ones that vary with MMU class. 877 */ 878 879 #if ARM_NMMUS > 1 880 /* More than one MMU class configured; use variables. */ 881 #define L1_S_PROT_U pte_l1_s_prot_u 882 #define L1_S_PROT_W pte_l1_s_prot_w 883 #define L1_S_PROT_RO pte_l1_s_prot_ro 884 #define L1_S_PROT_MASK pte_l1_s_prot_mask 885 886 #define L2_S_PROT_U pte_l2_s_prot_u 887 #define L2_S_PROT_W pte_l2_s_prot_w 888 #define L2_S_PROT_RO pte_l2_s_prot_ro 889 #define L2_S_PROT_MASK pte_l2_s_prot_mask 890 891 #define L2_L_PROT_U pte_l2_l_prot_u 892 #define L2_L_PROT_W pte_l2_l_prot_w 893 #define L2_L_PROT_RO pte_l2_l_prot_ro 894 #define L2_L_PROT_MASK pte_l2_l_prot_mask 895 896 #define L1_S_CACHE_MASK pte_l1_s_cache_mask 897 #define L2_L_CACHE_MASK pte_l2_l_cache_mask 898 #define L2_S_CACHE_MASK pte_l2_s_cache_mask 899 900 #define L1_SS_PROTO pte_l1_ss_proto 901 #define L1_S_PROTO pte_l1_s_proto 902 #define L1_C_PROTO pte_l1_c_proto 903 #define L2_S_PROTO pte_l2_s_proto 904 905 #define pmap_copy_page(s, d) (*pmap_copy_page_func)((s), (d)) 906 #define pmap_zero_page(d) (*pmap_zero_page_func)((d)) 907 #elif (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 908 #define L1_S_PROT_U L1_S_PROT_U_generic 909 #define L1_S_PROT_W L1_S_PROT_W_generic 910 #define L1_S_PROT_RO L1_S_PROT_RO_generic 911 #define L1_S_PROT_MASK L1_S_PROT_MASK_generic 912 913 #define L2_S_PROT_U L2_S_PROT_U_generic 914 #define L2_S_PROT_W L2_S_PROT_W_generic 915 #define L2_S_PROT_RO L2_S_PROT_RO_generic 916 #define L2_S_PROT_MASK L2_S_PROT_MASK_generic 917 918 #define L2_L_PROT_U L2_L_PROT_U_generic 919 #define L2_L_PROT_W L2_L_PROT_W_generic 920 #define L2_L_PROT_RO L2_L_PROT_RO_generic 921 #define L2_L_PROT_MASK L2_L_PROT_MASK_generic 922 923 #define L1_S_CACHE_MASK L1_S_CACHE_MASK_generic 924 #define L2_L_CACHE_MASK L2_L_CACHE_MASK_generic 925 #define L2_S_CACHE_MASK L2_S_CACHE_MASK_generic 926 927 #define L1_SS_PROTO L1_SS_PROTO_generic 928 #define L1_S_PROTO L1_S_PROTO_generic 929 #define L1_C_PROTO L1_C_PROTO_generic 930 #define L2_S_PROTO L2_S_PROTO_generic 931 932 #define pmap_copy_page(s, d) pmap_copy_page_generic((s), (d)) 933 #define pmap_zero_page(d) pmap_zero_page_generic((d)) 934 #elif ARM_MMU_V6N != 0 935 #define L1_S_PROT_U L1_S_PROT_U_armv6 936 #define L1_S_PROT_W L1_S_PROT_W_armv6 937 #define L1_S_PROT_RO L1_S_PROT_RO_armv6 938 #define L1_S_PROT_MASK L1_S_PROT_MASK_armv6 939 940 #define L2_S_PROT_U L2_S_PROT_U_armv6n 941 #define L2_S_PROT_W L2_S_PROT_W_armv6n 942 #define L2_S_PROT_RO L2_S_PROT_RO_armv6n 943 #define L2_S_PROT_MASK L2_S_PROT_MASK_armv6n 944 945 #define L2_L_PROT_U L2_L_PROT_U_armv6n 946 #define L2_L_PROT_W L2_L_PROT_W_armv6n 947 #define L2_L_PROT_RO L2_L_PROT_RO_armv6n 948 #define L2_L_PROT_MASK L2_L_PROT_MASK_armv6n 949 950 #define L1_S_CACHE_MASK L1_S_CACHE_MASK_armv6n 951 #define L2_L_CACHE_MASK L2_L_CACHE_MASK_armv6n 952 #define L2_S_CACHE_MASK L2_S_CACHE_MASK_armv6n 953 954 /* 955 * These prototypes make writeable mappings, while the other MMU types 956 * make read-only mappings. 957 */ 958 #define L1_SS_PROTO L1_SS_PROTO_armv6 959 #define L1_S_PROTO L1_S_PROTO_armv6 960 #define L1_C_PROTO L1_C_PROTO_armv6 961 #define L2_S_PROTO L2_S_PROTO_armv6n 962 963 #define pmap_copy_page(s, d) pmap_copy_page_generic((s), (d)) 964 #define pmap_zero_page(d) pmap_zero_page_generic((d)) 965 #elif ARM_MMU_V6C != 0 966 #define L1_S_PROT_U L1_S_PROT_U_generic 967 #define L1_S_PROT_W L1_S_PROT_W_generic 968 #define L1_S_PROT_RO L1_S_PROT_RO_generic 969 #define L1_S_PROT_MASK L1_S_PROT_MASK_generic 970 971 #define L2_S_PROT_U L2_S_PROT_U_generic 972 #define L2_S_PROT_W L2_S_PROT_W_generic 973 #define L2_S_PROT_RO L2_S_PROT_RO_generic 974 #define L2_S_PROT_MASK L2_S_PROT_MASK_generic 975 976 #define L2_L_PROT_U L2_L_PROT_U_generic 977 #define L2_L_PROT_W L2_L_PROT_W_generic 978 #define L2_L_PROT_RO L2_L_PROT_RO_generic 979 #define L2_L_PROT_MASK L2_L_PROT_MASK_generic 980 981 #define L1_S_CACHE_MASK L1_S_CACHE_MASK_generic 982 #define L2_L_CACHE_MASK L2_L_CACHE_MASK_generic 983 #define L2_S_CACHE_MASK L2_S_CACHE_MASK_generic 984 985 #define L1_SS_PROTO L1_SS_PROTO_armv6 986 #define L1_S_PROTO L1_S_PROTO_generic 987 #define L1_C_PROTO L1_C_PROTO_generic 988 #define L2_S_PROTO L2_S_PROTO_generic 989 990 #define pmap_copy_page(s, d) pmap_copy_page_generic((s), (d)) 991 #define pmap_zero_page(d) pmap_zero_page_generic((d)) 992 #elif ARM_MMU_XSCALE == 1 993 #define L1_S_PROT_U L1_S_PROT_U_generic 994 #define L1_S_PROT_W L1_S_PROT_W_generic 995 #define L1_S_PROT_RO L1_S_PROT_RO_generic 996 #define L1_S_PROT_MASK L1_S_PROT_MASK_generic 997 998 #define L2_S_PROT_U L2_S_PROT_U_xscale 999 #define L2_S_PROT_W L2_S_PROT_W_xscale 1000 #define L2_S_PROT_RO L2_S_PROT_RO_xscale 1001 #define L2_S_PROT_MASK L2_S_PROT_MASK_xscale 1002 1003 #define L2_L_PROT_U L2_L_PROT_U_generic 1004 #define L2_L_PROT_W L2_L_PROT_W_generic 1005 #define L2_L_PROT_RO L2_L_PROT_RO_generic 1006 #define L2_L_PROT_MASK L2_L_PROT_MASK_generic 1007 1008 #define L1_S_CACHE_MASK L1_S_CACHE_MASK_xscale 1009 #define L2_L_CACHE_MASK L2_L_CACHE_MASK_xscale 1010 #define L2_S_CACHE_MASK L2_S_CACHE_MASK_xscale 1011 1012 #define L1_SS_PROTO L1_SS_PROTO_xscale 1013 #define L1_S_PROTO L1_S_PROTO_xscale 1014 #define L1_C_PROTO L1_C_PROTO_xscale 1015 #define L2_S_PROTO L2_S_PROTO_xscale 1016 1017 #define pmap_copy_page(s, d) pmap_copy_page_xscale((s), (d)) 1018 #define pmap_zero_page(d) pmap_zero_page_xscale((d)) 1019 #elif ARM_MMU_V7 == 1 1020 #define L1_S_PROT_U L1_S_PROT_U_armv7 1021 #define L1_S_PROT_W L1_S_PROT_W_armv7 1022 #define L1_S_PROT_RO L1_S_PROT_RO_armv7 1023 #define L1_S_PROT_MASK L1_S_PROT_MASK_armv7 1024 1025 #define L2_S_PROT_U L2_S_PROT_U_armv7 1026 #define L2_S_PROT_W L2_S_PROT_W_armv7 1027 #define L2_S_PROT_RO L2_S_PROT_RO_armv7 1028 #define L2_S_PROT_MASK L2_S_PROT_MASK_armv7 1029 1030 #define L2_L_PROT_U L2_L_PROT_U_armv7 1031 #define L2_L_PROT_W L2_L_PROT_W_armv7 1032 #define L2_L_PROT_RO L2_L_PROT_RO_armv7 1033 #define L2_L_PROT_MASK L2_L_PROT_MASK_armv7 1034 1035 #define L1_S_CACHE_MASK L1_S_CACHE_MASK_armv7 1036 #define L2_L_CACHE_MASK L2_L_CACHE_MASK_armv7 1037 #define L2_S_CACHE_MASK L2_S_CACHE_MASK_armv7 1038 1039 /* 1040 * These prototypes make writeable mappings, while the other MMU types 1041 * make read-only mappings. 1042 */ 1043 #define L1_SS_PROTO L1_SS_PROTO_armv7 1044 #define L1_S_PROTO L1_S_PROTO_armv7 1045 #define L1_C_PROTO L1_C_PROTO_armv7 1046 #define L2_S_PROTO L2_S_PROTO_armv7 1047 1048 #define pmap_copy_page(s, d) pmap_copy_page_generic((s), (d)) 1049 #define pmap_zero_page(d) pmap_zero_page_generic((d)) 1050 #endif /* ARM_NMMUS > 1 */ 1051 1052 /* 1053 * Macros to set and query the write permission on page descriptors. 1054 */ 1055 #define l1pte_set_writable(pte) (((pte) & ~L1_S_PROT_RO) | L1_S_PROT_W) 1056 #define l1pte_set_readonly(pte) (((pte) & ~L1_S_PROT_W) | L1_S_PROT_RO) 1057 1058 #define l2pte_set_writable(pte) (((pte) & ~L2_S_PROT_RO) | L2_S_PROT_W) 1059 #define l2pte_set_readonly(pte) (((pte) & ~L2_S_PROT_W) | L2_S_PROT_RO) 1060 1061 #define l2pte_writable_p(pte) (((pte) & L2_S_PROT_W) == L2_S_PROT_W && \ 1062 (L2_S_PROT_RO == 0 || \ 1063 ((pte) & L2_S_PROT_RO) != L2_S_PROT_RO)) 1064 1065 /* 1066 * These macros return various bits based on kernel/user and protection. 1067 * Note that the compiler will usually fold these at compile time. 1068 */ 1069 1070 #define L1_S_PROT(ku, pr) ( \ 1071 (((ku) == PTE_USER) ? \ 1072 L1_S_PROT_U | (((pr) & VM_PROT_WRITE) ? L1_S_PROT_W : 0) \ 1073 : \ 1074 (((L1_S_PROT_RO && \ 1075 ((pr) & (VM_PROT_READ | VM_PROT_WRITE)) == VM_PROT_READ) ? \ 1076 L1_S_PROT_RO : L1_S_PROT_W))) \ 1077 ) 1078 1079 #define L2_L_PROT(ku, pr) ( \ 1080 (((ku) == PTE_USER) ? \ 1081 L2_L_PROT_U | (((pr) & VM_PROT_WRITE) ? L2_L_PROT_W : 0) \ 1082 : \ 1083 (((L2_L_PROT_RO && \ 1084 ((pr) & (VM_PROT_READ | VM_PROT_WRITE)) == VM_PROT_READ) ? \ 1085 L2_L_PROT_RO : L2_L_PROT_W))) \ 1086 ) 1087 1088 #define L2_S_PROT(ku, pr) ( \ 1089 (((ku) == PTE_USER) ? \ 1090 L2_S_PROT_U | (((pr) & VM_PROT_WRITE) ? L2_S_PROT_W : 0) \ 1091 : \ 1092 (((L2_S_PROT_RO && \ 1093 ((pr) & (VM_PROT_READ | VM_PROT_WRITE)) == VM_PROT_READ) ? \ 1094 L2_S_PROT_RO : L2_S_PROT_W))) \ 1095 ) 1096 1097 /* 1098 * Macros to test if a mapping is mappable with an L1 SuperSection, 1099 * L1 Section, or an L2 Large Page mapping. 1100 */ 1101 #define L1_SS_MAPPABLE_P(va, pa, size) \ 1102 ((((va) | (pa)) & L1_SS_OFFSET) == 0 && (size) >= L1_SS_SIZE) 1103 1104 #define L1_S_MAPPABLE_P(va, pa, size) \ 1105 ((((va) | (pa)) & L1_S_OFFSET) == 0 && (size) >= L1_S_SIZE) 1106 1107 #define L2_L_MAPPABLE_P(va, pa, size) \ 1108 ((((va) | (pa)) & L2_L_OFFSET) == 0 && (size) >= L2_L_SIZE) 1109 1110 #define PMAP_MAPSIZE1 L2_L_SIZE 1111 #define PMAP_MAPSIZE2 L1_S_SIZE 1112 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 1113 #define PMAP_MAPSIZE3 L1_SS_SIZE 1114 #endif 1115 1116 #ifndef _LOCORE 1117 /* 1118 * Hooks for the pool allocator. 1119 */ 1120 #define POOL_VTOPHYS(va) vtophys((vaddr_t) (va)) 1121 extern paddr_t physical_start, physical_end; 1122 #ifdef PMAP_NEED_ALLOC_POOLPAGE 1123 struct vm_page *arm_pmap_alloc_poolpage(int); 1124 #define PMAP_ALLOC_POOLPAGE arm_pmap_alloc_poolpage 1125 #endif 1126 #if defined(PMAP_NEED_ALLOC_POOLPAGE) || defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) 1127 vaddr_t pmap_map_poolpage(paddr_t); 1128 paddr_t pmap_unmap_poolpage(vaddr_t); 1129 #define PMAP_MAP_POOLPAGE(pa) pmap_map_poolpage(pa) 1130 #define PMAP_UNMAP_POOLPAGE(va) pmap_unmap_poolpage(va) 1131 #endif 1132 1133 #define __HAVE_PMAP_PV_TRACK 1 1134 1135 void pmap_pv_protect(paddr_t, vm_prot_t); 1136 1137 struct pmap_page { 1138 SLIST_HEAD(,pv_entry) pvh_list; /* pv_entry list */ 1139 int pvh_attrs; /* page attributes */ 1140 u_int uro_mappings; 1141 u_int urw_mappings; 1142 union { 1143 u_short s_mappings[2]; /* Assume kernel count <= 65535 */ 1144 u_int i_mappings; 1145 } k_u; 1146 }; 1147 1148 /* 1149 * pmap-specific data store in the vm_page structure. 1150 */ 1151 #define __HAVE_VM_PAGE_MD 1152 struct vm_page_md { 1153 struct pmap_page pp; 1154 #define pvh_list pp.pvh_list 1155 #define pvh_attrs pp.pvh_attrs 1156 #define uro_mappings pp.uro_mappings 1157 #define urw_mappings pp.urw_mappings 1158 #define kro_mappings pp.k_u.s_mappings[0] 1159 #define krw_mappings pp.k_u.s_mappings[1] 1160 #define k_mappings pp.k_u.i_mappings 1161 }; 1162 1163 #define PMAP_PAGE_TO_MD(ppage) container_of((ppage), struct vm_page_md, pp) 1164 1165 /* 1166 * Set the default color of each page. 1167 */ 1168 #if ARM_MMU_V6 > 0 1169 #define VM_MDPAGE_PVH_ATTRS_INIT(pg) \ 1170 (pg)->mdpage.pvh_attrs = VM_PAGE_TO_PHYS(pg) & arm_cache_prefer_mask 1171 #else 1172 #define VM_MDPAGE_PVH_ATTRS_INIT(pg) \ 1173 (pg)->mdpage.pvh_attrs = 0 1174 #endif 1175 1176 #define VM_MDPAGE_INIT(pg) \ 1177 do { \ 1178 SLIST_INIT(&(pg)->mdpage.pvh_list); \ 1179 VM_MDPAGE_PVH_ATTRS_INIT(pg); \ 1180 (pg)->mdpage.uro_mappings = 0; \ 1181 (pg)->mdpage.urw_mappings = 0; \ 1182 (pg)->mdpage.k_mappings = 0; \ 1183 } while (/*CONSTCOND*/0) 1184 1185 #ifndef __BSD_PTENTRY_T__ 1186 #define __BSD_PTENTRY_T__ 1187 typedef uint32_t pt_entry_t; 1188 #define PRIxPTE PRIx32 1189 #endif 1190 1191 #endif /* !_LOCORE */ 1192 1193 #endif /* _KERNEL */ 1194 1195 #endif /* _ARM32_PMAP_H_ */ 1196
Indexes created Fri Oct 31 11:10:07 GMT 2025