pmap.h revision 1.49
1 /* $NetBSD: pmap.h,v 1.49 2002/04/09 22:37:01 thorpej Exp $ */ 2 3 /* 4 * Copyright (c 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Copyright (c) 1994,1995 Mark Brinicombe. 40 * All rights reserved. 41 * 42 * Redistribution and use in source and binary forms, with or without 43 * modification, are permitted provided that the following conditions 44 * are met: 45 * 1. Redistributions of source code must retain the above copyright 46 * notice, this list of conditions and the following disclaimer. 47 * 2. Redistributions in binary form must reproduce the above copyright 48 * notice, this list of conditions and the following disclaimer in the 49 * documentation and/or other materials provided with the distribution. 50 * 3. All advertising materials mentioning features or use of this software 51 * must display the following acknowledgement: 52 * This product includes software developed by Mark Brinicombe 53 * 4. The name of the author may not be used to endorse or promote products 54 * derived from this software without specific prior written permission. 55 * 56 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 57 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 58 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 59 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 60 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 61 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 62 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 63 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 64 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 65 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 #ifndef _ARM32_PMAP_H_ 69 #define _ARM32_PMAP_H_ 70 71 #ifdef _KERNEL 72 73 #include <arm/cpufunc.h> 74 #include <arm/arm32/pte.h> 75 #include <uvm/uvm_object.h> 76 77 /* 78 * a pmap describes a processes' 4GB virtual address space. this 79 * virtual address space can be broken up into 4096 1MB regions which 80 * are described by L1 PTEs in the L1 table. 81 * 82 * There is a line drawn at KERNEL_BASE. Everything below that line 83 * changes when the VM context is switched. Everything above that line 84 * is the same no matter which VM context is running. This is achieved 85 * by making the L1 PTEs for those slots above KERNEL_BASE reference 86 * kernel L2 tables. 87 * 88 * The L2 tables are mapped linearly starting at PTE_BASE. PTE_BASE 89 * is below KERNEL_BASE, which means that the current process's PTEs 90 * are always available starting at PTE_BASE. Another region of KVA 91 * above KERNEL_BASE, APTE_BASE, is reserved for mapping in the PTEs 92 * of another process, should we need to manipulate them. 93 * 94 * The basic layout of the virtual address space thus looks like this: 95 * 96 * 0xffffffff 97 * . 98 * . 99 * . 100 * KERNEL_BASE 101 * -------------------- 102 * PTE_BASE 103 * . 104 * . 105 * . 106 * 0x00000000 107 */ 108 109 /* 110 * The pmap structure itself. 111 */ 112 struct pmap { 113 struct uvm_object pm_obj; /* uvm_object */ 114 #define pm_lock pm_obj.vmobjlock 115 LIST_ENTRY(pmap) pm_list; /* list (lck by pm_list lock) */ 116 pd_entry_t *pm_pdir; /* KVA of page directory */ 117 struct l1pt *pm_l1pt; /* L1 table metadata */ 118 paddr_t pm_pptpt; /* PA of pt's page table */ 119 vaddr_t pm_vptpt; /* VA of pt's page table */ 120 struct pmap_statistics pm_stats; /* pmap statistics */ 121 struct vm_page *pm_ptphint; /* recently used PT */ 122 }; 123 124 typedef struct pmap *pmap_t; 125 126 /* 127 * Physical / virtual address structure. In a number of places (particularly 128 * during bootstrapping) we need to keep track of the physical and virtual 129 * addresses of various pages 130 */ 131 typedef struct pv_addr { 132 SLIST_ENTRY(pv_addr) pv_list; 133 paddr_t pv_pa; 134 vaddr_t pv_va; 135 } pv_addr_t; 136 137 /* 138 * Determine various modes for PTEs (user vs. kernel, cacheable 139 * vs. non-cacheable). 140 */ 141 #define PTE_KERNEL 0 142 #define PTE_USER 1 143 #define PTE_NOCACHE 0 144 #define PTE_CACHE 1 145 146 /* 147 * Flags that indicate attributes of pages or mappings of pages. 148 * 149 * The PVF_MOD and PVF_REF flags are stored in the mdpage for each 150 * page. PVF_WIRED, PVF_WRITE, and PVF_NC are kept in individual 151 * pv_entry's for each page. They live in the same "namespace" so 152 * that we can clear multiple attributes at a time. 153 * 154 * Note the "non-cacheable" flag generally means the page has 155 * multiple mappings in a given address space. 156 */ 157 #define PVF_MOD 0x01 /* page is modified */ 158 #define PVF_REF 0x02 /* page is referenced */ 159 #define PVF_WIRED 0x04 /* mapping is wired */ 160 #define PVF_WRITE 0x08 /* mapping is writable */ 161 #define PVF_NC 0x10 /* mapping is non-cacheable */ 162 163 /* 164 * Commonly referenced structures 165 */ 166 extern struct pmap kernel_pmap_store; 167 extern int pmap_debug_level; /* Only exists if PMAP_DEBUG */ 168 169 /* 170 * Macros that we need to export 171 */ 172 #define pmap_kernel() (&kernel_pmap_store) 173 #define pmap_resident_count(pmap) ((pmap)->pm_stats.resident_count) 174 #define pmap_wired_count(pmap) ((pmap)->pm_stats.wired_count) 175 176 #define pmap_is_modified(pg) \ 177 (((pg)->mdpage.pvh_attrs & PVF_MOD) != 0) 178 #define pmap_is_referenced(pg) \ 179 (((pg)->mdpage.pvh_attrs & PVF_REF) != 0) 180 181 #define pmap_copy(dp, sp, da, l, sa) /* nothing */ 182 183 #define pmap_phys_address(ppn) (arm_ptob((ppn))) 184 185 /* 186 * Functions that we need to export 187 */ 188 vaddr_t pmap_map(vaddr_t, vaddr_t, vaddr_t, int); 189 void pmap_procwr(struct proc *, vaddr_t, int); 190 191 #define PMAP_NEED_PROCWR 192 #define PMAP_GROWKERNEL /* turn on pmap_growkernel interface */ 193 194 /* Functions we use internally. */ 195 void pmap_bootstrap(pd_entry_t *, pv_addr_t); 196 void pmap_debug(int); 197 int pmap_handled_emulation(struct pmap *, vaddr_t); 198 int pmap_modified_emulation(struct pmap *, vaddr_t); 199 void pmap_postinit(void); 200 201 void vector_page_setprot(int); 202 203 /* Bootstrapping routines. */ 204 void pmap_map_section(vaddr_t, vaddr_t, paddr_t, int, int); 205 void pmap_map_entry(vaddr_t, vaddr_t, paddr_t, int, int); 206 vsize_t pmap_map_chunk(vaddr_t, vaddr_t, paddr_t, vsize_t, int, int); 207 void pmap_link_l2pt(vaddr_t, vaddr_t, pv_addr_t *); 208 209 /* 210 * Special page zero routine for use by the idle loop (no cache cleans). 211 */ 212 boolean_t pmap_pageidlezero __P((paddr_t)); 213 #define PMAP_PAGEIDLEZERO(pa) pmap_pageidlezero((pa)) 214 215 /* 216 * The current top of kernel VM 217 */ 218 extern vaddr_t pmap_curmaxkvaddr; 219 220 /* 221 * Useful macros and constants 222 */ 223 224 /* Virtual address to page table entry */ 225 #define vtopte(va) \ 226 (((pt_entry_t *)PTE_BASE) + arm_btop((vaddr_t) (va))) 227 228 /* Virtual address to physical address */ 229 #define vtophys(va) \ 230 ((*vtopte(va) & L2_S_FRAME) | ((vaddr_t) (va) & L2_S_OFFSET)) 231 232 #define l1pte_valid(pde) ((pde) != 0) 233 #define l1pte_section_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_S) 234 #define l1pte_page_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_C) 235 #define l1pte_fpage_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_F) 236 237 #define l2pte_valid(pte) ((pte) != 0) 238 #define l2pte_pa(pte) ((pte) & L2_S_FRAME) 239 240 /* L1 and L2 page table macros */ 241 #define pmap_pdei(v) ((v & L1_S_FRAME) >> L1_S_SHIFT) 242 #define pmap_pde(m, v) (&((m)->pm_pdir[pmap_pdei(v)])) 243 244 #define pmap_pde_v(pde) l1pte_valid(*(pde)) 245 #define pmap_pde_section(pde) l1pte_section_p(*(pde)) 246 #define pmap_pde_page(pde) l1pte_page_p(*(pde)) 247 #define pmap_pde_fpage(pde) l1pte_fpage_p(*(pde)) 248 249 #define pmap_pte_v(pte) l2pte_valid(*(pte)) 250 #define pmap_pte_pa(pte) l2pte_pa(*(pte)) 251 252 253 /* Size of the kernel part of the L1 page table */ 254 #define KERNEL_PD_SIZE \ 255 (L1_TABLE_SIZE - (KERNEL_BASE >> L1_S_SHIFT) * sizeof(pd_entry_t)) 256 257 /************************* ARM MMU configuration *****************************/ 258 259 /* 260 * We define several classes of ARM MMU, here: 261 * 262 * ARM_MMU_GENERIC Generic ARM MMU, compatible with ARM6. 263 * 264 * ARM_MMU_XSCALE XScale MMU. Compatible with generic ARM 265 * MMU, but also has several extensions which 266 * require different PTE layout to use. 267 */ 268 269 #if defined(_LKM) || defined(CPU_ARM6) || defined(CPU_ARM7) || \ 270 defined(CPU_ARM7TDMI) || defined(CPU_ARM8) || defined(CPU_ARM9) || \ 271 defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) 272 #define ARM_MMU_GENERIC 1 273 274 void pmap_pte_init_generic(void); 275 #if defined(CPU_ARM9) 276 void pmap_pte_init_arm9(void); 277 #endif /* CPU_ARM9 */ 278 #else 279 #define ARM_MMU_GENERIC 0 280 #endif 281 282 #if defined(_LKM) || defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) 283 #define ARM_MMU_XSCALE 1 284 285 void pmap_pte_init_xscale(void); 286 #if defined(CPU_XSCALE_80200) 287 void pmap_pte_init_i80200(void); 288 #endif /* CPU_XSCALE_80200 */ 289 #else 290 #define ARM_MMU_XSCALE 0 291 #endif 292 293 #define ARM_NMMUS (ARM_MMU_GENERIC + ARM_MMU_XSCALE) 294 #if ARM_NMMUS == 0 295 #error ARM_NMMUS is 0 296 #endif 297 298 extern pt_entry_t pte_l1_s_cache_mode; 299 extern pt_entry_t pte_l1_s_cache_mask; 300 301 extern pt_entry_t pte_l2_l_cache_mode; 302 extern pt_entry_t pte_l2_l_cache_mask; 303 304 extern pt_entry_t pte_l2_s_cache_mode; 305 extern pt_entry_t pte_l2_s_cache_mask; 306 307 extern pt_entry_t pte_l2_s_prot_u; 308 extern pt_entry_t pte_l2_s_prot_w; 309 extern pt_entry_t pte_l2_s_prot_mask; 310 311 extern pt_entry_t pte_l1_s_proto; 312 extern pt_entry_t pte_l1_c_proto; 313 extern pt_entry_t pte_l2_s_proto; 314 315 /*****************************************************************************/ 316 317 /* 318 * tell MI code that the cache is virtually-indexed *and* virtually-tagged. 319 */ 320 #define PMAP_CACHE_VIVT 321 322 /* 323 * These macros define the various bit masks in the PTE. 324 * 325 * We use these macros since we use different bits on different processor 326 * models. 327 */ 328 #define L1_S_PROT_U (L1_S_AP(AP_U)) 329 #define L1_S_PROT_W (L1_S_AP(AP_W)) 330 #define L1_S_PROT_MASK (L1_S_PROT_U|L1_S_PROT_W) 331 332 #define L1_S_CACHE_MASK_generic (L1_S_B|L1_S_C) 333 #define L1_S_CACHE_MASK_xscale (L1_S_B|L1_S_C|L1_S_XSCALE_TEX(TEX_XSCALE_X)) 334 335 #define L2_L_PROT_U (L2_AP(AP_U)) 336 #define L2_L_PROT_W (L2_AP(AP_W)) 337 #define L2_L_PROT_MASK (L2_L_PROT_U|L2_L_PROT_W) 338 339 #define L2_L_CACHE_MASK_generic (L2_B|L2_C) 340 #define L2_L_CACHE_MASK_xscale (L2_B|L2_C|L2_XSCALE_L_TEX(TEX_XSCALE_X)) 341 342 #define L2_S_PROT_U_generic (L2_AP(AP_U)) 343 #define L2_S_PROT_W_generic (L2_AP(AP_W)) 344 #define L2_S_PROT_MASK_generic (L2_S_PROT_U|L2_S_PROT_W) 345 346 #define L2_S_PROT_U_xscale (L2_AP0(AP_U)) 347 #define L2_S_PROT_W_xscale (L2_AP0(AP_W)) 348 #define L2_S_PROT_MASK_xscale (L2_S_PROT_U|L2_S_PROT_W) 349 350 #define L2_S_CACHE_MASK_generic (L2_B|L2_C) 351 #define L2_S_CACHE_MASK_xscale (L2_B|L2_C|L2_XSCALE_T_TEX(TEX_XSCALE_X)) 352 353 #define L1_S_PROTO_generic (L1_TYPE_S | L1_S_IMP) 354 #define L1_S_PROTO_xscale (L1_TYPE_S) 355 356 #define L1_C_PROTO_generic (L1_TYPE_C | L1_C_IMP2) 357 #define L1_C_PROTO_xscale (L1_TYPE_C) 358 359 #define L2_L_PROTO (L2_TYPE_L) 360 361 #define L2_S_PROTO_generic (L2_TYPE_S) 362 #define L2_S_PROTO_xscale (L2_TYPE_XSCALE_XS) 363 364 /* 365 * User-visible names for the ones that vary with MMU class. 366 */ 367 368 #if ARM_NMMUS > 1 369 /* More than one MMU class configured; use variables. */ 370 #define L2_S_PROT_U pte_l2_s_prot_u 371 #define L2_S_PROT_W pte_l2_s_prot_w 372 #define L2_S_PROT_MASK pte_l2_s_prot_mask 373 374 #define L1_S_CACHE_MASK pte_l1_s_cache_mask 375 #define L2_L_CACHE_MASK pte_l2_l_cache_mask 376 #define L2_S_CACHE_MASK pte_l2_s_cache_mask 377 378 #define L1_S_PROTO pte_l1_s_proto 379 #define L1_C_PROTO pte_l1_c_proto 380 #define L2_S_PROTO pte_l2_s_proto 381 #elif ARM_MMU_GENERIC == 1 382 #define L2_S_PROT_U L2_S_PROT_U_generic 383 #define L2_S_PROT_W L2_S_PROT_W_generic 384 #define L2_S_PROT_MASK L2_S_PROT_MASK_generic 385 386 #define L1_S_CACHE_MASK L1_S_CACHE_MASK_generic 387 #define L2_L_CACHE_MASK L2_L_CACHE_MASK_generic 388 #define L2_S_CACHE_MASK L2_S_CACHE_MASK_generic 389 390 #define L1_S_PROTO L1_S_PROTO_generic 391 #define L1_C_PROTO L1_C_PROTO_generic 392 #define L2_S_PROTO L2_S_PROTO_generic 393 #elif ARM_MMU_XSCALE == 1 394 #define L2_S_PROT_U L2_S_PROT_U_xscale 395 #define L2_S_PROT_W L2_S_PROT_W_xscale 396 #define L2_S_PROT_MASK L2_S_PROT_MASK_xscale 397 398 #define L1_S_CACHE_MASK L1_S_CACHE_MASK_xscale 399 #define L2_L_CACHE_MASK L2_L_CACHE_MASK_xscale 400 #define L2_S_CACHE_MASK L2_S_CACHE_MASK_xscale 401 402 #define L1_S_PROTO L1_S_PROTO_xscale 403 #define L1_C_PROTO L1_C_PROTO_xscale 404 #define L2_S_PROTO L2_S_PROTO_xscale 405 #endif /* ARM_NMMUS > 1 */ 406 407 /* 408 * These macros return various bits based on kernel/user and protection. 409 * Note that the compiler will usually fold these at compile time. 410 */ 411 #define L1_S_PROT(ku, pr) ((((ku) == PTE_USER) ? L1_S_PROT_U : 0) | \ 412 (((pr) & VM_PROT_WRITE) ? L1_S_PROT_W : 0)) 413 414 #define L2_L_PROT(ku, pr) ((((ku) == PTE_USER) ? L2_L_PROT_U : 0) | \ 415 (((pr) & VM_PROT_WRITE) ? L2_L_PROT_W : 0)) 416 417 #define L2_S_PROT(ku, pr) ((((ku) == PTE_USER) ? L2_S_PROT_U : 0) | \ 418 (((pr) & VM_PROT_WRITE) ? L2_S_PROT_W : 0)) 419 420 #endif /* _KERNEL */ 421 422 #endif /* _ARM32_PMAP_H_ */ 423
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