pmap.h revision 1.68
1 /* $NetBSD: pmap.h,v 1.68 2003/04/18 23:45:50 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2002, 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe & Steve C. Woodford for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Copyright (c) 1994,1995 Mark Brinicombe. 40 * All rights reserved. 41 * 42 * Redistribution and use in source and binary forms, with or without 43 * modification, are permitted provided that the following conditions 44 * are met: 45 * 1. Redistributions of source code must retain the above copyright 46 * notice, this list of conditions and the following disclaimer. 47 * 2. Redistributions in binary form must reproduce the above copyright 48 * notice, this list of conditions and the following disclaimer in the 49 * documentation and/or other materials provided with the distribution. 50 * 3. All advertising materials mentioning features or use of this software 51 * must display the following acknowledgement: 52 * This product includes software developed by Mark Brinicombe 53 * 4. The name of the author may not be used to endorse or promote products 54 * derived from this software without specific prior written permission. 55 * 56 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 57 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 58 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 59 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 60 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 61 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 62 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 63 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 64 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 65 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 #ifndef _ARM32_PMAP_H_ 69 #define _ARM32_PMAP_H_ 70 71 #ifdef _KERNEL 72 73 #include <arm/cpuconf.h> 74 #include <arm/cpufunc.h> 75 #include <arm/arm32/pte.h> 76 #include <uvm/uvm_object.h> 77 78 /* 79 * a pmap describes a processes' 4GB virtual address space. this 80 * virtual address space can be broken up into 4096 1MB regions which 81 * are described by L1 PTEs in the L1 table. 82 * 83 * There is a line drawn at KERNEL_BASE. Everything below that line 84 * changes when the VM context is switched. Everything above that line 85 * is the same no matter which VM context is running. This is achieved 86 * by making the L1 PTEs for those slots above KERNEL_BASE reference 87 * kernel L2 tables. 88 * 89 *#ifndef ARM32_PMAP_NEW 90 * The L2 tables are mapped linearly starting at PTE_BASE. PTE_BASE 91 * is below KERNEL_BASE, which means that the current process's PTEs 92 * are always available starting at PTE_BASE. Another region of KVA 93 * above KERNEL_BASE, APTE_BASE, is reserved for mapping in the PTEs 94 * of another process, should we need to manipulate them. 95 *#endif 96 * 97 * The basic layout of the virtual address space thus looks like this: 98 * 99 * 0xffffffff 100 * . 101 * . 102 * . 103 * KERNEL_BASE 104 * -------------------- 105 *#ifndef ARM32_PMAP_NEW 106 * PTE_BASE 107 *#endif 108 * . 109 * . 110 * . 111 * 0x00000000 112 */ 113 114 #ifdef ARM32_PMAP_NEW 115 /* 116 * The number of L2 descriptor tables which can be tracked by an l2_dtable. 117 * A bucket size of 16 provides for 16MB of contiguous virtual address 118 * space per l2_dtable. Most processes will, therefore, require only two or 119 * three of these to map their whole working set. 120 */ 121 #define L2_BUCKET_LOG2 4 122 #define L2_BUCKET_SIZE (1 << L2_BUCKET_LOG2) 123 124 /* 125 * Given the above "L2-descriptors-per-l2_dtable" constant, the number 126 * of l2_dtable structures required to track all possible page descriptors 127 * mappable by an L1 translation table is given by the following constants: 128 */ 129 #define L2_LOG2 ((32 - L1_S_SHIFT) - L2_BUCKET_LOG2) 130 #define L2_SIZE (1 << L2_LOG2) 131 132 struct l1_ttable; 133 struct l2_dtable; 134 135 /* 136 * Track cache/tlb occupancy using the following structure 137 */ 138 union pmap_cache_state { 139 struct { 140 union { 141 u_int8_t csu_cache_b[2]; 142 u_int16_t csu_cache; 143 } cs_cache_u; 144 145 union { 146 u_int8_t csu_tlb_b[2]; 147 u_int16_t csu_tlb; 148 } cs_tlb_u; 149 } cs_s; 150 u_int32_t cs_all; 151 }; 152 #define cs_cache_id cs_s.cs_cache_u.csu_cache_b[0] 153 #define cs_cache_d cs_s.cs_cache_u.csu_cache_b[1] 154 #define cs_cache cs_s.cs_cache_u.csu_cache 155 #define cs_tlb_id cs_s.cs_tlb_u.csu_tlb_b[0] 156 #define cs_tlb_d cs_s.cs_tlb_u.csu_tlb_b[1] 157 #define cs_tlb cs_s.cs_tlb_u.csu_tlb 158 159 /* 160 * Assigned to cs_all to force cacheops to work for a particular pmap 161 */ 162 #define PMAP_CACHE_STATE_ALL 0xffffffffu 163 164 /* 165 * The pmap structure itself 166 */ 167 struct pmap { 168 u_int8_t pm_domain; 169 boolean_t pm_remove_all; 170 struct l1_ttable *pm_l1; 171 union pmap_cache_state pm_cstate; 172 struct uvm_object pm_obj; 173 #define pm_lock pm_obj.vmobjlock 174 struct l2_dtable *pm_l2[L2_SIZE]; 175 struct pmap_statistics pm_stats; 176 LIST_ENTRY(pmap) pm_list; 177 }; 178 179 #else /* !ARM32_PMAP_NEW */ 180 181 /* 182 * The pmap structure itself. 183 */ 184 struct pmap { 185 struct uvm_object pm_obj; /* uvm_object */ 186 #define pm_lock pm_obj.vmobjlock 187 LIST_ENTRY(pmap) pm_list; /* list (lck by pm_list lock) */ 188 pd_entry_t *pm_pdir; /* KVA of page directory */ 189 struct l1pt *pm_l1pt; /* L1 table metadata */ 190 paddr_t pm_pptpt; /* PA of pt's page table */ 191 vaddr_t pm_vptpt; /* VA of pt's page table */ 192 struct pmap_statistics pm_stats; /* pmap statistics */ 193 struct vm_page *pm_ptphint; /* recently used PT */ 194 }; 195 #endif /* ARM32_PMAP_NEW */ 196 197 typedef struct pmap *pmap_t; 198 199 /* 200 * Physical / virtual address structure. In a number of places (particularly 201 * during bootstrapping) we need to keep track of the physical and virtual 202 * addresses of various pages 203 */ 204 typedef struct pv_addr { 205 SLIST_ENTRY(pv_addr) pv_list; 206 paddr_t pv_pa; 207 vaddr_t pv_va; 208 } pv_addr_t; 209 210 /* 211 * Determine various modes for PTEs (user vs. kernel, cacheable 212 * vs. non-cacheable). 213 */ 214 #define PTE_KERNEL 0 215 #define PTE_USER 1 216 #define PTE_NOCACHE 0 217 #define PTE_CACHE 1 218 #ifdef ARM32_PMAP_NEW 219 #define PTE_PAGETABLE 2 220 #endif 221 222 /* 223 * Flags that indicate attributes of pages or mappings of pages. 224 * 225 * The PVF_MOD and PVF_REF flags are stored in the mdpage for each 226 * page. PVF_WIRED, PVF_WRITE, and PVF_NC are kept in individual 227 * pv_entry's for each page. They live in the same "namespace" so 228 * that we can clear multiple attributes at a time. 229 * 230 * Note the "non-cacheable" flag generally means the page has 231 * multiple mappings in a given address space. 232 */ 233 #define PVF_MOD 0x01 /* page is modified */ 234 #define PVF_REF 0x02 /* page is referenced */ 235 #define PVF_WIRED 0x04 /* mapping is wired */ 236 #define PVF_WRITE 0x08 /* mapping is writable */ 237 #define PVF_EXEC 0x10 /* mapping is executable */ 238 #ifndef ARM32_PMAP_NEW 239 #define PVF_NC 0x20 /* mapping is non-cacheable */ 240 #else 241 #define PVF_UNC 0x20 /* mapping is 'user' non-cacheable */ 242 #define PVF_KNC 0x40 /* mapping is 'kernel' non-cacheable */ 243 #define PVF_NC (PVF_UNC|PVF_KNC) 244 #endif 245 246 /* 247 * Commonly referenced structures 248 */ 249 extern struct pmap kernel_pmap_store; 250 extern int pmap_debug_level; /* Only exists if PMAP_DEBUG */ 251 252 /* 253 * Macros that we need to export 254 */ 255 #define pmap_kernel() (&kernel_pmap_store) 256 #define pmap_resident_count(pmap) ((pmap)->pm_stats.resident_count) 257 #define pmap_wired_count(pmap) ((pmap)->pm_stats.wired_count) 258 259 #define pmap_is_modified(pg) \ 260 (((pg)->mdpage.pvh_attrs & PVF_MOD) != 0) 261 #define pmap_is_referenced(pg) \ 262 (((pg)->mdpage.pvh_attrs & PVF_REF) != 0) 263 264 #define pmap_copy(dp, sp, da, l, sa) /* nothing */ 265 266 #ifndef ARM32_PMAP_NEW 267 /* ARGSUSED */ 268 static __inline void 269 pmap_remove_all(struct pmap *pmap) 270 { 271 /* Nothing. */ 272 } 273 #endif 274 275 #define pmap_phys_address(ppn) (arm_ptob((ppn))) 276 277 /* 278 * Functions that we need to export 279 */ 280 void pmap_procwr(struct proc *, vaddr_t, int); 281 #ifdef ARM32_PMAP_NEW 282 void pmap_remove_all(pmap_t); 283 boolean_t pmap_extract(pmap_t, vaddr_t, paddr_t *); 284 #endif 285 286 #define PMAP_NEED_PROCWR 287 #define PMAP_GROWKERNEL /* turn on pmap_growkernel interface */ 288 289 /* Functions we use internally. */ 290 #ifndef ARM32_PMAP_NEW 291 /* 292 * Old pmap 293 */ 294 void pmap_bootstrap(pd_entry_t *, pv_addr_t); 295 int pmap_handled_emulation(struct pmap *, vaddr_t); 296 int pmap_modified_emulation(struct pmap *, vaddr_t); 297 #else 298 /* 299 * New pmap 300 */ 301 #ifdef ARM32_NEW_VM_LAYOUT 302 void pmap_bootstrap(pd_entry_t *, vaddr_t); 303 #else 304 void pmap_bootstrap(pd_entry_t *); 305 #endif 306 307 int pmap_fault_fixup(pmap_t, vaddr_t, vm_prot_t); 308 boolean_t pmap_get_pde_pte(pmap_t, vaddr_t, pd_entry_t **, pt_entry_t **); 309 boolean_t pmap_get_pde(pmap_t, vaddr_t, pd_entry_t **); 310 void pmap_set_pcb_pagedir(pmap_t, struct pcb *); 311 #endif /* ARM32_PMAP_NEW */ 312 313 void pmap_debug(int); 314 void pmap_postinit(void); 315 316 void vector_page_setprot(int); 317 318 /* Bootstrapping routines. */ 319 void pmap_map_section(vaddr_t, vaddr_t, paddr_t, int, int); 320 void pmap_map_entry(vaddr_t, vaddr_t, paddr_t, int, int); 321 vsize_t pmap_map_chunk(vaddr_t, vaddr_t, paddr_t, vsize_t, int, int); 322 void pmap_link_l2pt(vaddr_t, vaddr_t, pv_addr_t *); 323 324 /* 325 * Special page zero routine for use by the idle loop (no cache cleans). 326 */ 327 boolean_t pmap_pageidlezero(paddr_t); 328 #define PMAP_PAGEIDLEZERO(pa) pmap_pageidlezero((pa)) 329 330 /* 331 * The current top of kernel VM 332 */ 333 extern vaddr_t pmap_curmaxkvaddr; 334 335 /* 336 * Useful macros and constants 337 */ 338 339 #ifndef ARM32_PMAP_NEW 340 /* 341 * While the ARM MMU's L1 descriptors describe a 1M "section", each 342 * one pointing to a 1K L2 table, NetBSD's VM system allocates the 343 * page tables in 4K chunks, and thus we describe 4M "super sections". 344 * 345 * We'll lift terminology from another architecture and refer to this as 346 * the "page directory" size. 347 */ 348 #define PD_SIZE (L1_S_SIZE * 4) /* 4M */ 349 #define PD_OFFSET (PD_SIZE - 1) 350 #define PD_FRAME (~PD_OFFSET) 351 #define PD_SHIFT 22 352 353 /* Virtual address to page table entry */ 354 #define vtopte(va) \ 355 (((pt_entry_t *)PTE_BASE) + arm_btop((vaddr_t) (va))) 356 357 /* Virtual address to physical address */ 358 #define vtophys(va) \ 359 ((*vtopte(va) & L2_S_FRAME) | ((vaddr_t) (va) & L2_S_OFFSET)) 360 361 #define PTE_SYNC(pte) \ 362 cpu_dcache_wb_range((vaddr_t)(pte), sizeof(pt_entry_t)) 363 #define PTE_FLUSH(pte) \ 364 cpu_dcache_wbinv_range((vaddr_t)(pte), sizeof(pt_entry_t)) 365 366 #define PTE_SYNC_RANGE(pte, cnt) \ 367 cpu_dcache_wb_range((vaddr_t)(pte), (cnt) << 2) /* * sizeof(...) */ 368 #define PTE_FLUSH_RANGE(pte, cnt) \ 369 cpu_dcache_wbinv_range((vaddr_t)(pte), (cnt) << 2) /* * sizeof(...) */ 370 371 #else /* ARM32_PMAP_NEW */ 372 373 /* Virtual address to page table entry */ 374 static __inline pt_entry_t * 375 vtopte(vaddr_t va) 376 { 377 pd_entry_t *pdep; 378 pt_entry_t *ptep; 379 380 if (pmap_get_pde_pte(pmap_kernel(), va, &pdep, &ptep) == FALSE) 381 return (NULL); 382 return (ptep); 383 } 384 385 /* 386 * Virtual address to physical address 387 */ 388 static __inline paddr_t 389 vtophys(vaddr_t va) 390 { 391 paddr_t pa; 392 393 if (pmap_extract(pmap_kernel(), va, &pa) == FALSE) 394 return (0); /* XXXSCW: Panic? */ 395 396 return (pa); 397 } 398 #endif /* ARM32_PMAP_NEW */ 399 400 /* 401 * The new pmap ensures that page-tables are always mapping Write-Thru. 402 * Thus, on some platforms we can run fast and loose and avoid syncing PTEs 403 * on every change. 404 * 405 * Actually, this may not work out quite as well as I'd planned. 406 * According to some documentation, the cache-mode "write-thru, unbuffered", 407 * as used by the pmap for page tables, may not work correctly on all types 408 * of cache. 409 */ 410 #if !defined(ARM32_PMAP_NEW) || defined(ARM32_PMAP_NEEDS_PTE_SYNC) 411 #define PTE_SYNC(pte) \ 412 cpu_dcache_wb_range((vaddr_t)(pte), sizeof(pt_entry_t)) 413 #define PTE_FLUSH(pte) \ 414 cpu_dcache_wbinv_range((vaddr_t)(pte), sizeof(pt_entry_t)) 415 416 #define PTE_SYNC_RANGE(pte, cnt) \ 417 cpu_dcache_wb_range((vaddr_t)(pte), (cnt) << 2) /* * sizeof(...) */ 418 #define PTE_FLUSH_RANGE(pte, cnt) \ 419 cpu_dcache_wbinv_range((vaddr_t)(pte), (cnt) << 2) /* * sizeof(...) */ 420 #else 421 #define PTE_SYNC(x) /* no-op */ 422 #define PTE_FLUSH(x) /* no-op */ 423 #define PTE_SYNC_RANGE(x,y) /* no-op */ 424 #define PTE_FLUSH_RANGE(x,y) /* no-op */ 425 #endif 426 427 #define l1pte_valid(pde) ((pde) != 0) 428 #define l1pte_section_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_S) 429 #define l1pte_page_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_C) 430 #define l1pte_fpage_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_F) 431 432 #ifdef ARM32_PMAP_NEW 433 #define l2pte_index(v) (((v) & L2_ADDR_BITS) >> L2_S_SHIFT) 434 #endif 435 #define l2pte_valid(pte) ((pte) != 0) 436 #define l2pte_pa(pte) ((pte) & L2_S_FRAME) 437 438 /* L1 and L2 page table macros */ 439 #ifndef ARM32_PMAP_NEW 440 #define pmap_pdei(v) ((v & L1_S_FRAME) >> L1_S_SHIFT) 441 #define pmap_pde(m, v) (&((m)->pm_pdir[pmap_pdei(v)])) 442 #endif 443 444 #define pmap_pde_v(pde) l1pte_valid(*(pde)) 445 #define pmap_pde_section(pde) l1pte_section_p(*(pde)) 446 #define pmap_pde_page(pde) l1pte_page_p(*(pde)) 447 #define pmap_pde_fpage(pde) l1pte_fpage_p(*(pde)) 448 449 #define pmap_pte_v(pte) l2pte_valid(*(pte)) 450 #define pmap_pte_pa(pte) l2pte_pa(*(pte)) 451 452 /* Size of the kernel part of the L1 page table */ 453 #define KERNEL_PD_SIZE \ 454 (L1_TABLE_SIZE - (KERNEL_BASE >> L1_S_SHIFT) * sizeof(pd_entry_t)) 455 456 /************************* ARM MMU configuration *****************************/ 457 458 #if ARM_MMU_GENERIC == 1 459 void pmap_copy_page_generic(paddr_t, paddr_t); 460 void pmap_zero_page_generic(paddr_t); 461 462 void pmap_pte_init_generic(void); 463 #if defined(CPU_ARM9) 464 void pmap_pte_init_arm9(void); 465 #endif /* CPU_ARM9 */ 466 #endif /* ARM_MMU_GENERIC == 1 */ 467 468 #if ARM_MMU_XSCALE == 1 469 void pmap_copy_page_xscale(paddr_t, paddr_t); 470 void pmap_zero_page_xscale(paddr_t); 471 472 void pmap_pte_init_xscale(void); 473 474 void xscale_setup_minidata(vaddr_t, vaddr_t, paddr_t); 475 #endif /* ARM_MMU_XSCALE == 1 */ 476 477 extern pt_entry_t pte_l1_s_cache_mode; 478 extern pt_entry_t pte_l1_s_cache_mask; 479 480 extern pt_entry_t pte_l2_l_cache_mode; 481 extern pt_entry_t pte_l2_l_cache_mask; 482 483 extern pt_entry_t pte_l2_s_cache_mode; 484 extern pt_entry_t pte_l2_s_cache_mask; 485 486 #ifdef ARM32_PMAP_NEW 487 extern pt_entry_t pte_l1_s_cache_mode_pt; 488 extern pt_entry_t pte_l2_l_cache_mode_pt; 489 extern pt_entry_t pte_l2_s_cache_mode_pt; 490 #endif 491 492 extern pt_entry_t pte_l2_s_prot_u; 493 extern pt_entry_t pte_l2_s_prot_w; 494 extern pt_entry_t pte_l2_s_prot_mask; 495 496 extern pt_entry_t pte_l1_s_proto; 497 extern pt_entry_t pte_l1_c_proto; 498 extern pt_entry_t pte_l2_s_proto; 499 500 extern void (*pmap_copy_page_func)(paddr_t, paddr_t); 501 extern void (*pmap_zero_page_func)(paddr_t); 502 503 /*****************************************************************************/ 504 505 /* 506 * tell MI code that the cache is virtually-indexed *and* virtually-tagged. 507 */ 508 #define PMAP_CACHE_VIVT 509 510 #ifdef ARM32_PMAP_NEW 511 /* 512 * Definitions for MMU domains 513 */ 514 #define PMAP_DOMAINS 15 /* 15 'user' domains (0-14) */ 515 #define PMAP_DOMAIN_KERNEL 15 /* The kernel uses domain #15 */ 516 #endif 517 518 /* 519 * These macros define the various bit masks in the PTE. 520 * 521 * We use these macros since we use different bits on different processor 522 * models. 523 */ 524 #define L1_S_PROT_U (L1_S_AP(AP_U)) 525 #define L1_S_PROT_W (L1_S_AP(AP_W)) 526 #define L1_S_PROT_MASK (L1_S_PROT_U|L1_S_PROT_W) 527 528 #define L1_S_CACHE_MASK_generic (L1_S_B|L1_S_C) 529 #define L1_S_CACHE_MASK_xscale (L1_S_B|L1_S_C|L1_S_XSCALE_TEX(TEX_XSCALE_X)) 530 531 #define L2_L_PROT_U (L2_AP(AP_U)) 532 #define L2_L_PROT_W (L2_AP(AP_W)) 533 #define L2_L_PROT_MASK (L2_L_PROT_U|L2_L_PROT_W) 534 535 #define L2_L_CACHE_MASK_generic (L2_B|L2_C) 536 #define L2_L_CACHE_MASK_xscale (L2_B|L2_C|L2_XSCALE_L_TEX(TEX_XSCALE_X)) 537 538 #define L2_S_PROT_U_generic (L2_AP(AP_U)) 539 #define L2_S_PROT_W_generic (L2_AP(AP_W)) 540 #define L2_S_PROT_MASK_generic (L2_S_PROT_U|L2_S_PROT_W) 541 542 #define L2_S_PROT_U_xscale (L2_AP0(AP_U)) 543 #define L2_S_PROT_W_xscale (L2_AP0(AP_W)) 544 #define L2_S_PROT_MASK_xscale (L2_S_PROT_U|L2_S_PROT_W) 545 546 #define L2_S_CACHE_MASK_generic (L2_B|L2_C) 547 #define L2_S_CACHE_MASK_xscale (L2_B|L2_C|L2_XSCALE_T_TEX(TEX_XSCALE_X)) 548 549 #define L1_S_PROTO_generic (L1_TYPE_S | L1_S_IMP) 550 #define L1_S_PROTO_xscale (L1_TYPE_S) 551 552 #define L1_C_PROTO_generic (L1_TYPE_C | L1_C_IMP2) 553 #define L1_C_PROTO_xscale (L1_TYPE_C) 554 555 #define L2_L_PROTO (L2_TYPE_L) 556 557 #define L2_S_PROTO_generic (L2_TYPE_S) 558 #define L2_S_PROTO_xscale (L2_TYPE_XSCALE_XS) 559 560 /* 561 * User-visible names for the ones that vary with MMU class. 562 */ 563 564 #if ARM_NMMUS > 1 565 /* More than one MMU class configured; use variables. */ 566 #define L2_S_PROT_U pte_l2_s_prot_u 567 #define L2_S_PROT_W pte_l2_s_prot_w 568 #define L2_S_PROT_MASK pte_l2_s_prot_mask 569 570 #define L1_S_CACHE_MASK pte_l1_s_cache_mask 571 #define L2_L_CACHE_MASK pte_l2_l_cache_mask 572 #define L2_S_CACHE_MASK pte_l2_s_cache_mask 573 574 #define L1_S_PROTO pte_l1_s_proto 575 #define L1_C_PROTO pte_l1_c_proto 576 #define L2_S_PROTO pte_l2_s_proto 577 578 #define pmap_copy_page(s, d) (*pmap_copy_page_func)((s), (d)) 579 #define pmap_zero_page(d) (*pmap_zero_page_func)((d)) 580 #elif ARM_MMU_GENERIC == 1 581 #define L2_S_PROT_U L2_S_PROT_U_generic 582 #define L2_S_PROT_W L2_S_PROT_W_generic 583 #define L2_S_PROT_MASK L2_S_PROT_MASK_generic 584 585 #define L1_S_CACHE_MASK L1_S_CACHE_MASK_generic 586 #define L2_L_CACHE_MASK L2_L_CACHE_MASK_generic 587 #define L2_S_CACHE_MASK L2_S_CACHE_MASK_generic 588 589 #define L1_S_PROTO L1_S_PROTO_generic 590 #define L1_C_PROTO L1_C_PROTO_generic 591 #define L2_S_PROTO L2_S_PROTO_generic 592 593 #define pmap_copy_page(s, d) pmap_copy_page_generic((s), (d)) 594 #define pmap_zero_page(d) pmap_zero_page_generic((d)) 595 #elif ARM_MMU_XSCALE == 1 596 #define L2_S_PROT_U L2_S_PROT_U_xscale 597 #define L2_S_PROT_W L2_S_PROT_W_xscale 598 #define L2_S_PROT_MASK L2_S_PROT_MASK_xscale 599 600 #define L1_S_CACHE_MASK L1_S_CACHE_MASK_xscale 601 #define L2_L_CACHE_MASK L2_L_CACHE_MASK_xscale 602 #define L2_S_CACHE_MASK L2_S_CACHE_MASK_xscale 603 604 #define L1_S_PROTO L1_S_PROTO_xscale 605 #define L1_C_PROTO L1_C_PROTO_xscale 606 #define L2_S_PROTO L2_S_PROTO_xscale 607 608 #define pmap_copy_page(s, d) pmap_copy_page_xscale((s), (d)) 609 #define pmap_zero_page(d) pmap_zero_page_xscale((d)) 610 #endif /* ARM_NMMUS > 1 */ 611 612 /* 613 * These macros return various bits based on kernel/user and protection. 614 * Note that the compiler will usually fold these at compile time. 615 */ 616 #define L1_S_PROT(ku, pr) ((((ku) == PTE_USER) ? L1_S_PROT_U : 0) | \ 617 (((pr) & VM_PROT_WRITE) ? L1_S_PROT_W : 0)) 618 619 #define L2_L_PROT(ku, pr) ((((ku) == PTE_USER) ? L2_L_PROT_U : 0) | \ 620 (((pr) & VM_PROT_WRITE) ? L2_L_PROT_W : 0)) 621 622 #define L2_S_PROT(ku, pr) ((((ku) == PTE_USER) ? L2_S_PROT_U : 0) | \ 623 (((pr) & VM_PROT_WRITE) ? L2_S_PROT_W : 0)) 624 625 /* 626 * Macros to test if a mapping is mappable with an L1 Section mapping 627 * or an L2 Large Page mapping. 628 */ 629 #define L1_S_MAPPABLE_P(va, pa, size) \ 630 ((((va) | (pa)) & L1_S_OFFSET) == 0 && (size) >= L1_S_SIZE) 631 632 #define L2_L_MAPPABLE_P(va, pa, size) \ 633 ((((va) | (pa)) & L2_L_OFFSET) == 0 && (size) >= L2_L_SIZE) 634 635 /* 636 * Hooks for the pool allocator. 637 */ 638 #define POOL_VTOPHYS(va) vtophys((vaddr_t) (va)) 639 640 #endif /* _KERNEL */ 641 642 #endif /* _ARM32_PMAP_H_ */ 643
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