pmap.h revision 1.72
1 /* $NetBSD: pmap.h,v 1.72 2003/05/21 18:04:43 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2002, 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe & Steve C. Woodford for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Copyright (c) 1994,1995 Mark Brinicombe. 40 * All rights reserved. 41 * 42 * Redistribution and use in source and binary forms, with or without 43 * modification, are permitted provided that the following conditions 44 * are met: 45 * 1. Redistributions of source code must retain the above copyright 46 * notice, this list of conditions and the following disclaimer. 47 * 2. Redistributions in binary form must reproduce the above copyright 48 * notice, this list of conditions and the following disclaimer in the 49 * documentation and/or other materials provided with the distribution. 50 * 3. All advertising materials mentioning features or use of this software 51 * must display the following acknowledgement: 52 * This product includes software developed by Mark Brinicombe 53 * 4. The name of the author may not be used to endorse or promote products 54 * derived from this software without specific prior written permission. 55 * 56 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 57 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 58 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 59 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 60 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 61 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 62 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 63 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 64 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 65 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 #ifndef _ARM32_PMAP_H_ 69 #define _ARM32_PMAP_H_ 70 71 #ifdef _KERNEL 72 73 #include <arm/cpuconf.h> 74 #include <arm/cpufunc.h> 75 #include <arm/arm32/pte.h> 76 #include <uvm/uvm_object.h> 77 78 /* 79 * a pmap describes a processes' 4GB virtual address space. this 80 * virtual address space can be broken up into 4096 1MB regions which 81 * are described by L1 PTEs in the L1 table. 82 * 83 * There is a line drawn at KERNEL_BASE. Everything below that line 84 * changes when the VM context is switched. Everything above that line 85 * is the same no matter which VM context is running. This is achieved 86 * by making the L1 PTEs for those slots above KERNEL_BASE reference 87 * kernel L2 tables. 88 * 89 * The basic layout of the virtual address space thus looks like this: 90 * 91 * 0xffffffff 92 * . 93 * . 94 * . 95 * KERNEL_BASE 96 * -------------------- 97 * . 98 * . 99 * . 100 * 0x00000000 101 */ 102 103 /* 104 * The number of L2 descriptor tables which can be tracked by an l2_dtable. 105 * A bucket size of 16 provides for 16MB of contiguous virtual address 106 * space per l2_dtable. Most processes will, therefore, require only two or 107 * three of these to map their whole working set. 108 */ 109 #define L2_BUCKET_LOG2 4 110 #define L2_BUCKET_SIZE (1 << L2_BUCKET_LOG2) 111 112 /* 113 * Given the above "L2-descriptors-per-l2_dtable" constant, the number 114 * of l2_dtable structures required to track all possible page descriptors 115 * mappable by an L1 translation table is given by the following constants: 116 */ 117 #define L2_LOG2 ((32 - L1_S_SHIFT) - L2_BUCKET_LOG2) 118 #define L2_SIZE (1 << L2_LOG2) 119 120 struct l1_ttable; 121 struct l2_dtable; 122 123 /* 124 * Track cache/tlb occupancy using the following structure 125 */ 126 union pmap_cache_state { 127 struct { 128 union { 129 u_int8_t csu_cache_b[2]; 130 u_int16_t csu_cache; 131 } cs_cache_u; 132 133 union { 134 u_int8_t csu_tlb_b[2]; 135 u_int16_t csu_tlb; 136 } cs_tlb_u; 137 } cs_s; 138 u_int32_t cs_all; 139 }; 140 #define cs_cache_id cs_s.cs_cache_u.csu_cache_b[0] 141 #define cs_cache_d cs_s.cs_cache_u.csu_cache_b[1] 142 #define cs_cache cs_s.cs_cache_u.csu_cache 143 #define cs_tlb_id cs_s.cs_tlb_u.csu_tlb_b[0] 144 #define cs_tlb_d cs_s.cs_tlb_u.csu_tlb_b[1] 145 #define cs_tlb cs_s.cs_tlb_u.csu_tlb 146 147 /* 148 * Assigned to cs_all to force cacheops to work for a particular pmap 149 */ 150 #define PMAP_CACHE_STATE_ALL 0xffffffffu 151 152 /* 153 * The pmap structure itself 154 */ 155 struct pmap { 156 u_int8_t pm_domain; 157 boolean_t pm_remove_all; 158 struct l1_ttable *pm_l1; 159 union pmap_cache_state pm_cstate; 160 struct uvm_object pm_obj; 161 #define pm_lock pm_obj.vmobjlock 162 struct l2_dtable *pm_l2[L2_SIZE]; 163 struct pmap_statistics pm_stats; 164 LIST_ENTRY(pmap) pm_list; 165 }; 166 167 typedef struct pmap *pmap_t; 168 169 /* 170 * Physical / virtual address structure. In a number of places (particularly 171 * during bootstrapping) we need to keep track of the physical and virtual 172 * addresses of various pages 173 */ 174 typedef struct pv_addr { 175 SLIST_ENTRY(pv_addr) pv_list; 176 paddr_t pv_pa; 177 vaddr_t pv_va; 178 } pv_addr_t; 179 180 /* 181 * Determine various modes for PTEs (user vs. kernel, cacheable 182 * vs. non-cacheable). 183 */ 184 #define PTE_KERNEL 0 185 #define PTE_USER 1 186 #define PTE_NOCACHE 0 187 #define PTE_CACHE 1 188 #define PTE_PAGETABLE 2 189 190 /* 191 * Flags that indicate attributes of pages or mappings of pages. 192 * 193 * The PVF_MOD and PVF_REF flags are stored in the mdpage for each 194 * page. PVF_WIRED, PVF_WRITE, and PVF_NC are kept in individual 195 * pv_entry's for each page. They live in the same "namespace" so 196 * that we can clear multiple attributes at a time. 197 * 198 * Note the "non-cacheable" flag generally means the page has 199 * multiple mappings in a given address space. 200 */ 201 #define PVF_MOD 0x01 /* page is modified */ 202 #define PVF_REF 0x02 /* page is referenced */ 203 #define PVF_WIRED 0x04 /* mapping is wired */ 204 #define PVF_WRITE 0x08 /* mapping is writable */ 205 #define PVF_EXEC 0x10 /* mapping is executable */ 206 #define PVF_UNC 0x20 /* mapping is 'user' non-cacheable */ 207 #define PVF_KNC 0x40 /* mapping is 'kernel' non-cacheable */ 208 #define PVF_NC (PVF_UNC|PVF_KNC) 209 210 /* 211 * Commonly referenced structures 212 */ 213 extern struct pmap kernel_pmap_store; 214 extern int pmap_debug_level; /* Only exists if PMAP_DEBUG */ 215 216 /* 217 * Macros that we need to export 218 */ 219 #define pmap_kernel() (&kernel_pmap_store) 220 #define pmap_resident_count(pmap) ((pmap)->pm_stats.resident_count) 221 #define pmap_wired_count(pmap) ((pmap)->pm_stats.wired_count) 222 223 #define pmap_is_modified(pg) \ 224 (((pg)->mdpage.pvh_attrs & PVF_MOD) != 0) 225 #define pmap_is_referenced(pg) \ 226 (((pg)->mdpage.pvh_attrs & PVF_REF) != 0) 227 228 #define pmap_copy(dp, sp, da, l, sa) /* nothing */ 229 230 #define pmap_phys_address(ppn) (arm_ptob((ppn))) 231 232 /* 233 * Functions that we need to export 234 */ 235 void pmap_procwr(struct proc *, vaddr_t, int); 236 void pmap_remove_all(pmap_t); 237 boolean_t pmap_extract(pmap_t, vaddr_t, paddr_t *); 238 239 #define PMAP_NEED_PROCWR 240 #define PMAP_GROWKERNEL /* turn on pmap_growkernel interface */ 241 242 /* Functions we use internally. */ 243 void pmap_bootstrap(pd_entry_t *, vaddr_t, vaddr_t); 244 245 int pmap_fault_fixup(pmap_t, vaddr_t, vm_prot_t, int); 246 boolean_t pmap_get_pde_pte(pmap_t, vaddr_t, pd_entry_t **, pt_entry_t **); 247 boolean_t pmap_get_pde(pmap_t, vaddr_t, pd_entry_t **); 248 void pmap_set_pcb_pagedir(pmap_t, struct pcb *); 249 250 void pmap_debug(int); 251 void pmap_postinit(void); 252 253 void vector_page_setprot(int); 254 255 /* Bootstrapping routines. */ 256 void pmap_map_section(vaddr_t, vaddr_t, paddr_t, int, int); 257 void pmap_map_entry(vaddr_t, vaddr_t, paddr_t, int, int); 258 vsize_t pmap_map_chunk(vaddr_t, vaddr_t, paddr_t, vsize_t, int, int); 259 void pmap_link_l2pt(vaddr_t, vaddr_t, pv_addr_t *); 260 261 /* 262 * Special page zero routine for use by the idle loop (no cache cleans). 263 */ 264 boolean_t pmap_pageidlezero(paddr_t); 265 #define PMAP_PAGEIDLEZERO(pa) pmap_pageidlezero((pa)) 266 267 /* 268 * The current top of kernel VM 269 */ 270 extern vaddr_t pmap_curmaxkvaddr; 271 272 /* 273 * Useful macros and constants 274 */ 275 276 /* Virtual address to page table entry */ 277 static __inline pt_entry_t * 278 vtopte(vaddr_t va) 279 { 280 pd_entry_t *pdep; 281 pt_entry_t *ptep; 282 283 if (pmap_get_pde_pte(pmap_kernel(), va, &pdep, &ptep) == FALSE) 284 return (NULL); 285 return (ptep); 286 } 287 288 /* 289 * Virtual address to physical address 290 */ 291 static __inline paddr_t 292 vtophys(vaddr_t va) 293 { 294 paddr_t pa; 295 296 if (pmap_extract(pmap_kernel(), va, &pa) == FALSE) 297 return (0); /* XXXSCW: Panic? */ 298 299 return (pa); 300 } 301 302 /* 303 * The new pmap ensures that page-tables are always mapping Write-Thru. 304 * Thus, on some platforms we can run fast and loose and avoid syncing PTEs 305 * on every change. 306 * 307 * Unfortunately, not all CPUs have a write-through cache mode. So we 308 * define PMAP_NEEDS_PTE_SYNC for C code to conditionally do PTE syncs, 309 * and if there is the chance for PTE syncs to be needed, we define 310 * PMAP_INCLUDE_PTE_SYNC so e.g. assembly code can include (and run) 311 * the code. 312 */ 313 extern int pmap_needs_pte_sync; 314 #if defined(_KERNEL_OPT) 315 /* 316 * StrongARM SA-1 caches do not have a write-through mode. So, on these, 317 * we need to do PTE syncs. If only SA-1 is configured, then evaluate 318 * this at compile time. 319 */ 320 #if (ARM_MMU_SA1 == 1) && (ARM_NMMUS == 1) 321 #define PMAP_NEEDS_PTE_SYNC 1 322 #define PMAP_INCLUDE_PTE_SYNC 323 #elif (ARM_MMU_SA1 == 0) 324 #define PMAP_NEEDS_PTE_SYNC 0 325 #endif 326 #endif /* _KERNEL_OPT */ 327 328 /* 329 * Provide a fallback in case we were not able to determine it at 330 * compile-time. 331 */ 332 #ifndef PMAP_NEEDS_PTE_SYNC 333 #define PMAP_NEEDS_PTE_SYNC pmap_needs_pte_sync 334 #define PMAP_INCLUDE_PTE_SYNC 335 #endif 336 337 #define PTE_SYNC(pte) \ 338 do { \ 339 if (PMAP_NEEDS_PTE_SYNC) \ 340 cpu_dcache_wb_range((vaddr_t)(pte), sizeof(pt_entry_t));\ 341 } while (/*CONSTCOND*/0) 342 343 #define PTE_SYNC_RANGE(pte, cnt) \ 344 do { \ 345 if (PMAP_NEEDS_PTE_SYNC) { \ 346 cpu_dcache_wb_range((vaddr_t)(pte), \ 347 (cnt) << 2); /* * sizeof(pt_entry_t) */ \ 348 } \ 349 } while (/*CONSTCOND*/0) 350 351 #define l1pte_valid(pde) ((pde) != 0) 352 #define l1pte_section_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_S) 353 #define l1pte_page_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_C) 354 #define l1pte_fpage_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_F) 355 356 #define l2pte_index(v) (((v) & L2_ADDR_BITS) >> L2_S_SHIFT) 357 #define l2pte_valid(pte) ((pte) != 0) 358 #define l2pte_pa(pte) ((pte) & L2_S_FRAME) 359 360 /* L1 and L2 page table macros */ 361 #define pmap_pde_v(pde) l1pte_valid(*(pde)) 362 #define pmap_pde_section(pde) l1pte_section_p(*(pde)) 363 #define pmap_pde_page(pde) l1pte_page_p(*(pde)) 364 #define pmap_pde_fpage(pde) l1pte_fpage_p(*(pde)) 365 366 #define pmap_pte_v(pte) l2pte_valid(*(pte)) 367 #define pmap_pte_pa(pte) l2pte_pa(*(pte)) 368 369 /* Size of the kernel part of the L1 page table */ 370 #define KERNEL_PD_SIZE \ 371 (L1_TABLE_SIZE - (KERNEL_BASE >> L1_S_SHIFT) * sizeof(pd_entry_t)) 372 373 /************************* ARM MMU configuration *****************************/ 374 375 #if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 376 void pmap_copy_page_generic(paddr_t, paddr_t); 377 void pmap_zero_page_generic(paddr_t); 378 379 void pmap_pte_init_generic(void); 380 #if defined(CPU_ARM8) 381 void pmap_pte_init_arm8(void); 382 #endif 383 #if defined(CPU_ARM9) 384 void pmap_pte_init_arm9(void); 385 #endif /* CPU_ARM9 */ 386 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */ 387 388 #if ARM_MMU_SA1 == 1 389 void pmap_pte_init_sa1(void); 390 #endif /* ARM_MMU_SA1 == 1 */ 391 392 #if ARM_MMU_XSCALE == 1 393 void pmap_copy_page_xscale(paddr_t, paddr_t); 394 void pmap_zero_page_xscale(paddr_t); 395 396 void pmap_pte_init_xscale(void); 397 398 void xscale_setup_minidata(vaddr_t, vaddr_t, paddr_t); 399 #endif /* ARM_MMU_XSCALE == 1 */ 400 401 extern pt_entry_t pte_l1_s_cache_mode; 402 extern pt_entry_t pte_l1_s_cache_mask; 403 404 extern pt_entry_t pte_l2_l_cache_mode; 405 extern pt_entry_t pte_l2_l_cache_mask; 406 407 extern pt_entry_t pte_l2_s_cache_mode; 408 extern pt_entry_t pte_l2_s_cache_mask; 409 410 extern pt_entry_t pte_l1_s_cache_mode_pt; 411 extern pt_entry_t pte_l2_l_cache_mode_pt; 412 extern pt_entry_t pte_l2_s_cache_mode_pt; 413 414 extern pt_entry_t pte_l2_s_prot_u; 415 extern pt_entry_t pte_l2_s_prot_w; 416 extern pt_entry_t pte_l2_s_prot_mask; 417 418 extern pt_entry_t pte_l1_s_proto; 419 extern pt_entry_t pte_l1_c_proto; 420 extern pt_entry_t pte_l2_s_proto; 421 422 extern void (*pmap_copy_page_func)(paddr_t, paddr_t); 423 extern void (*pmap_zero_page_func)(paddr_t); 424 425 /*****************************************************************************/ 426 427 /* 428 * tell MI code that the cache is virtually-indexed *and* virtually-tagged. 429 */ 430 #define PMAP_CACHE_VIVT 431 432 /* 433 * Definitions for MMU domains 434 */ 435 #define PMAP_DOMAINS 15 /* 15 'user' domains (0-14) */ 436 #define PMAP_DOMAIN_KERNEL 15 /* The kernel uses domain #15 */ 437 438 /* 439 * These macros define the various bit masks in the PTE. 440 * 441 * We use these macros since we use different bits on different processor 442 * models. 443 */ 444 #define L1_S_PROT_U (L1_S_AP(AP_U)) 445 #define L1_S_PROT_W (L1_S_AP(AP_W)) 446 #define L1_S_PROT_MASK (L1_S_PROT_U|L1_S_PROT_W) 447 448 #define L1_S_CACHE_MASK_generic (L1_S_B|L1_S_C) 449 #define L1_S_CACHE_MASK_xscale (L1_S_B|L1_S_C|L1_S_XSCALE_TEX(TEX_XSCALE_X)) 450 451 #define L2_L_PROT_U (L2_AP(AP_U)) 452 #define L2_L_PROT_W (L2_AP(AP_W)) 453 #define L2_L_PROT_MASK (L2_L_PROT_U|L2_L_PROT_W) 454 455 #define L2_L_CACHE_MASK_generic (L2_B|L2_C) 456 #define L2_L_CACHE_MASK_xscale (L2_B|L2_C|L2_XSCALE_L_TEX(TEX_XSCALE_X)) 457 458 #define L2_S_PROT_U_generic (L2_AP(AP_U)) 459 #define L2_S_PROT_W_generic (L2_AP(AP_W)) 460 #define L2_S_PROT_MASK_generic (L2_S_PROT_U|L2_S_PROT_W) 461 462 #define L2_S_PROT_U_xscale (L2_AP0(AP_U)) 463 #define L2_S_PROT_W_xscale (L2_AP0(AP_W)) 464 #define L2_S_PROT_MASK_xscale (L2_S_PROT_U|L2_S_PROT_W) 465 466 #define L2_S_CACHE_MASK_generic (L2_B|L2_C) 467 #define L2_S_CACHE_MASK_xscale (L2_B|L2_C|L2_XSCALE_T_TEX(TEX_XSCALE_X)) 468 469 #define L1_S_PROTO_generic (L1_TYPE_S | L1_S_IMP) 470 #define L1_S_PROTO_xscale (L1_TYPE_S) 471 472 #define L1_C_PROTO_generic (L1_TYPE_C | L1_C_IMP2) 473 #define L1_C_PROTO_xscale (L1_TYPE_C) 474 475 #define L2_L_PROTO (L2_TYPE_L) 476 477 #define L2_S_PROTO_generic (L2_TYPE_S) 478 #define L2_S_PROTO_xscale (L2_TYPE_XSCALE_XS) 479 480 /* 481 * User-visible names for the ones that vary with MMU class. 482 */ 483 484 #if ARM_NMMUS > 1 485 /* More than one MMU class configured; use variables. */ 486 #define L2_S_PROT_U pte_l2_s_prot_u 487 #define L2_S_PROT_W pte_l2_s_prot_w 488 #define L2_S_PROT_MASK pte_l2_s_prot_mask 489 490 #define L1_S_CACHE_MASK pte_l1_s_cache_mask 491 #define L2_L_CACHE_MASK pte_l2_l_cache_mask 492 #define L2_S_CACHE_MASK pte_l2_s_cache_mask 493 494 #define L1_S_PROTO pte_l1_s_proto 495 #define L1_C_PROTO pte_l1_c_proto 496 #define L2_S_PROTO pte_l2_s_proto 497 498 #define pmap_copy_page(s, d) (*pmap_copy_page_func)((s), (d)) 499 #define pmap_zero_page(d) (*pmap_zero_page_func)((d)) 500 #elif (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 501 #define L2_S_PROT_U L2_S_PROT_U_generic 502 #define L2_S_PROT_W L2_S_PROT_W_generic 503 #define L2_S_PROT_MASK L2_S_PROT_MASK_generic 504 505 #define L1_S_CACHE_MASK L1_S_CACHE_MASK_generic 506 #define L2_L_CACHE_MASK L2_L_CACHE_MASK_generic 507 #define L2_S_CACHE_MASK L2_S_CACHE_MASK_generic 508 509 #define L1_S_PROTO L1_S_PROTO_generic 510 #define L1_C_PROTO L1_C_PROTO_generic 511 #define L2_S_PROTO L2_S_PROTO_generic 512 513 #define pmap_copy_page(s, d) pmap_copy_page_generic((s), (d)) 514 #define pmap_zero_page(d) pmap_zero_page_generic((d)) 515 #elif ARM_MMU_XSCALE == 1 516 #define L2_S_PROT_U L2_S_PROT_U_xscale 517 #define L2_S_PROT_W L2_S_PROT_W_xscale 518 #define L2_S_PROT_MASK L2_S_PROT_MASK_xscale 519 520 #define L1_S_CACHE_MASK L1_S_CACHE_MASK_xscale 521 #define L2_L_CACHE_MASK L2_L_CACHE_MASK_xscale 522 #define L2_S_CACHE_MASK L2_S_CACHE_MASK_xscale 523 524 #define L1_S_PROTO L1_S_PROTO_xscale 525 #define L1_C_PROTO L1_C_PROTO_xscale 526 #define L2_S_PROTO L2_S_PROTO_xscale 527 528 #define pmap_copy_page(s, d) pmap_copy_page_xscale((s), (d)) 529 #define pmap_zero_page(d) pmap_zero_page_xscale((d)) 530 #endif /* ARM_NMMUS > 1 */ 531 532 /* 533 * These macros return various bits based on kernel/user and protection. 534 * Note that the compiler will usually fold these at compile time. 535 */ 536 #define L1_S_PROT(ku, pr) ((((ku) == PTE_USER) ? L1_S_PROT_U : 0) | \ 537 (((pr) & VM_PROT_WRITE) ? L1_S_PROT_W : 0)) 538 539 #define L2_L_PROT(ku, pr) ((((ku) == PTE_USER) ? L2_L_PROT_U : 0) | \ 540 (((pr) & VM_PROT_WRITE) ? L2_L_PROT_W : 0)) 541 542 #define L2_S_PROT(ku, pr) ((((ku) == PTE_USER) ? L2_S_PROT_U : 0) | \ 543 (((pr) & VM_PROT_WRITE) ? L2_S_PROT_W : 0)) 544 545 /* 546 * Macros to test if a mapping is mappable with an L1 Section mapping 547 * or an L2 Large Page mapping. 548 */ 549 #define L1_S_MAPPABLE_P(va, pa, size) \ 550 ((((va) | (pa)) & L1_S_OFFSET) == 0 && (size) >= L1_S_SIZE) 551 552 #define L2_L_MAPPABLE_P(va, pa, size) \ 553 ((((va) | (pa)) & L2_L_OFFSET) == 0 && (size) >= L2_L_SIZE) 554 555 /* 556 * Hooks for the pool allocator. 557 */ 558 #define POOL_VTOPHYS(va) vtophys((vaddr_t) (va)) 559 560 #endif /* _KERNEL */ 561 562 #endif /* _ARM32_PMAP_H_ */ 563
Indexes created Wed Oct 29 20:09:47 GMT 2025