pmap.h revision 1.79.30.1
1 /* $NetBSD: pmap.h,v 1.79.30.1 2007/11/10 02:56:42 matt Exp $ */ 2 3 /* 4 * Copyright (c) 2002, 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe & Steve C. Woodford for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Copyright (c) 1994,1995 Mark Brinicombe. 40 * All rights reserved. 41 * 42 * Redistribution and use in source and binary forms, with or without 43 * modification, are permitted provided that the following conditions 44 * are met: 45 * 1. Redistributions of source code must retain the above copyright 46 * notice, this list of conditions and the following disclaimer. 47 * 2. Redistributions in binary form must reproduce the above copyright 48 * notice, this list of conditions and the following disclaimer in the 49 * documentation and/or other materials provided with the distribution. 50 * 3. All advertising materials mentioning features or use of this software 51 * must display the following acknowledgement: 52 * This product includes software developed by Mark Brinicombe 53 * 4. The name of the author may not be used to endorse or promote products 54 * derived from this software without specific prior written permission. 55 * 56 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 57 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 58 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 59 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 60 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 61 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 62 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 63 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 64 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 65 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * armv6 and VIPT cache support by 3am Software Foundry, 70 * Copyright (c) 2007 Danger Inc 71 */ 72 73 #ifndef _ARM32_PMAP_H_ 74 #define _ARM32_PMAP_H_ 75 76 #ifdef _KERNEL 77 78 #include <arm/cpuconf.h> 79 #include <arm/arm32/pte.h> 80 #ifndef _LOCORE 81 #include <arm/cpufunc.h> 82 #include <uvm/uvm_object.h> 83 #endif 84 85 /* 86 * a pmap describes a processes' 4GB virtual address space. this 87 * virtual address space can be broken up into 4096 1MB regions which 88 * are described by L1 PTEs in the L1 table. 89 * 90 * There is a line drawn at KERNEL_BASE. Everything below that line 91 * changes when the VM context is switched. Everything above that line 92 * is the same no matter which VM context is running. This is achieved 93 * by making the L1 PTEs for those slots above KERNEL_BASE reference 94 * kernel L2 tables. 95 * 96 * The basic layout of the virtual address space thus looks like this: 97 * 98 * 0xffffffff 99 * . 100 * . 101 * . 102 * KERNEL_BASE 103 * -------------------- 104 * . 105 * . 106 * . 107 * 0x00000000 108 */ 109 110 /* 111 * The number of L2 descriptor tables which can be tracked by an l2_dtable. 112 * A bucket size of 16 provides for 16MB of contiguous virtual address 113 * space per l2_dtable. Most processes will, therefore, require only two or 114 * three of these to map their whole working set. 115 */ 116 #define L2_BUCKET_LOG2 4 117 #define L2_BUCKET_SIZE (1 << L2_BUCKET_LOG2) 118 119 /* 120 * Given the above "L2-descriptors-per-l2_dtable" constant, the number 121 * of l2_dtable structures required to track all possible page descriptors 122 * mappable by an L1 translation table is given by the following constants: 123 */ 124 #define L2_LOG2 ((32 - L1_S_SHIFT) - L2_BUCKET_LOG2) 125 #define L2_SIZE (1 << L2_LOG2) 126 127 #ifndef _LOCORE 128 129 struct l1_ttable; 130 struct l2_dtable; 131 132 /* 133 * Track cache/tlb occupancy using the following structure 134 */ 135 union pmap_cache_state { 136 struct { 137 union { 138 u_int8_t csu_cache_b[2]; 139 u_int16_t csu_cache; 140 } cs_cache_u; 141 142 union { 143 u_int8_t csu_tlb_b[2]; 144 u_int16_t csu_tlb; 145 } cs_tlb_u; 146 } cs_s; 147 u_int32_t cs_all; 148 }; 149 #define cs_cache_id cs_s.cs_cache_u.csu_cache_b[0] 150 #define cs_cache_d cs_s.cs_cache_u.csu_cache_b[1] 151 #define cs_cache cs_s.cs_cache_u.csu_cache 152 #define cs_tlb_id cs_s.cs_tlb_u.csu_tlb_b[0] 153 #define cs_tlb_d cs_s.cs_tlb_u.csu_tlb_b[1] 154 #define cs_tlb cs_s.cs_tlb_u.csu_tlb 155 156 /* 157 * Assigned to cs_all to force cacheops to work for a particular pmap 158 */ 159 #define PMAP_CACHE_STATE_ALL 0xffffffffu 160 161 /* 162 * This structure is used by machine-dependent code to describe 163 * static mappings of devices, created at bootstrap time. 164 */ 165 struct pmap_devmap { 166 vaddr_t pd_va; /* virtual address */ 167 paddr_t pd_pa; /* physical address */ 168 psize_t pd_size; /* size of region */ 169 vm_prot_t pd_prot; /* protection code */ 170 int pd_cache; /* cache attributes */ 171 }; 172 173 /* 174 * The pmap structure itself 175 */ 176 struct pmap { 177 u_int8_t pm_domain; 178 boolean_t pm_remove_all; 179 struct l1_ttable *pm_l1; 180 union pmap_cache_state pm_cstate; 181 struct uvm_object pm_obj; 182 #define pm_lock pm_obj.vmobjlock 183 struct l2_dtable *pm_l2[L2_SIZE]; 184 struct pmap_statistics pm_stats; 185 LIST_ENTRY(pmap) pm_list; 186 }; 187 188 typedef struct pmap *pmap_t; 189 190 /* 191 * Physical / virtual address structure. In a number of places (particularly 192 * during bootstrapping) we need to keep track of the physical and virtual 193 * addresses of various pages 194 */ 195 typedef struct pv_addr { 196 SLIST_ENTRY(pv_addr) pv_list; 197 paddr_t pv_pa; 198 vaddr_t pv_va; 199 } pv_addr_t; 200 201 /* 202 * Determine various modes for PTEs (user vs. kernel, cacheable 203 * vs. non-cacheable). 204 */ 205 #define PTE_KERNEL 0 206 #define PTE_USER 1 207 #define PTE_NOCACHE 0 208 #define PTE_CACHE 1 209 #define PTE_PAGETABLE 2 210 211 /* 212 * Flags that indicate attributes of pages or mappings of pages. 213 * 214 * The PVF_MOD and PVF_REF flags are stored in the mdpage for each 215 * page. PVF_WIRED, PVF_WRITE, and PVF_NC are kept in individual 216 * pv_entry's for each page. They live in the same "namespace" so 217 * that we can clear multiple attributes at a time. 218 * 219 * Note the "non-cacheable" flag generally means the page has 220 * multiple mappings in a given address space. 221 */ 222 #define PVF_MOD 0x01 /* page is modified */ 223 #define PVF_REF 0x02 /* page is referenced */ 224 #define PVF_WIRED 0x04 /* mapping is wired */ 225 #define PVF_WRITE 0x08 /* mapping is writable */ 226 #define PVF_EXEC 0x10 /* mapping is executable */ 227 #define PVF_UNC 0x20 /* mapping is 'user' non-cacheable */ 228 #define PVF_KNC 0x40 /* mapping is 'kernel' non-cacheable */ 229 #define PVF_COLORED 0x80 /* page has a color */ 230 #define PVF_KENTRY 0x0100 /* page entered via pmap_kenter_pa */ 231 #define PVF_NC (PVF_UNC|PVF_KNC) 232 233 /* 234 * Commonly referenced structures 235 */ 236 extern struct pmap kernel_pmap_store; 237 extern int pmap_debug_level; /* Only exists if PMAP_DEBUG */ 238 239 /* 240 * Macros that we need to export 241 */ 242 #define pmap_kernel() (&kernel_pmap_store) 243 #define pmap_resident_count(pmap) ((pmap)->pm_stats.resident_count) 244 #define pmap_wired_count(pmap) ((pmap)->pm_stats.wired_count) 245 246 #define pmap_remove(pmap,sva,eva) pmap_do_remove((pmap),(sva),(eva),0) 247 248 #define pmap_is_modified(pg) \ 249 (((pg)->mdpage.pvh_attrs & PVF_MOD) != 0) 250 #define pmap_is_referenced(pg) \ 251 (((pg)->mdpage.pvh_attrs & PVF_REF) != 0) 252 #define pmap_is_page_colored_p(pg) \ 253 (((pg)->mdpage.pvh_attrs & PVF_COLORED) != 0) 254 255 #define pmap_copy(dp, sp, da, l, sa) /* nothing */ 256 257 #define pmap_phys_address(ppn) (arm_ptob((ppn))) 258 259 /* 260 * Functions that we need to export 261 */ 262 void pmap_procwr(struct proc *, vaddr_t, int); 263 void pmap_remove_all(pmap_t); 264 boolean_t pmap_extract(pmap_t, vaddr_t, paddr_t *); 265 266 #define PMAP_NEED_PROCWR 267 #define PMAP_GROWKERNEL /* turn on pmap_growkernel interface */ 268 269 #if ARM_MMU_V6 > 0 270 #define PMAP_PREFER(hint, vap, sz, td) pmap_prefer((hint), (vap), (td)) 271 void pmap_prefer(vaddr_t, vaddr_t *, int); 272 #endif 273 274 void pmap_icache_sync_range(pmap_t, vaddr_t, vaddr_t); 275 276 /* Functions we use internally. */ 277 void pmap_bootstrap(pd_entry_t *, vaddr_t, vaddr_t); 278 279 void pmap_do_remove(pmap_t, vaddr_t, vaddr_t, int); 280 int pmap_fault_fixup(pmap_t, vaddr_t, vm_prot_t, int); 281 boolean_t pmap_get_pde_pte(pmap_t, vaddr_t, pd_entry_t **, pt_entry_t **); 282 boolean_t pmap_get_pde(pmap_t, vaddr_t, pd_entry_t **); 283 void pmap_set_pcb_pagedir(pmap_t, struct pcb *); 284 285 void pmap_debug(int); 286 void pmap_postinit(void); 287 288 void vector_page_setprot(int); 289 290 const struct pmap_devmap *pmap_devmap_find_pa(paddr_t, psize_t); 291 const struct pmap_devmap *pmap_devmap_find_va(vaddr_t, vsize_t); 292 293 /* Bootstrapping routines. */ 294 void pmap_map_section(vaddr_t, vaddr_t, paddr_t, int, int); 295 void pmap_map_entry(vaddr_t, vaddr_t, paddr_t, int, int); 296 vsize_t pmap_map_chunk(vaddr_t, vaddr_t, paddr_t, vsize_t, int, int); 297 void pmap_link_l2pt(vaddr_t, vaddr_t, pv_addr_t *); 298 void pmap_devmap_bootstrap(vaddr_t, const struct pmap_devmap *); 299 void pmap_devmap_register(const struct pmap_devmap *); 300 301 /* 302 * Special page zero routine for use by the idle loop (no cache cleans). 303 */ 304 boolean_t pmap_pageidlezero(paddr_t); 305 #define PMAP_PAGEIDLEZERO(pa) pmap_pageidlezero((pa)) 306 307 /* 308 * The current top of kernel VM 309 */ 310 extern vaddr_t pmap_curmaxkvaddr; 311 312 /* 313 * Useful macros and constants 314 */ 315 316 /* Virtual address to page table entry */ 317 static inline pt_entry_t * 318 vtopte(vaddr_t va) 319 { 320 pd_entry_t *pdep; 321 pt_entry_t *ptep; 322 323 if (pmap_get_pde_pte(pmap_kernel(), va, &pdep, &ptep) == FALSE) 324 return (NULL); 325 return (ptep); 326 } 327 328 /* 329 * Virtual address to physical address 330 */ 331 static inline paddr_t 332 vtophys(vaddr_t va) 333 { 334 paddr_t pa; 335 336 if (pmap_extract(pmap_kernel(), va, &pa) == FALSE) 337 return (0); /* XXXSCW: Panic? */ 338 339 return (pa); 340 } 341 342 /* 343 * The new pmap ensures that page-tables are always mapping Write-Thru. 344 * Thus, on some platforms we can run fast and loose and avoid syncing PTEs 345 * on every change. 346 * 347 * Unfortunately, not all CPUs have a write-through cache mode. So we 348 * define PMAP_NEEDS_PTE_SYNC for C code to conditionally do PTE syncs, 349 * and if there is the chance for PTE syncs to be needed, we define 350 * PMAP_INCLUDE_PTE_SYNC so e.g. assembly code can include (and run) 351 * the code. 352 */ 353 extern int pmap_needs_pte_sync; 354 #if defined(_KERNEL_OPT) 355 /* 356 * StrongARM SA-1 caches do not have a write-through mode. So, on these, 357 * we need to do PTE syncs. If only SA-1 is configured, then evaluate 358 * this at compile time. 359 */ 360 #if (ARM_MMU_SA1 == 1 || ARM_MMU_V6 == 1) && (ARM_NMMUS == 1) 361 #define PMAP_NEEDS_PTE_SYNC 1 362 #define PMAP_INCLUDE_PTE_SYNC 363 #elif (ARM_MMU_SA1 == 0) 364 #define PMAP_NEEDS_PTE_SYNC 0 365 #endif 366 #endif /* _KERNEL_OPT */ 367 368 /* 369 * Provide a fallback in case we were not able to determine it at 370 * compile-time. 371 */ 372 #ifndef PMAP_NEEDS_PTE_SYNC 373 #define PMAP_NEEDS_PTE_SYNC pmap_needs_pte_sync 374 #define PMAP_INCLUDE_PTE_SYNC 375 #endif 376 377 #define PTE_SYNC(pte) \ 378 do { \ 379 if (PMAP_NEEDS_PTE_SYNC) \ 380 cpu_dcache_wb_range((vaddr_t)(pte), sizeof(pt_entry_t));\ 381 } while (/*CONSTCOND*/0) 382 383 #define PTE_SYNC_RANGE(pte, cnt) \ 384 do { \ 385 if (PMAP_NEEDS_PTE_SYNC) { \ 386 cpu_dcache_wb_range((vaddr_t)(pte), \ 387 (cnt) << 2); /* * sizeof(pt_entry_t) */ \ 388 } \ 389 } while (/*CONSTCOND*/0) 390 391 #define l1pte_valid(pde) ((pde) != 0) 392 #define l1pte_section_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_S) 393 #define l1pte_page_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_C) 394 #define l1pte_fpage_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_F) 395 396 #define l2pte_index(v) (((v) & L2_ADDR_BITS) >> L2_S_SHIFT) 397 #define l2pte_valid(pte) (((pte) & L2_TYPE_MASK) != L2_TYPE_INV) 398 #define l2pte_pa(pte) ((pte) & L2_S_FRAME) 399 #define l2pte_minidata(pte) (((pte) & \ 400 (L2_B | L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X)))\ 401 == (L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X))) 402 403 /* L1 and L2 page table macros */ 404 #define pmap_pde_v(pde) l1pte_valid(*(pde)) 405 #define pmap_pde_section(pde) l1pte_section_p(*(pde)) 406 #define pmap_pde_page(pde) l1pte_page_p(*(pde)) 407 #define pmap_pde_fpage(pde) l1pte_fpage_p(*(pde)) 408 409 #define pmap_pte_v(pte) l2pte_valid(*(pte)) 410 #define pmap_pte_pa(pte) l2pte_pa(*(pte)) 411 412 /* Size of the kernel part of the L1 page table */ 413 #define KERNEL_PD_SIZE \ 414 (L1_TABLE_SIZE - (KERNEL_BASE >> L1_S_SHIFT) * sizeof(pd_entry_t)) 415 416 /************************* ARM MMU configuration *****************************/ 417 418 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 419 void pmap_copy_page_generic(paddr_t, paddr_t); 420 void pmap_zero_page_generic(paddr_t); 421 422 void pmap_pte_init_generic(void); 423 #if defined(CPU_ARM8) 424 void pmap_pte_init_arm8(void); 425 #endif 426 #if defined(CPU_ARM9) 427 void pmap_pte_init_arm9(void); 428 #endif /* CPU_ARM9 */ 429 #if defined(CPU_ARM10) 430 void pmap_pte_init_arm10(void); 431 #endif /* CPU_ARM10 */ 432 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */ 433 434 #if ARM_MMU_SA1 == 1 435 void pmap_pte_init_sa1(void); 436 #endif /* ARM_MMU_SA1 == 1 */ 437 438 #if ARM_MMU_XSCALE == 1 439 void pmap_copy_page_xscale(paddr_t, paddr_t); 440 void pmap_zero_page_xscale(paddr_t); 441 442 void pmap_pte_init_xscale(void); 443 444 void xscale_setup_minidata(vaddr_t, vaddr_t, paddr_t); 445 446 #define PMAP_UAREA(va) pmap_uarea(va) 447 void pmap_uarea(vaddr_t); 448 #endif /* ARM_MMU_XSCALE == 1 */ 449 450 extern pt_entry_t pte_l1_s_cache_mode; 451 extern pt_entry_t pte_l1_s_cache_mask; 452 453 extern pt_entry_t pte_l2_l_cache_mode; 454 extern pt_entry_t pte_l2_l_cache_mask; 455 456 extern pt_entry_t pte_l2_s_cache_mode; 457 extern pt_entry_t pte_l2_s_cache_mask; 458 459 extern pt_entry_t pte_l1_s_cache_mode_pt; 460 extern pt_entry_t pte_l2_l_cache_mode_pt; 461 extern pt_entry_t pte_l2_s_cache_mode_pt; 462 463 extern pt_entry_t pte_l2_s_prot_u; 464 extern pt_entry_t pte_l2_s_prot_w; 465 extern pt_entry_t pte_l2_s_prot_mask; 466 467 extern pt_entry_t pte_l1_s_proto; 468 extern pt_entry_t pte_l1_c_proto; 469 extern pt_entry_t pte_l2_s_proto; 470 471 extern void (*pmap_copy_page_func)(paddr_t, paddr_t); 472 extern void (*pmap_zero_page_func)(paddr_t); 473 474 #endif /* !_LOCORE */ 475 476 /*****************************************************************************/ 477 478 /* 479 * tell MI code whether the cache is virtually-indexed and virtually-tagged 480 * or vitually-indexed and physically tagged. 481 */ 482 #if ARM_MMU_V6 > 0 483 #define PMAP_CACHE_VIPT 484 #else 485 #define PMAP_CACHE_VIVT 486 #endif 487 488 /* 489 * Definitions for MMU domains 490 */ 491 #define PMAP_DOMAINS 15 /* 15 'user' domains (0-14) */ 492 #define PMAP_DOMAIN_KERNEL 15 /* The kernel uses domain #15 */ 493 494 /* 495 * These macros define the various bit masks in the PTE. 496 * 497 * We use these macros since we use different bits on different processor 498 * models. 499 */ 500 #define L1_S_PROT_U (L1_S_AP(AP_U)) 501 #define L1_S_PROT_W (L1_S_AP(AP_W)) 502 #define L1_S_PROT_MASK (L1_S_PROT_U|L1_S_PROT_W) 503 504 #define L1_S_CACHE_MASK_generic (L1_S_B|L1_S_C) 505 #define L1_S_CACHE_MASK_xscale (L1_S_B|L1_S_C|L1_S_XSCALE_TEX(TEX_XSCALE_X)) 506 507 #define L2_L_PROT_U (L2_AP(AP_U)) 508 #define L2_L_PROT_W (L2_AP(AP_W)) 509 #define L2_L_PROT_MASK (L2_L_PROT_U|L2_L_PROT_W) 510 511 #define L2_L_CACHE_MASK_generic (L2_B|L2_C) 512 #define L2_L_CACHE_MASK_xscale (L2_B|L2_C|L2_XSCALE_L_TEX(TEX_XSCALE_X)) 513 514 #define L2_S_PROT_U_generic (L2_AP(AP_U)) 515 #define L2_S_PROT_W_generic (L2_AP(AP_W)) 516 #define L2_S_PROT_MASK_generic (L2_S_PROT_U|L2_S_PROT_W) 517 518 #define L2_S_PROT_U_xscale (L2_AP0(AP_U)) 519 #define L2_S_PROT_W_xscale (L2_AP0(AP_W)) 520 #define L2_S_PROT_MASK_xscale (L2_S_PROT_U|L2_S_PROT_W) 521 522 #define L2_S_CACHE_MASK_generic (L2_B|L2_C) 523 #define L2_S_CACHE_MASK_xscale (L2_B|L2_C|L2_XSCALE_T_TEX(TEX_XSCALE_X)) 524 525 #define L1_S_PROTO_generic (L1_TYPE_S | L1_S_IMP) 526 #define L1_S_PROTO_xscale (L1_TYPE_S) 527 528 #define L1_C_PROTO_generic (L1_TYPE_C | L1_C_IMP2) 529 #define L1_C_PROTO_xscale (L1_TYPE_C) 530 531 #define L2_L_PROTO (L2_TYPE_L) 532 533 #define L2_S_PROTO_generic (L2_TYPE_S) 534 #define L2_S_PROTO_xscale (L2_TYPE_XSCALE_XS) 535 536 /* 537 * User-visible names for the ones that vary with MMU class. 538 */ 539 540 #if ARM_NMMUS > 1 541 /* More than one MMU class configured; use variables. */ 542 #define L2_S_PROT_U pte_l2_s_prot_u 543 #define L2_S_PROT_W pte_l2_s_prot_w 544 #define L2_S_PROT_MASK pte_l2_s_prot_mask 545 546 #define L1_S_CACHE_MASK pte_l1_s_cache_mask 547 #define L2_L_CACHE_MASK pte_l2_l_cache_mask 548 #define L2_S_CACHE_MASK pte_l2_s_cache_mask 549 550 #define L1_S_PROTO pte_l1_s_proto 551 #define L1_C_PROTO pte_l1_c_proto 552 #define L2_S_PROTO pte_l2_s_proto 553 554 #define pmap_copy_page(s, d) (*pmap_copy_page_func)((s), (d)) 555 #define pmap_zero_page(d) (*pmap_zero_page_func)((d)) 556 #elif (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 557 #define L2_S_PROT_U L2_S_PROT_U_generic 558 #define L2_S_PROT_W L2_S_PROT_W_generic 559 #define L2_S_PROT_MASK L2_S_PROT_MASK_generic 560 561 #define L1_S_CACHE_MASK L1_S_CACHE_MASK_generic 562 #define L2_L_CACHE_MASK L2_L_CACHE_MASK_generic 563 #define L2_S_CACHE_MASK L2_S_CACHE_MASK_generic 564 565 #define L1_S_PROTO L1_S_PROTO_generic 566 #define L1_C_PROTO L1_C_PROTO_generic 567 #define L2_S_PROTO L2_S_PROTO_generic 568 569 #define pmap_copy_page(s, d) pmap_copy_page_generic((s), (d)) 570 #define pmap_zero_page(d) pmap_zero_page_generic((d)) 571 #elif ARM_MMU_XSCALE == 1 572 #define L2_S_PROT_U L2_S_PROT_U_xscale 573 #define L2_S_PROT_W L2_S_PROT_W_xscale 574 #define L2_S_PROT_MASK L2_S_PROT_MASK_xscale 575 576 #define L1_S_CACHE_MASK L1_S_CACHE_MASK_xscale 577 #define L2_L_CACHE_MASK L2_L_CACHE_MASK_xscale 578 #define L2_S_CACHE_MASK L2_S_CACHE_MASK_xscale 579 580 #define L1_S_PROTO L1_S_PROTO_xscale 581 #define L1_C_PROTO L1_C_PROTO_xscale 582 #define L2_S_PROTO L2_S_PROTO_xscale 583 584 #define pmap_copy_page(s, d) pmap_copy_page_xscale((s), (d)) 585 #define pmap_zero_page(d) pmap_zero_page_xscale((d)) 586 #endif /* ARM_NMMUS > 1 */ 587 588 /* 589 * These macros return various bits based on kernel/user and protection. 590 * Note that the compiler will usually fold these at compile time. 591 */ 592 #define L1_S_PROT(ku, pr) ((((ku) == PTE_USER) ? L1_S_PROT_U : 0) | \ 593 (((pr) & VM_PROT_WRITE) ? L1_S_PROT_W : 0)) 594 595 #define L2_L_PROT(ku, pr) ((((ku) == PTE_USER) ? L2_L_PROT_U : 0) | \ 596 (((pr) & VM_PROT_WRITE) ? L2_L_PROT_W : 0)) 597 598 #define L2_S_PROT(ku, pr) ((((ku) == PTE_USER) ? L2_S_PROT_U : 0) | \ 599 (((pr) & VM_PROT_WRITE) ? L2_S_PROT_W : 0)) 600 601 /* 602 * Macros to test if a mapping is mappable with an L1 Section mapping 603 * or an L2 Large Page mapping. 604 */ 605 #define L1_S_MAPPABLE_P(va, pa, size) \ 606 ((((va) | (pa)) & L1_S_OFFSET) == 0 && (size) >= L1_S_SIZE) 607 608 #define L2_L_MAPPABLE_P(va, pa, size) \ 609 ((((va) | (pa)) & L2_L_OFFSET) == 0 && (size) >= L2_L_SIZE) 610 611 /* 612 * Hooks for the pool allocator. 613 */ 614 #define POOL_VTOPHYS(va) vtophys((vaddr_t) (va)) 615 616 #endif /* _KERNEL */ 617 618 #endif /* _ARM32_PMAP_H_ */ 619
Indexes created Wed Oct 29 09:09:48 GMT 2025