pmap.h revision 1.88.10.1
1 /* $NetBSD: pmap.h,v 1.88.10.1 2014/02/15 16:18:36 matt Exp $ */ 2 3 /* 4 * Copyright (c) 2002, 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe & Steve C. Woodford for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Copyright (c) 1994,1995 Mark Brinicombe. 40 * All rights reserved. 41 * 42 * Redistribution and use in source and binary forms, with or without 43 * modification, are permitted provided that the following conditions 44 * are met: 45 * 1. Redistributions of source code must retain the above copyright 46 * notice, this list of conditions and the following disclaimer. 47 * 2. Redistributions in binary form must reproduce the above copyright 48 * notice, this list of conditions and the following disclaimer in the 49 * documentation and/or other materials provided with the distribution. 50 * 3. All advertising materials mentioning features or use of this software 51 * must display the following acknowledgement: 52 * This product includes software developed by Mark Brinicombe 53 * 4. The name of the author may not be used to endorse or promote products 54 * derived from this software without specific prior written permission. 55 * 56 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 57 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 58 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 59 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 60 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 61 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 62 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 63 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 64 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 65 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 #ifndef _ARM32_PMAP_H_ 69 #define _ARM32_PMAP_H_ 70 71 #ifdef _KERNEL 72 73 #include <arm/cpuconf.h> 74 #include <arm/arm32/pte.h> 75 #ifndef _LOCORE 76 #if defined(_KERNEL_OPT) 77 #include "opt_arm32_pmap.h" 78 #endif 79 #include <arm/cpufunc.h> 80 #include <uvm/uvm_object.h> 81 #endif 82 83 /* 84 * a pmap describes a processes' 4GB virtual address space. this 85 * virtual address space can be broken up into 4096 1MB regions which 86 * are described by L1 PTEs in the L1 table. 87 * 88 * There is a line drawn at KERNEL_BASE. Everything below that line 89 * changes when the VM context is switched. Everything above that line 90 * is the same no matter which VM context is running. This is achieved 91 * by making the L1 PTEs for those slots above KERNEL_BASE reference 92 * kernel L2 tables. 93 * 94 * The basic layout of the virtual address space thus looks like this: 95 * 96 * 0xffffffff 97 * . 98 * . 99 * . 100 * KERNEL_BASE 101 * -------------------- 102 * . 103 * . 104 * . 105 * 0x00000000 106 */ 107 108 /* 109 * The number of L2 descriptor tables which can be tracked by an l2_dtable. 110 * A bucket size of 16 provides for 16MB of contiguous virtual address 111 * space per l2_dtable. Most processes will, therefore, require only two or 112 * three of these to map their whole working set. 113 */ 114 #define L2_BUCKET_LOG2 4 115 #define L2_BUCKET_SIZE (1 << L2_BUCKET_LOG2) 116 117 /* 118 * Given the above "L2-descriptors-per-l2_dtable" constant, the number 119 * of l2_dtable structures required to track all possible page descriptors 120 * mappable by an L1 translation table is given by the following constants: 121 */ 122 #define L2_LOG2 ((32 - L1_S_SHIFT) - L2_BUCKET_LOG2) 123 #define L2_SIZE (1 << L2_LOG2) 124 125 /* 126 * tell MI code that the cache is virtually-indexed. 127 * ARMv6 is physically-tagged but all others are virtually-tagged. 128 */ 129 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 130 #define PMAP_CACHE_VIPT 131 #else 132 #define PMAP_CACHE_VIVT 133 #endif 134 135 #ifndef _LOCORE 136 137 struct l1_ttable; 138 struct l2_dtable; 139 140 /* 141 * Track cache/tlb occupancy using the following structure 142 */ 143 union pmap_cache_state { 144 struct { 145 union { 146 uint8_t csu_cache_b[2]; 147 uint16_t csu_cache; 148 } cs_cache_u; 149 150 union { 151 uint8_t csu_tlb_b[2]; 152 uint16_t csu_tlb; 153 } cs_tlb_u; 154 } cs_s; 155 uint32_t cs_all; 156 }; 157 #define cs_cache_id cs_s.cs_cache_u.csu_cache_b[0] 158 #define cs_cache_d cs_s.cs_cache_u.csu_cache_b[1] 159 #define cs_cache cs_s.cs_cache_u.csu_cache 160 #define cs_tlb_id cs_s.cs_tlb_u.csu_tlb_b[0] 161 #define cs_tlb_d cs_s.cs_tlb_u.csu_tlb_b[1] 162 #define cs_tlb cs_s.cs_tlb_u.csu_tlb 163 164 /* 165 * Assigned to cs_all to force cacheops to work for a particular pmap 166 */ 167 #define PMAP_CACHE_STATE_ALL 0xffffffffu 168 169 /* 170 * This structure is used by machine-dependent code to describe 171 * static mappings of devices, created at bootstrap time. 172 */ 173 struct pmap_devmap { 174 vaddr_t pd_va; /* virtual address */ 175 paddr_t pd_pa; /* physical address */ 176 psize_t pd_size; /* size of region */ 177 vm_prot_t pd_prot; /* protection code */ 178 int pd_cache; /* cache attributes */ 179 }; 180 181 /* 182 * The pmap structure itself 183 */ 184 struct pmap { 185 uint8_t pm_domain; 186 bool pm_remove_all; 187 bool pm_activated; 188 struct l1_ttable *pm_l1; 189 #ifndef ARM_HAS_VBAR 190 pd_entry_t *pm_pl1vec; 191 #endif 192 pd_entry_t pm_l1vec; 193 union pmap_cache_state pm_cstate; 194 struct uvm_object pm_obj; 195 #define pm_lock pm_obj.vmobjlock 196 struct l2_dtable *pm_l2[L2_SIZE]; 197 struct pmap_statistics pm_stats; 198 LIST_ENTRY(pmap) pm_list; 199 }; 200 201 typedef struct pmap *pmap_t; 202 203 /* 204 * Physical / virtual address structure. In a number of places (particularly 205 * during bootstrapping) we need to keep track of the physical and virtual 206 * addresses of various pages 207 */ 208 typedef struct pv_addr { 209 SLIST_ENTRY(pv_addr) pv_list; 210 paddr_t pv_pa; 211 vaddr_t pv_va; 212 vsize_t pv_size; 213 uint8_t pv_cache; 214 uint8_t pv_prot; 215 } pv_addr_t; 216 typedef SLIST_HEAD(, pv_addr) pv_addrqh_t; 217 218 extern pv_addrqh_t pmap_freeq; 219 extern pv_addr_t kernelstack; 220 extern pv_addr_t abtstack; 221 extern pv_addr_t fiqstack; 222 extern pv_addr_t irqstack; 223 extern pv_addr_t undstack; 224 extern pv_addr_t idlestack; 225 extern pv_addr_t systempage; 226 extern pv_addr_t kernel_l1pt; 227 228 /* 229 * Determine various modes for PTEs (user vs. kernel, cacheable 230 * vs. non-cacheable). 231 */ 232 #define PTE_KERNEL 0 233 #define PTE_USER 1 234 #define PTE_NOCACHE 0 235 #define PTE_CACHE 1 236 #define PTE_PAGETABLE 2 237 238 /* 239 * Flags that indicate attributes of pages or mappings of pages. 240 * 241 * The PVF_MOD and PVF_REF flags are stored in the mdpage for each 242 * page. PVF_WIRED, PVF_WRITE, and PVF_NC are kept in individual 243 * pv_entry's for each page. They live in the same "namespace" so 244 * that we can clear multiple attributes at a time. 245 * 246 * Note the "non-cacheable" flag generally means the page has 247 * multiple mappings in a given address space. 248 */ 249 #define PVF_MOD 0x01 /* page is modified */ 250 #define PVF_REF 0x02 /* page is referenced */ 251 #define PVF_WIRED 0x04 /* mapping is wired */ 252 #define PVF_WRITE 0x08 /* mapping is writable */ 253 #define PVF_EXEC 0x10 /* mapping is executable */ 254 #ifdef PMAP_CACHE_VIVT 255 #define PVF_UNC 0x20 /* mapping is 'user' non-cacheable */ 256 #define PVF_KNC 0x40 /* mapping is 'kernel' non-cacheable */ 257 #define PVF_NC (PVF_UNC|PVF_KNC) 258 #endif 259 #ifdef PMAP_CACHE_VIPT 260 #define PVF_NC 0x20 /* mapping is 'kernel' non-cacheable */ 261 #define PVF_MULTCLR 0x40 /* mapping is multi-colored */ 262 #endif 263 #define PVF_COLORED 0x80 /* page has or had a color */ 264 #define PVF_KENTRY 0x0100 /* page entered via pmap_kenter_pa */ 265 #define PVF_KMPAGE 0x0200 /* page is used for kmem */ 266 #define PVF_DIRTY 0x0400 /* page may have dirty cache lines */ 267 #define PVF_KMOD 0x0800 /* unmanaged page is modified */ 268 #define PVF_KWRITE (PVF_KENTRY|PVF_WRITE) 269 #define PVF_DMOD (PVF_MOD|PVF_KMOD|PVF_KMPAGE) 270 271 /* 272 * Commonly referenced structures 273 */ 274 #define pmap_kernel() (&kernel_pmap_store) 275 extern struct pmap kernel_pmap_store; 276 extern int pmap_debug_level; /* Only exists if PMAP_DEBUG */ 277 extern int arm_poolpage_vmfreelist; 278 279 /* 280 * Macros that we need to export 281 */ 282 #define pmap_resident_count(pmap) ((pmap)->pm_stats.resident_count) 283 #define pmap_wired_count(pmap) ((pmap)->pm_stats.wired_count) 284 285 #define pmap_is_modified(pg) \ 286 (((pg)->mdpage.pvh_attrs & PVF_MOD) != 0) 287 #define pmap_is_referenced(pg) \ 288 (((pg)->mdpage.pvh_attrs & PVF_REF) != 0) 289 #define pmap_is_page_colored_p(md) \ 290 (((md)->pvh_attrs & PVF_COLORED) != 0) 291 292 #define pmap_copy(dp, sp, da, l, sa) /* nothing */ 293 294 #define pmap_phys_address(ppn) (arm_ptob((ppn))) 295 u_int arm32_mmap_flags(paddr_t); 296 #define ARM32_MMAP_WRITECOMBINE 0x40000000 297 #define ARM32_MMAP_CACHEABLE 0x20000000 298 #define pmap_mmap_flags(ppn) arm32_mmap_flags(ppn) 299 300 /* 301 * Functions that we need to export 302 */ 303 void pmap_procwr(struct proc *, vaddr_t, int); 304 void pmap_remove_all(struct pmap *); 305 bool pmap_extract(struct pmap *, vaddr_t, paddr_t *); 306 307 #define PMAP_NEED_PROCWR 308 #define PMAP_GROWKERNEL /* turn on pmap_growkernel interface */ 309 #define PMAP_ENABLE_PMAP_KMPAGE /* enable the PMAP_KMPAGE flag */ 310 311 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 312 #define PMAP_PREFER(hint, vap, sz, td) pmap_prefer((hint), (vap), (td)) 313 void pmap_prefer(vaddr_t, vaddr_t *, int); 314 #endif 315 316 void pmap_icache_sync_range(struct pmap *, vaddr_t, vaddr_t); 317 318 /* Functions we use internally. */ 319 #ifdef PMAP_STEAL_MEMORY 320 void pmap_boot_pagealloc(psize_t, psize_t, psize_t, pv_addr_t *); 321 void pmap_boot_pageadd(pv_addr_t *); 322 vaddr_t pmap_steal_memory(vsize_t, vaddr_t *, vaddr_t *); 323 #endif 324 void pmap_bootstrap(vaddr_t, vaddr_t); 325 326 void pmap_do_remove(struct pmap *, vaddr_t, vaddr_t, int); 327 int pmap_fault_fixup(struct pmap *, vaddr_t, vm_prot_t, int); 328 bool pmap_get_pde_pte(struct pmap *, vaddr_t, pd_entry_t **, pt_entry_t **); 329 bool pmap_get_pde(struct pmap *, vaddr_t, pd_entry_t **); 330 struct pcb; 331 void pmap_set_pcb_pagedir(struct pmap *, struct pcb *); 332 333 void pmap_debug(int); 334 void pmap_postinit(void); 335 336 void vector_page_setprot(int); 337 338 const struct pmap_devmap *pmap_devmap_find_pa(paddr_t, psize_t); 339 const struct pmap_devmap *pmap_devmap_find_va(vaddr_t, vsize_t); 340 341 /* Bootstrapping routines. */ 342 void pmap_map_section(vaddr_t, vaddr_t, paddr_t, int, int); 343 void pmap_map_entry(vaddr_t, vaddr_t, paddr_t, int, int); 344 vsize_t pmap_map_chunk(vaddr_t, vaddr_t, paddr_t, vsize_t, int, int); 345 void pmap_link_l2pt(vaddr_t, vaddr_t, pv_addr_t *); 346 void pmap_devmap_bootstrap(vaddr_t, const struct pmap_devmap *); 347 void pmap_devmap_register(const struct pmap_devmap *); 348 349 /* 350 * Special page zero routine for use by the idle loop (no cache cleans). 351 */ 352 bool pmap_pageidlezero(paddr_t); 353 #define PMAP_PAGEIDLEZERO(pa) pmap_pageidlezero((pa)) 354 355 /* 356 * used by dumpsys to record the PA of the L1 table 357 */ 358 uint32_t pmap_kernel_L1_addr(void); 359 /* 360 * The current top of kernel VM 361 */ 362 extern vaddr_t pmap_curmaxkvaddr; 363 364 /* 365 * Useful macros and constants 366 */ 367 368 /* Virtual address to page table entry */ 369 static inline pt_entry_t * 370 vtopte(vaddr_t va) 371 { 372 pd_entry_t *pdep; 373 pt_entry_t *ptep; 374 375 if (pmap_get_pde_pte(pmap_kernel(), va, &pdep, &ptep) == false) 376 return (NULL); 377 return (ptep); 378 } 379 380 /* 381 * Virtual address to physical address 382 */ 383 static inline paddr_t 384 vtophys(vaddr_t va) 385 { 386 paddr_t pa; 387 388 if (pmap_extract(pmap_kernel(), va, &pa) == false) 389 return (0); /* XXXSCW: Panic? */ 390 391 return (pa); 392 } 393 394 /* 395 * The new pmap ensures that page-tables are always mapping Write-Thru. 396 * Thus, on some platforms we can run fast and loose and avoid syncing PTEs 397 * on every change. 398 * 399 * Unfortunately, not all CPUs have a write-through cache mode. So we 400 * define PMAP_NEEDS_PTE_SYNC for C code to conditionally do PTE syncs, 401 * and if there is the chance for PTE syncs to be needed, we define 402 * PMAP_INCLUDE_PTE_SYNC so e.g. assembly code can include (and run) 403 * the code. 404 */ 405 extern int pmap_needs_pte_sync; 406 #if defined(_KERNEL_OPT) 407 /* 408 * StrongARM SA-1 caches do not have a write-through mode. So, on these, 409 * we need to do PTE syncs. If only SA-1 is configured, then evaluate 410 * this at compile time. 411 */ 412 #if (ARM_MMU_SA1 + ARM_MMU_V6 != 0) && (ARM_NMMUS == 1) 413 #define PMAP_INCLUDE_PTE_SYNC 414 #if (ARM_MMU_V6 > 0) 415 #define PMAP_NEEDS_PTE_SYNC 1 416 #elif (ARM_MMU_SA1 == 0) 417 #define PMAP_NEEDS_PTE_SYNC 0 418 #endif 419 #endif 420 #endif /* _KERNEL_OPT */ 421 422 /* 423 * Provide a fallback in case we were not able to determine it at 424 * compile-time. 425 */ 426 #ifndef PMAP_NEEDS_PTE_SYNC 427 #define PMAP_NEEDS_PTE_SYNC pmap_needs_pte_sync 428 #define PMAP_INCLUDE_PTE_SYNC 429 #endif 430 431 static inline void 432 pmap_ptesync(pt_entry_t *ptep, size_t cnt) 433 { 434 if (PMAP_NEEDS_PTE_SYNC) 435 cpu_dcache_wb_range((vaddr_t)ptep, cnt * sizeof(pt_entry_t)); 436 #if ARM_MMU_V7 > 0 437 __asm("dsb"); 438 #endif 439 } 440 441 #define PTE_SYNC(ptep) pmap_ptesync((ptep), 1) 442 #define PTE_SYNC_RANGE(ptep, cnt) pmap_ptesync((ptep), (cnt)) 443 444 #define l1pte_valid(pde) ((pde) != 0) 445 #define l1pte_section_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_S) 446 #define l1pte_supersection_p(pde) (l1pte_section_p(pde) \ 447 && ((pde) & L1_S_V6_SUPER) != 0) 448 #define l1pte_page_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_C) 449 #define l1pte_fpage_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_F) 450 451 #define l2pte_index(v) (((v) & L2_ADDR_BITS) >> L2_S_SHIFT) 452 #define l2pte_valid(pte) (((pte) & L2_TYPE_MASK) != L2_TYPE_INV) 453 #define l2pte_pa(pte) ((pte) & L2_S_FRAME) 454 #define l2pte_minidata(pte) (((pte) & \ 455 (L2_B | L2_C | L2_XS_T_TEX(TEX_XSCALE_X)))\ 456 == (L2_C | L2_XS_T_TEX(TEX_XSCALE_X))) 457 458 static inline void 459 l2pte_set(pt_entry_t *ptep, pt_entry_t pte, pt_entry_t opte) 460 { 461 KASSERT(*ptep == opte); 462 *ptep = pte; 463 for (vsize_t k = 1; k < PAGE_SIZE / L2_S_SIZE; k++) { 464 KASSERT(ptep[k] == opte ? opte + k * L2_S_SIZE : 0); 465 pte += L2_S_SIZE; 466 ptep[k] = pte; 467 } 468 } 469 470 static inline void 471 l2pte_reset(pt_entry_t *ptep) 472 { 473 *ptep = 0; 474 for (vsize_t k = 1; k < PAGE_SIZE / L2_S_SIZE; k++) { 475 ptep[k] = 0; 476 } 477 } 478 479 /* L1 and L2 page table macros */ 480 #define pmap_pde_v(pde) l1pte_valid(*(pde)) 481 #define pmap_pde_section(pde) l1pte_section_p(*(pde)) 482 #define pmap_pde_supersection(pde) l1pte_supersection_p(*(pde)) 483 #define pmap_pde_page(pde) l1pte_page_p(*(pde)) 484 #define pmap_pde_fpage(pde) l1pte_fpage_p(*(pde)) 485 486 #define pmap_pte_v(pte) l2pte_valid(*(pte)) 487 #define pmap_pte_pa(pte) l2pte_pa(*(pte)) 488 489 /* Size of the kernel part of the L1 page table */ 490 #define KERNEL_PD_SIZE \ 491 (L1_TABLE_SIZE - (KERNEL_BASE >> L1_S_SHIFT) * sizeof(pd_entry_t)) 492 493 void bzero_page(vaddr_t); 494 void bcopy_page(vaddr_t, vaddr_t); 495 496 #ifdef FPU_VFP 497 void bzero_page_vfp(vaddr_t); 498 void bcopy_page_vfp(vaddr_t, vaddr_t); 499 #endif 500 501 /************************* ARM MMU configuration *****************************/ 502 503 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 504 void pmap_copy_page_generic(paddr_t, paddr_t); 505 void pmap_zero_page_generic(paddr_t); 506 507 void pmap_pte_init_generic(void); 508 #if defined(CPU_ARM8) 509 void pmap_pte_init_arm8(void); 510 #endif 511 #if defined(CPU_ARM9) 512 void pmap_pte_init_arm9(void); 513 #endif /* CPU_ARM9 */ 514 #if defined(CPU_ARM10) 515 void pmap_pte_init_arm10(void); 516 #endif /* CPU_ARM10 */ 517 #if defined(CPU_ARM11) /* ARM_MMU_V6 */ 518 void pmap_pte_init_arm11(void); 519 #endif /* CPU_ARM11 */ 520 #if defined(CPU_ARM11MPCORE) /* ARM_MMU_V6 */ 521 void pmap_pte_init_arm11mpcore(void); 522 #endif 523 #if ARM_MMU_V7 == 1 524 void pmap_pte_init_armv7(void); 525 #endif /* ARM_MMU_V7 */ 526 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */ 527 528 #if ARM_MMU_SA1 == 1 529 void pmap_pte_init_sa1(void); 530 #endif /* ARM_MMU_SA1 == 1 */ 531 532 #if ARM_MMU_XSCALE == 1 533 void pmap_copy_page_xscale(paddr_t, paddr_t); 534 void pmap_zero_page_xscale(paddr_t); 535 536 void pmap_pte_init_xscale(void); 537 538 void xscale_setup_minidata(vaddr_t, vaddr_t, paddr_t); 539 540 #define PMAP_UAREA(va) pmap_uarea(va) 541 void pmap_uarea(vaddr_t); 542 #endif /* ARM_MMU_XSCALE == 1 */ 543 544 extern pt_entry_t pte_l1_s_cache_mode; 545 extern pt_entry_t pte_l1_s_cache_mask; 546 547 extern pt_entry_t pte_l2_l_cache_mode; 548 extern pt_entry_t pte_l2_l_cache_mask; 549 550 extern pt_entry_t pte_l2_s_cache_mode; 551 extern pt_entry_t pte_l2_s_cache_mask; 552 553 extern pt_entry_t pte_l1_s_cache_mode_pt; 554 extern pt_entry_t pte_l2_l_cache_mode_pt; 555 extern pt_entry_t pte_l2_s_cache_mode_pt; 556 557 extern pt_entry_t pte_l1_s_wc_mode; 558 extern pt_entry_t pte_l2_l_wc_mode; 559 extern pt_entry_t pte_l2_s_wc_mode; 560 561 extern pt_entry_t pte_l1_s_prot_u; 562 extern pt_entry_t pte_l1_s_prot_w; 563 extern pt_entry_t pte_l1_s_prot_ro; 564 extern pt_entry_t pte_l1_s_prot_mask; 565 566 extern pt_entry_t pte_l2_s_prot_u; 567 extern pt_entry_t pte_l2_s_prot_w; 568 extern pt_entry_t pte_l2_s_prot_ro; 569 extern pt_entry_t pte_l2_s_prot_mask; 570 571 extern pt_entry_t pte_l2_l_prot_u; 572 extern pt_entry_t pte_l2_l_prot_w; 573 extern pt_entry_t pte_l2_l_prot_ro; 574 extern pt_entry_t pte_l2_l_prot_mask; 575 576 extern pt_entry_t pte_l1_ss_proto; 577 extern pt_entry_t pte_l1_s_proto; 578 extern pt_entry_t pte_l1_c_proto; 579 extern pt_entry_t pte_l2_s_proto; 580 581 extern void (*pmap_copy_page_func)(paddr_t, paddr_t); 582 extern void (*pmap_zero_page_func)(paddr_t); 583 584 #endif /* !_LOCORE */ 585 586 /*****************************************************************************/ 587 588 /* 589 * Definitions for MMU domains 590 */ 591 #define PMAP_DOMAINS 15 /* 15 'user' domains (1-15) */ 592 #define PMAP_DOMAIN_KERNEL 0 /* The kernel uses domain #0 */ 593 594 /* 595 * These macros define the various bit masks in the PTE. 596 * 597 * We use these macros since we use different bits on different processor 598 * models. 599 */ 600 #define L1_S_PROT_U_generic (L1_S_AP(AP_U)) 601 #define L1_S_PROT_W_generic (L1_S_AP(AP_W)) 602 #define L1_S_PROT_RO_generic (0) 603 #define L1_S_PROT_MASK_generic (L1_S_PROT_U|L1_S_PROT_W|L1_S_PROT_RO) 604 605 #define L1_S_PROT_U_xscale (L1_S_AP(AP_U)) 606 #define L1_S_PROT_W_xscale (L1_S_AP(AP_W)) 607 #define L1_S_PROT_RO_xscale (0) 608 #define L1_S_PROT_MASK_xscale (L1_S_PROT_U|L1_S_PROT_W|L1_S_PROT_RO) 609 610 #define L1_S_PROT_U_armv6 (L1_S_AP(AP_R) | L1_S_AP(AP_U)) 611 #define L1_S_PROT_W_armv6 (L1_S_AP(AP_W)) 612 #define L1_S_PROT_RO_armv6 (L1_S_AP(AP_R) | L1_S_AP(AP_RO)) 613 #define L1_S_PROT_MASK_armv6 (L1_S_PROT_U|L1_S_PROT_W|L1_S_PROT_RO) 614 615 #define L1_S_PROT_U_armv7 (L1_S_AP(AP_R) | L1_S_AP(AP_U)) 616 #define L1_S_PROT_W_armv7 (L1_S_AP(AP_W)) 617 #define L1_S_PROT_RO_armv7 (L1_S_AP(AP_R) | L1_S_AP(AP_RO)) 618 #define L1_S_PROT_MASK_armv7 (L1_S_PROT_U|L1_S_PROT_W|L1_S_PROT_RO) 619 620 #define L1_S_CACHE_MASK_generic (L1_S_B|L1_S_C) 621 #define L1_S_CACHE_MASK_xscale (L1_S_B|L1_S_C|L1_S_XS_TEX(TEX_XSCALE_X)) 622 #define L1_S_CACHE_MASK_armv6 (L1_S_B|L1_S_C|L1_S_XS_TEX(TEX_ARMV6_TEX)) 623 #define L1_S_CACHE_MASK_armv7 (L1_S_B|L1_S_C|L1_S_XS_TEX(TEX_ARMV6_TEX)|L1_S_V6_S) 624 625 #define L2_L_PROT_U_generic (L2_AP(AP_U)) 626 #define L2_L_PROT_W_generic (L2_AP(AP_W)) 627 #define L2_L_PROT_RO_generic (0) 628 #define L2_L_PROT_MASK_generic (L2_L_PROT_U|L2_L_PROT_W|L2_L_PROT_RO) 629 630 #define L2_L_PROT_U_xscale (L2_AP(AP_U)) 631 #define L2_L_PROT_W_xscale (L2_AP(AP_W)) 632 #define L2_L_PROT_RO_xscale (0) 633 #define L2_L_PROT_MASK_xscale (L2_L_PROT_U|L2_L_PROT_W|L2_L_PROT_RO) 634 635 #define L2_L_PROT_U_armv6n (L2_AP0(AP_R) | L2_AP0(AP_U)) 636 #define L2_L_PROT_W_armv6n (L2_AP0(AP_W)) 637 #define L2_L_PROT_RO_armv6n (L2_AP0(AP_R) | L2_AP0(AP_RO)) 638 #define L2_L_PROT_MASK_armv6n (L2_L_PROT_U|L2_L_PROT_W|L2_L_PROT_RO) 639 640 #define L2_L_PROT_U_armv7 (L2_AP0(AP_R) | L2_AP0(AP_U)) 641 #define L2_L_PROT_W_armv7 (L2_AP0(AP_W)) 642 #define L2_L_PROT_RO_armv7 (L2_AP0(AP_R) | L2_AP0(AP_RO)) 643 #define L2_L_PROT_MASK_armv7 (L2_L_PROT_U|L2_L_PROT_W|L2_L_PROT_RO) 644 645 #define L2_L_CACHE_MASK_generic (L2_B|L2_C) 646 #define L2_L_CACHE_MASK_xscale (L2_B|L2_C|L2_XS_L_TEX(TEX_XSCALE_X)) 647 #define L2_L_CACHE_MASK_armv6 (L2_B|L2_C|L2_V6_L_TEX(TEX_ARMV6_TEX)) 648 #define L2_L_CACHE_MASK_armv7 (L2_B|L2_C|L2_V6_L_TEX(TEX_ARMV6_TEX)|L2_XS_S) 649 650 #define L2_S_PROT_U_generic (L2_AP(AP_U)) 651 #define L2_S_PROT_W_generic (L2_AP(AP_W)) 652 #define L2_S_PROT_RO_generic (0) 653 #define L2_S_PROT_MASK_generic (L2_S_PROT_U|L2_S_PROT_W|L2_S_PROT_RO) 654 655 #define L2_S_PROT_U_xscale (L2_AP0(AP_U)) 656 #define L2_S_PROT_W_xscale (L2_AP0(AP_W)) 657 #define L2_S_PROT_RO_xscale (0) 658 #define L2_S_PROT_MASK_xscale (L2_S_PROT_U|L2_S_PROT_W|L2_S_PROT_RO) 659 660 #define L2_S_PROT_U_armv6n (L2_AP0(AP_R) | L2_AP0(AP_U)) 661 #define L2_S_PROT_W_armv6n (L2_AP0(AP_W)) 662 #define L2_S_PROT_RO_armv6n (L2_AP0(AP_R) | L2_AP0(AP_RO)) 663 #define L2_S_PROT_MASK_armv6n (L2_S_PROT_U|L2_S_PROT_W|L2_S_PROT_RO) 664 665 #define L2_S_PROT_U_armv7 (L2_AP0(AP_R) | L2_AP0(AP_U)) 666 #define L2_S_PROT_W_armv7 (L2_AP0(AP_W)) 667 #define L2_S_PROT_RO_armv7 (L2_AP0(AP_R) | L2_AP0(AP_RO)) 668 #define L2_S_PROT_MASK_armv7 (L2_S_PROT_U|L2_S_PROT_W|L2_S_PROT_RO) 669 670 #define L2_S_CACHE_MASK_generic (L2_B|L2_C) 671 #define L2_S_CACHE_MASK_xscale (L2_B|L2_C|L2_XS_T_TEX(TEX_XSCALE_X)) 672 #define L2_XS_CACHE_MASK_armv6 (L2_B|L2_C|L2_V6_XS_TEX(TEX_ARMV6_TEX)) 673 #define L2_S_CACHE_MASK_armv6n L2_XS_CACHE_MASK_armv6 674 #ifdef ARMV6_EXTENDED_SMALL_PAGE 675 #define L2_S_CACHE_MASK_armv6c L2_XS_CACHE_MASK_armv6 676 #else 677 #define L2_S_CACHE_MASK_armv6c L2_S_CACHE_MASK_generic 678 #endif 679 #define L2_S_CACHE_MASK_armv7 (L2_B|L2_C|L2_V6_XS_TEX(TEX_ARMV6_TEX)|L2_XS_S) 680 681 682 #define L1_S_PROTO_generic (L1_TYPE_S | L1_S_IMP) 683 #define L1_S_PROTO_xscale (L1_TYPE_S) 684 #define L1_S_PROTO_armv6 (L1_TYPE_S) 685 #define L1_S_PROTO_armv7 (L1_TYPE_S) 686 687 #define L1_SS_PROTO_generic 0 688 #define L1_SS_PROTO_xscale 0 689 #define L1_SS_PROTO_armv6 (L1_TYPE_S | L1_S_V6_SS) 690 #define L1_SS_PROTO_armv7 (L1_TYPE_S | L1_S_V6_SS) 691 692 #define L1_C_PROTO_generic (L1_TYPE_C | L1_C_IMP2) 693 #define L1_C_PROTO_xscale (L1_TYPE_C) 694 #define L1_C_PROTO_armv6 (L1_TYPE_C) 695 #define L1_C_PROTO_armv7 (L1_TYPE_C) 696 697 #define L2_L_PROTO (L2_TYPE_L) 698 699 #define L2_S_PROTO_generic (L2_TYPE_S) 700 #define L2_S_PROTO_xscale (L2_TYPE_XS) 701 #ifdef ARMV6_EXTENDED_SMALL_PAGE 702 #define L2_S_PROTO_armv6c (L2_TYPE_XS) /* XP=0, extended small page */ 703 #else 704 #define L2_S_PROTO_armv6c (L2_TYPE_S) /* XP=0, subpage APs */ 705 #endif 706 #define L2_S_PROTO_armv6n (L2_TYPE_S) /* with XP=1 */ 707 #define L2_S_PROTO_armv7 (L2_TYPE_S) 708 709 /* 710 * User-visible names for the ones that vary with MMU class. 711 */ 712 713 #if ARM_NMMUS > 1 714 /* More than one MMU class configured; use variables. */ 715 #define L1_S_PROT_U pte_l1_s_prot_u 716 #define L1_S_PROT_W pte_l1_s_prot_w 717 #define L1_S_PROT_RO pte_l1_s_prot_ro 718 #define L1_S_PROT_MASK pte_l1_s_prot_mask 719 720 #define L2_S_PROT_U pte_l2_s_prot_u 721 #define L2_S_PROT_W pte_l2_s_prot_w 722 #define L2_S_PROT_RO pte_l2_s_prot_ro 723 #define L2_S_PROT_MASK pte_l2_s_prot_mask 724 725 #define L2_L_PROT_U pte_l2_l_prot_u 726 #define L2_L_PROT_W pte_l2_l_prot_w 727 #define L2_L_PROT_RO pte_l2_l_prot_ro 728 #define L2_L_PROT_MASK pte_l2_l_prot_mask 729 730 #define L1_S_CACHE_MASK pte_l1_s_cache_mask 731 #define L2_L_CACHE_MASK pte_l2_l_cache_mask 732 #define L2_S_CACHE_MASK pte_l2_s_cache_mask 733 734 #define L1_SS_PROTO pte_l1_ss_proto 735 #define L1_S_PROTO pte_l1_s_proto 736 #define L1_C_PROTO pte_l1_c_proto 737 #define L2_S_PROTO pte_l2_s_proto 738 739 #define pmap_copy_page(s, d) (*pmap_copy_page_func)((s), (d)) 740 #define pmap_zero_page(d) (*pmap_zero_page_func)((d)) 741 #elif (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 742 #define L1_S_PROT_U L1_S_PROT_U_generic 743 #define L1_S_PROT_W L1_S_PROT_W_generic 744 #define L1_S_PROT_RO L1_S_PROT_RO_generic 745 #define L1_S_PROT_MASK L1_S_PROT_MASK_generic 746 747 #define L2_S_PROT_U L2_S_PROT_U_generic 748 #define L2_S_PROT_W L2_S_PROT_W_generic 749 #define L2_S_PROT_RO L2_S_PROT_RO_generic 750 #define L2_S_PROT_MASK L2_S_PROT_MASK_generic 751 752 #define L2_L_PROT_U L2_L_PROT_U_generic 753 #define L2_L_PROT_W L2_L_PROT_W_generic 754 #define L2_L_PROT_RO L2_L_PROT_RO_generic 755 #define L2_L_PROT_MASK L2_L_PROT_MASK_generic 756 757 #define L1_S_CACHE_MASK L1_S_CACHE_MASK_generic 758 #define L2_L_CACHE_MASK L2_L_CACHE_MASK_generic 759 #define L2_S_CACHE_MASK L2_S_CACHE_MASK_generic 760 761 #define L1_SS_PROTO L1_SS_PROTO_generic 762 #define L1_S_PROTO L1_S_PROTO_generic 763 #define L1_C_PROTO L1_C_PROTO_generic 764 #define L2_S_PROTO L2_S_PROTO_generic 765 766 #define pmap_copy_page(s, d) pmap_copy_page_generic((s), (d)) 767 #define pmap_zero_page(d) pmap_zero_page_generic((d)) 768 #elif ARM_MMU_V6N != 0 769 #define L1_S_PROT_U L1_S_PROT_U_armv6 770 #define L1_S_PROT_W L1_S_PROT_W_armv6 771 #define L1_S_PROT_RO L1_S_PROT_RO_armv6 772 #define L1_S_PROT_MASK L1_S_PROT_MASK_armv6 773 774 #define L2_S_PROT_U L2_S_PROT_U_armv6n 775 #define L2_S_PROT_W L2_S_PROT_W_armv6n 776 #define L2_S_PROT_RO L2_S_PROT_RO_armv6n 777 #define L2_S_PROT_MASK L2_S_PROT_MASK_armv6n 778 779 #define L2_L_PROT_U L2_L_PROT_U_armv6n 780 #define L2_L_PROT_W L2_L_PROT_W_armv6n 781 #define L2_L_PROT_RO L2_L_PROT_RO_armv6n 782 #define L2_L_PROT_MASK L2_L_PROT_MASK_armv6n 783 784 #define L1_S_CACHE_MASK L1_S_CACHE_MASK_armv6 785 #define L2_L_CACHE_MASK L2_L_CACHE_MASK_armv6 786 #define L2_S_CACHE_MASK L2_S_CACHE_MASK_armv6n 787 788 /* These prototypes make writeable mappings, while the other MMU types 789 * make read-only mappings. */ 790 #define L1_SS_PROTO L1_SS_PROTO_armv6 791 #define L1_S_PROTO L1_S_PROTO_armv6 792 #define L1_C_PROTO L1_C_PROTO_armv6 793 #define L2_S_PROTO L2_S_PROTO_armv6n 794 795 #define pmap_copy_page(s, d) pmap_copy_page_generic((s), (d)) 796 #define pmap_zero_page(d) pmap_zero_page_generic((d)) 797 #elif ARM_MMU_V6C != 0 798 #define L1_S_PROT_U L1_S_PROT_U_generic 799 #define L1_S_PROT_W L1_S_PROT_W_generic 800 #define L1_S_PROT_RO L1_S_PROT_RO_generic 801 #define L1_S_PROT_MASK L1_S_PROT_MASK_generic 802 803 #define L2_S_PROT_U L2_S_PROT_U_generic 804 #define L2_S_PROT_W L2_S_PROT_W_generic 805 #define L2_S_PROT_RO L2_S_PROT_RO_generic 806 #define L2_S_PROT_MASK L2_S_PROT_MASK_generic 807 808 #define L2_L_PROT_U L2_L_PROT_U_generic 809 #define L2_L_PROT_W L2_L_PROT_W_generic 810 #define L2_L_PROT_RO L2_L_PROT_RO_generic 811 #define L2_L_PROT_MASK L2_L_PROT_MASK_generic 812 813 #define L1_S_CACHE_MASK L1_S_CACHE_MASK_generic 814 #define L2_L_CACHE_MASK L2_L_CACHE_MASK_generic 815 #define L2_S_CACHE_MASK L2_S_CACHE_MASK_generic 816 817 #define L1_SS_PROTO L1_SS_PROTO_generic 818 #define L1_S_PROTO L1_S_PROTO_generic 819 #define L1_C_PROTO L1_C_PROTO_generic 820 #define L2_S_PROTO L2_S_PROTO_generic 821 822 #define pmap_copy_page(s, d) pmap_copy_page_generic((s), (d)) 823 #define pmap_zero_page(d) pmap_zero_page_generic((d)) 824 #elif ARM_MMU_XSCALE == 1 825 #define L1_S_PROT_U L1_S_PROT_U_generic 826 #define L1_S_PROT_W L1_S_PROT_W_generic 827 #define L1_S_PROT_RO L1_S_PROT_RO_generic 828 #define L1_S_PROT_MASK L1_S_PROT_MASK_generic 829 830 #define L2_S_PROT_U L2_S_PROT_U_xscale 831 #define L2_S_PROT_W L2_S_PROT_W_xscale 832 #define L2_S_PROT_RO L2_S_PROT_RO_xscale 833 #define L2_S_PROT_MASK L2_S_PROT_MASK_xscale 834 835 #define L2_L_PROT_U L2_L_PROT_U_generic 836 #define L2_L_PROT_W L2_L_PROT_W_generic 837 #define L2_L_PROT_RO L2_L_PROT_RO_generic 838 #define L2_L_PROT_MASK L2_L_PROT_MASK_generic 839 840 #define L1_S_CACHE_MASK L1_S_CACHE_MASK_xscale 841 #define L2_L_CACHE_MASK L2_L_CACHE_MASK_xscale 842 #define L2_S_CACHE_MASK L2_S_CACHE_MASK_xscale 843 844 #define L1_SS_PROTO L1_SS_PROTO_xscale 845 #define L1_S_PROTO L1_S_PROTO_xscale 846 #define L1_C_PROTO L1_C_PROTO_xscale 847 #define L2_S_PROTO L2_S_PROTO_xscale 848 849 #define pmap_copy_page(s, d) pmap_copy_page_xscale((s), (d)) 850 #define pmap_zero_page(d) pmap_zero_page_xscale((d)) 851 #elif ARM_MMU_V7 == 1 852 #define L1_S_PROT_U L1_S_PROT_U_armv7 853 #define L1_S_PROT_W L1_S_PROT_W_armv7 854 #define L1_S_PROT_RO L1_S_PROT_RO_armv7 855 #define L1_S_PROT_MASK L1_S_PROT_MASK_armv7 856 857 #define L2_S_PROT_U L2_S_PROT_U_armv7 858 #define L2_S_PROT_W L2_S_PROT_W_armv7 859 #define L2_S_PROT_RO L2_S_PROT_RO_armv7 860 #define L2_S_PROT_MASK L2_S_PROT_MASK_armv7 861 862 #define L2_L_PROT_U L2_L_PROT_U_armv7 863 #define L2_L_PROT_W L2_L_PROT_W_armv7 864 #define L2_L_PROT_RO L2_L_PROT_RO_armv7 865 #define L2_L_PROT_MASK L2_L_PROT_MASK_armv7 866 867 #define L1_S_CACHE_MASK L1_S_CACHE_MASK_armv7 868 #define L2_L_CACHE_MASK L2_L_CACHE_MASK_armv7 869 #define L2_S_CACHE_MASK L2_S_CACHE_MASK_armv7 870 871 /* These prototypes make writeable mappings, while the other MMU types 872 * make read-only mappings. */ 873 #define L1_SS_PROTO L1_SS_PROTO_armv7 874 #define L1_S_PROTO L1_S_PROTO_armv7 875 #define L1_C_PROTO L1_C_PROTO_armv7 876 #define L2_S_PROTO L2_S_PROTO_armv7 877 878 #define pmap_copy_page(s, d) pmap_copy_page_generic((s), (d)) 879 #define pmap_zero_page(d) pmap_zero_page_generic((d)) 880 #endif /* ARM_NMMUS > 1 */ 881 882 /* 883 * Macros to set and query the write permission on page descriptors. 884 */ 885 #define l1pte_set_writable(pte) (((pte) & ~L1_S_PROT_RO) | L1_S_PROT_W) 886 #define l1pte_set_readonly(pte) (((pte) & ~L1_S_PROT_W) | L1_S_PROT_RO) 887 #define l2pte_set_writable(pte) (((pte) & ~L2_S_PROT_RO) | L2_S_PROT_W) 888 #define l2pte_set_readonly(pte) (((pte) & ~L2_S_PROT_W) | L2_S_PROT_RO) 889 890 #define l2pte_writable_p(pte) (((pte) & L2_S_PROT_W) == L2_S_PROT_W && \ 891 (L2_S_PROT_RO == 0 || \ 892 ((pte) & L2_S_PROT_RO) != L2_S_PROT_RO)) 893 894 /* 895 * These macros return various bits based on kernel/user and protection. 896 * Note that the compiler will usually fold these at compile time. 897 */ 898 #define L1_S_PROT(ku, pr) ((((ku) == PTE_USER) ? L1_S_PROT_U : 0) | \ 899 (((pr) & VM_PROT_WRITE) ? L1_S_PROT_W : L1_S_PROT_RO)) 900 901 #define L2_L_PROT(ku, pr) ((((ku) == PTE_USER) ? L2_L_PROT_U : 0) | \ 902 (((pr) & VM_PROT_WRITE) ? L2_L_PROT_W : L2_L_PROT_RO)) 903 904 #define L2_S_PROT(ku, pr) ((((ku) == PTE_USER) ? L2_S_PROT_U : 0) | \ 905 (((pr) & VM_PROT_WRITE) ? L2_S_PROT_W : L2_S_PROT_RO)) 906 907 /* 908 * Macros to test if a mapping is mappable with an L1 SuperSection, 909 * L1 Section, or an L2 Large Page mapping. 910 */ 911 #define L1_SS_MAPPABLE_P(va, pa, size) \ 912 ((((va) | (pa)) & L1_SS_OFFSET) == 0 && (size) >= L1_SS_SIZE) 913 914 #define L1_S_MAPPABLE_P(va, pa, size) \ 915 ((((va) | (pa)) & L1_S_OFFSET) == 0 && (size) >= L1_S_SIZE) 916 917 #define L2_L_MAPPABLE_P(va, pa, size) \ 918 ((((va) | (pa)) & L2_L_OFFSET) == 0 && (size) >= L2_L_SIZE) 919 920 #ifndef _LOCORE 921 /* 922 * Hooks for the pool allocator. 923 */ 924 #define POOL_VTOPHYS(va) vtophys((vaddr_t) (va)) 925 extern paddr_t physical_start, physical_end; 926 #ifdef PMAP_NEED_ALLOC_POOLPAGE 927 struct vm_page *arm_pmap_alloc_poolpage(int); 928 #define PMAP_ALLOC_POOLPAGE arm_pmap_alloc_poolpage 929 #endif 930 #if defined(PMAP_NEED_ALLOC_POOLPAGE) || defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS) 931 #define PMAP_MAP_POOLPAGE(pa) \ 932 ((vaddr_t)((paddr_t)(pa) - physical_start + KERNEL_BASE)) 933 #define PMAP_UNMAP_POOLPAGE(va) \ 934 ((paddr_t)((vaddr_t)(va) - KERNEL_BASE + physical_start)) 935 #endif 936 937 #endif /* !_LOCORE */ 938 939 #endif /* _KERNEL */ 940 941 #endif /* _ARM32_PMAP_H_ */ 942
Indexes created Mon Oct 27 17:09:47 GMT 2025