pmap.h revision 1.94.4.3
1 /* $NetBSD: pmap.h,v 1.94.4.3 2011/03/05 20:49:36 rmind Exp $ */ 2 3 /* 4 * Copyright (c) 2002, 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe & Steve C. Woodford for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Copyright (c) 1994,1995 Mark Brinicombe. 40 * All rights reserved. 41 * 42 * Redistribution and use in source and binary forms, with or without 43 * modification, are permitted provided that the following conditions 44 * are met: 45 * 1. Redistributions of source code must retain the above copyright 46 * notice, this list of conditions and the following disclaimer. 47 * 2. Redistributions in binary form must reproduce the above copyright 48 * notice, this list of conditions and the following disclaimer in the 49 * documentation and/or other materials provided with the distribution. 50 * 3. All advertising materials mentioning features or use of this software 51 * must display the following acknowledgement: 52 * This product includes software developed by Mark Brinicombe 53 * 4. The name of the author may not be used to endorse or promote products 54 * derived from this software without specific prior written permission. 55 * 56 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 57 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 58 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 59 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 60 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 61 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 62 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 63 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 64 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 65 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 #ifndef _ARM32_PMAP_H_ 69 #define _ARM32_PMAP_H_ 70 71 #ifdef _KERNEL 72 73 #include <arm/cpuconf.h> 74 #include <arm/arm32/pte.h> 75 #ifndef _LOCORE 76 #if defined(_KERNEL_OPT) 77 #include "opt_arm32_pmap.h" 78 #endif 79 #include <arm/cpufunc.h> 80 #include <uvm/uvm_object.h> 81 #endif 82 83 /* 84 * a pmap describes a processes' 4GB virtual address space. this 85 * virtual address space can be broken up into 4096 1MB regions which 86 * are described by L1 PTEs in the L1 table. 87 * 88 * There is a line drawn at KERNEL_BASE. Everything below that line 89 * changes when the VM context is switched. Everything above that line 90 * is the same no matter which VM context is running. This is achieved 91 * by making the L1 PTEs for those slots above KERNEL_BASE reference 92 * kernel L2 tables. 93 * 94 * The basic layout of the virtual address space thus looks like this: 95 * 96 * 0xffffffff 97 * . 98 * . 99 * . 100 * KERNEL_BASE 101 * -------------------- 102 * . 103 * . 104 * . 105 * 0x00000000 106 */ 107 108 /* 109 * The number of L2 descriptor tables which can be tracked by an l2_dtable. 110 * A bucket size of 16 provides for 16MB of contiguous virtual address 111 * space per l2_dtable. Most processes will, therefore, require only two or 112 * three of these to map their whole working set. 113 */ 114 #define L2_BUCKET_LOG2 4 115 #define L2_BUCKET_SIZE (1 << L2_BUCKET_LOG2) 116 117 /* 118 * Given the above "L2-descriptors-per-l2_dtable" constant, the number 119 * of l2_dtable structures required to track all possible page descriptors 120 * mappable by an L1 translation table is given by the following constants: 121 */ 122 #define L2_LOG2 ((32 - L1_S_SHIFT) - L2_BUCKET_LOG2) 123 #define L2_SIZE (1 << L2_LOG2) 124 125 /* 126 * tell MI code that the cache is virtually-indexed. 127 * ARMv6 is physically-tagged but all others are virtually-tagged. 128 */ 129 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 130 #define PMAP_CACHE_VIPT 131 #else 132 #define PMAP_CACHE_VIVT 133 #endif 134 135 #ifndef _LOCORE 136 137 struct l1_ttable; 138 struct l2_dtable; 139 140 /* 141 * Track cache/tlb occupancy using the following structure 142 */ 143 union pmap_cache_state { 144 struct { 145 union { 146 u_int8_t csu_cache_b[2]; 147 u_int16_t csu_cache; 148 } cs_cache_u; 149 150 union { 151 u_int8_t csu_tlb_b[2]; 152 u_int16_t csu_tlb; 153 } cs_tlb_u; 154 } cs_s; 155 u_int32_t cs_all; 156 }; 157 #define cs_cache_id cs_s.cs_cache_u.csu_cache_b[0] 158 #define cs_cache_d cs_s.cs_cache_u.csu_cache_b[1] 159 #define cs_cache cs_s.cs_cache_u.csu_cache 160 #define cs_tlb_id cs_s.cs_tlb_u.csu_tlb_b[0] 161 #define cs_tlb_d cs_s.cs_tlb_u.csu_tlb_b[1] 162 #define cs_tlb cs_s.cs_tlb_u.csu_tlb 163 164 /* 165 * Assigned to cs_all to force cacheops to work for a particular pmap 166 */ 167 #define PMAP_CACHE_STATE_ALL 0xffffffffu 168 169 /* 170 * This structure is used by machine-dependent code to describe 171 * static mappings of devices, created at bootstrap time. 172 */ 173 struct pmap_devmap { 174 vaddr_t pd_va; /* virtual address */ 175 paddr_t pd_pa; /* physical address */ 176 psize_t pd_size; /* size of region */ 177 vm_prot_t pd_prot; /* protection code */ 178 int pd_cache; /* cache attributes */ 179 }; 180 181 /* 182 * The pmap structure itself 183 */ 184 struct pmap { 185 u_int8_t pm_domain; 186 bool pm_remove_all; 187 bool pm_activated; 188 struct l1_ttable *pm_l1; 189 pd_entry_t *pm_pl1vec; 190 pd_entry_t pm_l1vec; 191 union pmap_cache_state pm_cstate; 192 struct uvm_object pm_obj; 193 kmutex_t pm_obj_lock; 194 #define pm_lock pm_obj.vmobjlock 195 struct l2_dtable *pm_l2[L2_SIZE]; 196 struct pmap_statistics pm_stats; 197 LIST_ENTRY(pmap) pm_list; 198 }; 199 200 /* 201 * Physical / virtual address structure. In a number of places (particularly 202 * during bootstrapping) we need to keep track of the physical and virtual 203 * addresses of various pages 204 */ 205 typedef struct pv_addr { 206 SLIST_ENTRY(pv_addr) pv_list; 207 paddr_t pv_pa; 208 vaddr_t pv_va; 209 vsize_t pv_size; 210 } pv_addr_t; 211 typedef SLIST_HEAD(, pv_addr) pv_addrqh_t; 212 213 extern pv_addrqh_t pmap_freeq; 214 extern pv_addr_t kernelpages; 215 extern pv_addr_t systempage; 216 extern pv_addr_t kernel_l1pt; 217 218 /* 219 * Determine various modes for PTEs (user vs. kernel, cacheable 220 * vs. non-cacheable). 221 */ 222 #define PTE_KERNEL 0 223 #define PTE_USER 1 224 #define PTE_NOCACHE 0 225 #define PTE_CACHE 1 226 #define PTE_PAGETABLE 2 227 228 /* 229 * Flags that indicate attributes of pages or mappings of pages. 230 * 231 * The PVF_MOD and PVF_REF flags are stored in the mdpage for each 232 * page. PVF_WIRED, PVF_WRITE, and PVF_NC are kept in individual 233 * pv_entry's for each page. They live in the same "namespace" so 234 * that we can clear multiple attributes at a time. 235 * 236 * Note the "non-cacheable" flag generally means the page has 237 * multiple mappings in a given address space. 238 */ 239 #define PVF_MOD 0x01 /* page is modified */ 240 #define PVF_REF 0x02 /* page is referenced */ 241 #define PVF_WIRED 0x04 /* mapping is wired */ 242 #define PVF_WRITE 0x08 /* mapping is writable */ 243 #define PVF_EXEC 0x10 /* mapping is executable */ 244 #ifdef PMAP_CACHE_VIVT 245 #define PVF_UNC 0x20 /* mapping is 'user' non-cacheable */ 246 #define PVF_KNC 0x40 /* mapping is 'kernel' non-cacheable */ 247 #define PVF_NC (PVF_UNC|PVF_KNC) 248 #endif 249 #ifdef PMAP_CACHE_VIPT 250 #define PVF_NC 0x20 /* mapping is 'kernel' non-cacheable */ 251 #define PVF_MULTCLR 0x40 /* mapping is multi-colored */ 252 #endif 253 #define PVF_COLORED 0x80 /* page has or had a color */ 254 #define PVF_KENTRY 0x0100 /* page entered via pmap_kenter_pa */ 255 #define PVF_KMPAGE 0x0200 /* page is used for kmem */ 256 #define PVF_DIRTY 0x0400 /* page may have dirty cache lines */ 257 #define PVF_KMOD 0x0800 /* unmanaged page is modified */ 258 #define PVF_KWRITE (PVF_KENTRY|PVF_WRITE) 259 #define PVF_DMOD (PVF_MOD|PVF_KMOD|PVF_KMPAGE) 260 261 /* 262 * Commonly referenced structures 263 */ 264 extern int pmap_debug_level; /* Only exists if PMAP_DEBUG */ 265 266 /* 267 * Macros that we need to export 268 */ 269 #define pmap_resident_count(pmap) ((pmap)->pm_stats.resident_count) 270 #define pmap_wired_count(pmap) ((pmap)->pm_stats.wired_count) 271 272 #define pmap_is_modified(pg) \ 273 (((pg)->mdpage.pvh_attrs & PVF_MOD) != 0) 274 #define pmap_is_referenced(pg) \ 275 (((pg)->mdpage.pvh_attrs & PVF_REF) != 0) 276 #define pmap_is_page_colored_p(md) \ 277 (((md)->pvh_attrs & PVF_COLORED) != 0) 278 279 #define pmap_copy(dp, sp, da, l, sa) /* nothing */ 280 281 #define pmap_phys_address(ppn) (arm_ptob((ppn))) 282 u_int arm32_mmap_flags(paddr_t); 283 #define ARM32_MMAP_WRITECOMBINE 0x40000000 284 #define ARM32_MMAP_CACHEABLE 0x20000000 285 #define pmap_mmap_flags(ppn) arm32_mmap_flags(ppn) 286 287 /* 288 * Functions that we need to export 289 */ 290 void pmap_procwr(struct proc *, vaddr_t, int); 291 void pmap_remove_all(pmap_t); 292 bool pmap_extract(pmap_t, vaddr_t, paddr_t *); 293 294 #define PMAP_NEED_PROCWR 295 #define PMAP_GROWKERNEL /* turn on pmap_growkernel interface */ 296 #define PMAP_ENABLE_PMAP_KMPAGE /* enable the PMAP_KMPAGE flag */ 297 298 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 299 #define PMAP_PREFER(hint, vap, sz, td) pmap_prefer((hint), (vap), (td)) 300 void pmap_prefer(vaddr_t, vaddr_t *, int); 301 #endif 302 303 void pmap_icache_sync_range(pmap_t, vaddr_t, vaddr_t); 304 305 /* Functions we use internally. */ 306 #ifdef PMAP_STEAL_MEMORY 307 void pmap_boot_pagealloc(psize_t, psize_t, psize_t, pv_addr_t *); 308 void pmap_boot_pageadd(pv_addr_t *); 309 vaddr_t pmap_steal_memory(vsize_t, vaddr_t *, vaddr_t *); 310 #endif 311 void pmap_bootstrap(vaddr_t, vaddr_t); 312 313 void pmap_do_remove(pmap_t, vaddr_t, vaddr_t, int); 314 int pmap_fault_fixup(pmap_t, vaddr_t, vm_prot_t, int); 315 bool pmap_get_pde_pte(pmap_t, vaddr_t, pd_entry_t **, pt_entry_t **); 316 bool pmap_get_pde(pmap_t, vaddr_t, pd_entry_t **); 317 void pmap_set_pcb_pagedir(pmap_t, struct pcb *); 318 319 void pmap_debug(int); 320 void pmap_postinit(void); 321 322 void vector_page_setprot(int); 323 324 const struct pmap_devmap *pmap_devmap_find_pa(paddr_t, psize_t); 325 const struct pmap_devmap *pmap_devmap_find_va(vaddr_t, vsize_t); 326 327 /* Bootstrapping routines. */ 328 void pmap_map_section(vaddr_t, vaddr_t, paddr_t, int, int); 329 void pmap_map_entry(vaddr_t, vaddr_t, paddr_t, int, int); 330 vsize_t pmap_map_chunk(vaddr_t, vaddr_t, paddr_t, vsize_t, int, int); 331 void pmap_link_l2pt(vaddr_t, vaddr_t, pv_addr_t *); 332 void pmap_devmap_bootstrap(vaddr_t, const struct pmap_devmap *); 333 void pmap_devmap_register(const struct pmap_devmap *); 334 335 /* 336 * Special page zero routine for use by the idle loop (no cache cleans). 337 */ 338 bool pmap_pageidlezero(paddr_t); 339 #define PMAP_PAGEIDLEZERO(pa) pmap_pageidlezero((pa)) 340 341 /* 342 * used by dumpsys to record the PA of the L1 table 343 */ 344 uint32_t pmap_kernel_L1_addr(void); 345 /* 346 * The current top of kernel VM 347 */ 348 extern vaddr_t pmap_curmaxkvaddr; 349 350 /* 351 * Useful macros and constants 352 */ 353 354 /* Virtual address to page table entry */ 355 static inline pt_entry_t * 356 vtopte(vaddr_t va) 357 { 358 pd_entry_t *pdep; 359 pt_entry_t *ptep; 360 361 if (pmap_get_pde_pte(pmap_kernel(), va, &pdep, &ptep) == false) 362 return (NULL); 363 return (ptep); 364 } 365 366 /* 367 * Virtual address to physical address 368 */ 369 static inline paddr_t 370 vtophys(vaddr_t va) 371 { 372 paddr_t pa; 373 374 if (pmap_extract(pmap_kernel(), va, &pa) == false) 375 return (0); /* XXXSCW: Panic? */ 376 377 return (pa); 378 } 379 380 /* 381 * The new pmap ensures that page-tables are always mapping Write-Thru. 382 * Thus, on some platforms we can run fast and loose and avoid syncing PTEs 383 * on every change. 384 * 385 * Unfortunately, not all CPUs have a write-through cache mode. So we 386 * define PMAP_NEEDS_PTE_SYNC for C code to conditionally do PTE syncs, 387 * and if there is the chance for PTE syncs to be needed, we define 388 * PMAP_INCLUDE_PTE_SYNC so e.g. assembly code can include (and run) 389 * the code. 390 */ 391 extern int pmap_needs_pte_sync; 392 #if defined(_KERNEL_OPT) 393 /* 394 * StrongARM SA-1 caches do not have a write-through mode. So, on these, 395 * we need to do PTE syncs. If only SA-1 is configured, then evaluate 396 * this at compile time. 397 */ 398 #if (ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7 != 0) && (ARM_NMMUS == 1) 399 #define PMAP_NEEDS_PTE_SYNC 1 400 #define PMAP_INCLUDE_PTE_SYNC 401 #elif (ARM_MMU_SA1 == 0) 402 #define PMAP_NEEDS_PTE_SYNC 0 403 #endif 404 #endif /* _KERNEL_OPT */ 405 406 /* 407 * Provide a fallback in case we were not able to determine it at 408 * compile-time. 409 */ 410 #ifndef PMAP_NEEDS_PTE_SYNC 411 #define PMAP_NEEDS_PTE_SYNC pmap_needs_pte_sync 412 #define PMAP_INCLUDE_PTE_SYNC 413 #endif 414 415 #define PTE_SYNC(pte) \ 416 do { \ 417 if (PMAP_NEEDS_PTE_SYNC) \ 418 cpu_dcache_wb_range((vaddr_t)(pte), sizeof(pt_entry_t));\ 419 } while (/*CONSTCOND*/0) 420 421 #define PTE_SYNC_RANGE(pte, cnt) \ 422 do { \ 423 if (PMAP_NEEDS_PTE_SYNC) { \ 424 cpu_dcache_wb_range((vaddr_t)(pte), \ 425 (cnt) << 2); /* * sizeof(pt_entry_t) */ \ 426 } \ 427 } while (/*CONSTCOND*/0) 428 429 #define l1pte_valid(pde) ((pde) != 0) 430 #define l1pte_section_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_S) 431 #define l1pte_page_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_C) 432 #define l1pte_fpage_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_F) 433 434 #define l2pte_index(v) (((v) & L2_ADDR_BITS) >> L2_S_SHIFT) 435 #define l2pte_valid(pte) (((pte) & L2_TYPE_MASK) != L2_TYPE_INV) 436 #define l2pte_pa(pte) ((pte) & L2_S_FRAME) 437 #define l2pte_minidata(pte) (((pte) & \ 438 (L2_B | L2_C | L2_XS_T_TEX(TEX_XSCALE_X)))\ 439 == (L2_C | L2_XS_T_TEX(TEX_XSCALE_X))) 440 441 /* L1 and L2 page table macros */ 442 #define pmap_pde_v(pde) l1pte_valid(*(pde)) 443 #define pmap_pde_section(pde) l1pte_section_p(*(pde)) 444 #define pmap_pde_page(pde) l1pte_page_p(*(pde)) 445 #define pmap_pde_fpage(pde) l1pte_fpage_p(*(pde)) 446 447 #define pmap_pte_v(pte) l2pte_valid(*(pte)) 448 #define pmap_pte_pa(pte) l2pte_pa(*(pte)) 449 450 /* Size of the kernel part of the L1 page table */ 451 #define KERNEL_PD_SIZE \ 452 (L1_TABLE_SIZE - (KERNEL_BASE >> L1_S_SHIFT) * sizeof(pd_entry_t)) 453 454 /************************* ARM MMU configuration *****************************/ 455 456 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 457 void pmap_copy_page_generic(paddr_t, paddr_t); 458 void pmap_zero_page_generic(paddr_t); 459 460 void pmap_pte_init_generic(void); 461 #if defined(CPU_ARM8) 462 void pmap_pte_init_arm8(void); 463 #endif 464 #if defined(CPU_ARM9) 465 void pmap_pte_init_arm9(void); 466 #endif /* CPU_ARM9 */ 467 #if defined(CPU_ARM10) 468 void pmap_pte_init_arm10(void); 469 #endif /* CPU_ARM10 */ 470 #if defined(CPU_ARM11) 471 void pmap_pte_init_arm11(void); 472 #endif /* CPU_ARM11 */ 473 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */ 474 475 #if ARM_MMU_SA1 == 1 476 void pmap_pte_init_sa1(void); 477 #endif /* ARM_MMU_SA1 == 1 */ 478 479 #if ARM_MMU_XSCALE == 1 480 void pmap_copy_page_xscale(paddr_t, paddr_t); 481 void pmap_zero_page_xscale(paddr_t); 482 483 void pmap_pte_init_xscale(void); 484 485 void xscale_setup_minidata(vaddr_t, vaddr_t, paddr_t); 486 487 #define PMAP_UAREA(va) pmap_uarea(va) 488 void pmap_uarea(vaddr_t); 489 #endif /* ARM_MMU_XSCALE == 1 */ 490 491 #if ARM_MMU_V7 == 1 492 void pmap_pte_init_armv7(void); 493 #endif /* ARM_MMU_V7 */ 494 495 extern pt_entry_t pte_l1_s_cache_mode; 496 extern pt_entry_t pte_l1_s_cache_mask; 497 498 extern pt_entry_t pte_l2_l_cache_mode; 499 extern pt_entry_t pte_l2_l_cache_mask; 500 501 extern pt_entry_t pte_l2_s_cache_mode; 502 extern pt_entry_t pte_l2_s_cache_mask; 503 504 extern pt_entry_t pte_l1_s_cache_mode_pt; 505 extern pt_entry_t pte_l2_l_cache_mode_pt; 506 extern pt_entry_t pte_l2_s_cache_mode_pt; 507 508 extern pt_entry_t pte_l1_s_wc_mode; 509 extern pt_entry_t pte_l2_l_wc_mode; 510 extern pt_entry_t pte_l2_s_wc_mode; 511 512 extern pt_entry_t pte_l1_s_prot_u; 513 extern pt_entry_t pte_l1_s_prot_w; 514 extern pt_entry_t pte_l1_s_prot_ro; 515 extern pt_entry_t pte_l1_s_prot_mask; 516 517 extern pt_entry_t pte_l2_s_prot_u; 518 extern pt_entry_t pte_l2_s_prot_w; 519 extern pt_entry_t pte_l2_s_prot_ro; 520 extern pt_entry_t pte_l2_s_prot_mask; 521 522 extern pt_entry_t pte_l2_l_prot_u; 523 extern pt_entry_t pte_l2_l_prot_w; 524 extern pt_entry_t pte_l2_l_prot_ro; 525 extern pt_entry_t pte_l2_l_prot_mask; 526 527 extern pt_entry_t pte_l1_s_proto; 528 extern pt_entry_t pte_l1_c_proto; 529 extern pt_entry_t pte_l2_s_proto; 530 531 extern void (*pmap_copy_page_func)(paddr_t, paddr_t); 532 extern void (*pmap_zero_page_func)(paddr_t); 533 534 #endif /* !_LOCORE */ 535 536 /*****************************************************************************/ 537 538 /* 539 * Definitions for MMU domains 540 */ 541 #define PMAP_DOMAINS 15 /* 15 'user' domains (0-14) */ 542 #define PMAP_DOMAIN_KERNEL 15 /* The kernel uses domain #15 */ 543 544 /* 545 * These macros define the various bit masks in the PTE. 546 * 547 * We use these macros since we use different bits on different processor 548 * models. 549 */ 550 #define L1_S_PROT_U_generic (L1_S_AP(AP_U)) 551 #define L1_S_PROT_W_generic (L1_S_AP(AP_W)) 552 #define L1_S_PROT_RO_generic (0) 553 #define L1_S_PROT_MASK_generic (L1_S_PROT_U|L1_S_PROT_W|L1_S_PROT_RO) 554 555 #define L1_S_PROT_U_xscale (L1_S_AP(AP_U)) 556 #define L1_S_PROT_W_xscale (L1_S_AP(AP_W)) 557 #define L1_S_PROT_RO_xscale (0) 558 #define L1_S_PROT_MASK_xscale (L1_S_PROT_U|L1_S_PROT_W|L1_S_PROT_RO) 559 560 #define L1_S_PROT_U_armv7 (L1_S_AP(AP_R) | L1_S_AP(AP_U)) 561 #define L1_S_PROT_W_armv7 (L1_S_AP(AP_W)) 562 #define L1_S_PROT_RO_armv7 (L1_S_AP(AP_R) | L1_S_AP(AP_RO)) 563 #define L1_S_PROT_MASK_armv7 (L1_S_PROT_U|L1_S_PROT_W|L1_S_PROT_RO) 564 565 #define L1_S_CACHE_MASK_generic (L1_S_B|L1_S_C) 566 #define L1_S_CACHE_MASK_xscale (L1_S_B|L1_S_C|L1_S_XS_TEX(TEX_XSCALE_X)) 567 #define L1_S_CACHE_MASK_armv7 (L1_S_B|L1_S_C) 568 569 #define L2_L_PROT_U_generic (L2_AP(AP_U)) 570 #define L2_L_PROT_W_generic (L2_AP(AP_W)) 571 #define L2_L_PROT_RO_generic (0) 572 #define L2_L_PROT_MASK_generic (L2_L_PROT_U|L2_L_PROT_W|L2_L_PROT_RO) 573 574 #define L2_L_PROT_U_xscale (L2_AP(AP_U)) 575 #define L2_L_PROT_W_xscale (L2_AP(AP_W)) 576 #define L2_L_PROT_RO_xscale (0) 577 #define L2_L_PROT_MASK_xscale (L2_L_PROT_U|L2_L_PROT_W|L2_L_PROT_RO) 578 579 #define L2_L_PROT_U_armv7 (L2_AP0(AP_R) | L2_AP0(AP_U)) 580 #define L2_L_PROT_W_armv7 (L2_AP0(AP_W)) 581 #define L2_L_PROT_RO_armv7 (L2_AP0(AP_R) | L2_AP0(AP_RO)) 582 #define L2_L_PROT_MASK_armv7 (L2_L_PROT_U|L2_L_PROT_W|L2_L_PROT_RO) 583 584 #define L2_L_CACHE_MASK_generic (L2_B|L2_C) 585 #define L2_L_CACHE_MASK_xscale (L2_B|L2_C|L2_XS_L_TEX(TEX_XSCALE_X)) 586 #define L2_L_CACHE_MASK_armv7 (L2_B|L2_C) 587 588 #define L2_S_PROT_U_generic (L2_AP(AP_U)) 589 #define L2_S_PROT_W_generic (L2_AP(AP_W)) 590 #define L2_S_PROT_RO_generic (0) 591 #define L2_S_PROT_MASK_generic (L2_S_PROT_U|L2_S_PROT_W|L2_S_PROT_RO) 592 593 #define L2_S_PROT_U_xscale (L2_AP0(AP_U)) 594 #define L2_S_PROT_W_xscale (L2_AP0(AP_W)) 595 #define L2_S_PROT_RO_xscale (0) 596 #define L2_S_PROT_MASK_xscale (L2_S_PROT_U|L2_S_PROT_W|L2_S_PROT_RO) 597 598 #define L2_S_PROT_U_armv7 (L2_AP0(AP_R) | L2_AP0(AP_U)) 599 #define L2_S_PROT_W_armv7 (L2_AP0(AP_W)) 600 #define L2_S_PROT_RO_armv7 (L2_AP0(AP_R) | L2_AP0(AP_RO)) 601 #define L2_S_PROT_MASK_armv7 (L2_S_PROT_U|L2_S_PROT_W|L2_S_PROT_RO) 602 603 #define L2_S_CACHE_MASK_generic (L2_B|L2_C) 604 #define L2_S_CACHE_MASK_xscale (L2_B|L2_C|L2_XS_T_TEX(TEX_XSCALE_X)) 605 #define L2_S_CACHE_MASK_armv7 (L2_B|L2_C) 606 607 #define L1_S_PROTO_generic (L1_TYPE_S | L1_S_IMP) 608 #define L1_S_PROTO_xscale (L1_TYPE_S) 609 #define L1_S_PROTO_armv7 (L1_TYPE_S) 610 611 #define L1_C_PROTO_generic (L1_TYPE_C | L1_C_IMP2) 612 #define L1_C_PROTO_xscale (L1_TYPE_C) 613 #define L1_C_PROTO_armv7 (L1_TYPE_C) 614 615 #define L2_L_PROTO (L2_TYPE_L) 616 617 #define L2_S_PROTO_generic (L2_TYPE_S) 618 #define L2_S_PROTO_xscale (L2_TYPE_XS) 619 #define L2_S_PROTO_armv7 (L2_TYPE_S) 620 621 /* 622 * User-visible names for the ones that vary with MMU class. 623 */ 624 625 #if ARM_NMMUS > 1 626 /* More than one MMU class configured; use variables. */ 627 #define L1_S_PROT_U pte_l1_s_prot_u 628 #define L1_S_PROT_W pte_l1_s_prot_w 629 #define L1_S_PROT_RO pte_l1_s_prot_ro 630 #define L1_S_PROT_MASK pte_l1_s_prot_mask 631 632 #define L2_S_PROT_U pte_l2_s_prot_u 633 #define L2_S_PROT_W pte_l2_s_prot_w 634 #define L2_S_PROT_RO pte_l2_s_prot_ro 635 #define L2_S_PROT_MASK pte_l2_s_prot_mask 636 637 #define L2_L_PROT_U pte_l2_l_prot_u 638 #define L2_L_PROT_W pte_l2_l_prot_w 639 #define L2_L_PROT_RO pte_l2_l_prot_ro 640 #define L2_L_PROT_MASK pte_l2_l_prot_mask 641 642 #define L1_S_CACHE_MASK pte_l1_s_cache_mask 643 #define L2_L_CACHE_MASK pte_l2_l_cache_mask 644 #define L2_S_CACHE_MASK pte_l2_s_cache_mask 645 646 #define L1_S_PROTO pte_l1_s_proto 647 #define L1_C_PROTO pte_l1_c_proto 648 #define L2_S_PROTO pte_l2_s_proto 649 650 #define pmap_copy_page(s, d) (*pmap_copy_page_func)((s), (d)) 651 #define pmap_zero_page(d) (*pmap_zero_page_func)((d)) 652 #elif (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 653 #define L1_S_PROT_U L1_S_PROT_U_generic 654 #define L1_S_PROT_W L1_S_PROT_W_generic 655 #define L1_S_PROT_RO L1_S_PROT_RO_generic 656 #define L1_S_PROT_MASK L1_S_PROT_MASK_generic 657 658 #define L2_S_PROT_U L2_S_PROT_U_generic 659 #define L2_S_PROT_W L2_S_PROT_W_generic 660 #define L2_S_PROT_RO L2_S_PROT_RO_generic 661 #define L2_S_PROT_MASK L2_S_PROT_MASK_generic 662 663 #define L2_L_PROT_U L2_L_PROT_U_generic 664 #define L2_L_PROT_W L2_L_PROT_W_generic 665 #define L2_L_PROT_RO L2_L_PROT_RO_generic 666 #define L2_L_PROT_MASK L2_L_PROT_MASK_generic 667 668 #define L1_S_CACHE_MASK L1_S_CACHE_MASK_generic 669 #define L2_L_CACHE_MASK L2_L_CACHE_MASK_generic 670 #define L2_S_CACHE_MASK L2_S_CACHE_MASK_generic 671 672 #define L1_S_PROTO L1_S_PROTO_generic 673 #define L1_C_PROTO L1_C_PROTO_generic 674 #define L2_S_PROTO L2_S_PROTO_generic 675 676 #define pmap_copy_page(s, d) pmap_copy_page_generic((s), (d)) 677 #define pmap_zero_page(d) pmap_zero_page_generic((d)) 678 #elif ARM_MMU_XSCALE == 1 679 #define L1_S_PROT_U L1_S_PROT_U_generic 680 #define L1_S_PROT_W L1_S_PROT_W_generic 681 #define L1_S_PROT_RO L1_S_PROT_RO_generic 682 #define L1_S_PROT_MASK L1_S_PROT_MASK_generic 683 684 #define L2_S_PROT_U L2_S_PROT_U_xscale 685 #define L2_S_PROT_W L2_S_PROT_W_xscale 686 #define L2_S_PROT_RO L2_S_PROT_RO_xscale 687 #define L2_S_PROT_MASK L2_S_PROT_MASK_xscale 688 689 #define L2_L_PROT_U L2_L_PROT_U_generic 690 #define L2_L_PROT_W L2_L_PROT_W_generic 691 #define L2_L_PROT_RO L2_L_PROT_RO_generic 692 #define L2_L_PROT_MASK L2_L_PROT_MASK_generic 693 694 #define L1_S_CACHE_MASK L1_S_CACHE_MASK_xscale 695 #define L2_L_CACHE_MASK L2_L_CACHE_MASK_xscale 696 #define L2_S_CACHE_MASK L2_S_CACHE_MASK_xscale 697 698 #define L1_S_PROTO L1_S_PROTO_xscale 699 #define L1_C_PROTO L1_C_PROTO_xscale 700 #define L2_S_PROTO L2_S_PROTO_xscale 701 702 #define pmap_copy_page(s, d) pmap_copy_page_xscale((s), (d)) 703 #define pmap_zero_page(d) pmap_zero_page_xscale((d)) 704 #elif ARM_MMU_V7 == 1 705 #define L1_S_PROT_U L1_S_PROT_U_armv7 706 #define L1_S_PROT_W L1_S_PROT_W_armv7 707 #define L1_S_PROT_RO L1_S_PROT_RO_armv7 708 #define L1_S_PROT_MASK L1_S_PROT_MASK_armv7 709 710 #define L2_S_PROT_U L2_S_PROT_U_armv7 711 #define L2_S_PROT_W L2_S_PROT_W_armv7 712 #define L2_S_PROT_RO L2_S_PROT_RO_armv7 713 #define L2_S_PROT_MASK L2_S_PROT_MASK_armv7 714 715 #define L2_L_PROT_U L2_L_PROT_U_armv7 716 #define L2_L_PROT_W L2_L_PROT_W_armv7 717 #define L2_L_PROT_RO L2_L_PROT_RO_armv7 718 #define L2_L_PROT_MASK L2_L_PROT_MASK_armv7 719 720 #define L1_S_CACHE_MASK L1_S_CACHE_MASK_armv7 721 #define L2_L_CACHE_MASK L2_L_CACHE_MASK_armv7 722 #define L2_S_CACHE_MASK L2_S_CACHE_MASK_armv7 723 724 /* These prototypes make writeable mappings, while the other MMU types 725 * make read-only mappings. */ 726 #define L1_S_PROTO L1_S_PROTO_armv7 727 #define L1_C_PROTO L1_C_PROTO_armv7 728 #define L2_S_PROTO L2_S_PROTO_armv7 729 730 #define pmap_copy_page(s, d) pmap_copy_page_generic((s), (d)) 731 #define pmap_zero_page(d) pmap_zero_page_generic((d)) 732 #endif /* ARM_NMMUS > 1 */ 733 734 /* 735 * Macros to set and query the write permission on page descriptors. 736 */ 737 #define l1pte_set_writable(pte) (((pte) & ~L1_S_PROT_RO) | L1_S_PROT_W) 738 #define l1pte_set_readonly(pte) (((pte) & ~L1_S_PROT_W) | L1_S_PROT_RO) 739 #define l2pte_set_writable(pte) (((pte) & ~L2_S_PROT_RO) | L2_S_PROT_W) 740 #define l2pte_set_readonly(pte) (((pte) & ~L2_S_PROT_W) | L2_S_PROT_RO) 741 742 #define l2pte_writable_p(pte) (((pte) & L2_S_PROT_W) == L2_S_PROT_W && \ 743 (L2_S_PROT_RO == 0 || \ 744 ((pte) & L2_S_PROT_RO) != L2_S_PROT_RO)) 745 746 /* 747 * These macros return various bits based on kernel/user and protection. 748 * Note that the compiler will usually fold these at compile time. 749 */ 750 #define L1_S_PROT(ku, pr) ((((ku) == PTE_USER) ? L1_S_PROT_U : 0) | \ 751 (((pr) & VM_PROT_WRITE) ? L1_S_PROT_W : L1_S_PROT_RO)) 752 753 #define L2_L_PROT(ku, pr) ((((ku) == PTE_USER) ? L2_L_PROT_U : 0) | \ 754 (((pr) & VM_PROT_WRITE) ? L2_L_PROT_W : L2_L_PROT_RO)) 755 756 #define L2_S_PROT(ku, pr) ((((ku) == PTE_USER) ? L2_S_PROT_U : 0) | \ 757 (((pr) & VM_PROT_WRITE) ? L2_S_PROT_W : L2_S_PROT_RO)) 758 759 /* 760 * Macros to test if a mapping is mappable with an L1 Section mapping 761 * or an L2 Large Page mapping. 762 */ 763 #define L1_S_MAPPABLE_P(va, pa, size) \ 764 ((((va) | (pa)) & L1_S_OFFSET) == 0 && (size) >= L1_S_SIZE) 765 766 #define L2_L_MAPPABLE_P(va, pa, size) \ 767 ((((va) | (pa)) & L2_L_OFFSET) == 0 && (size) >= L2_L_SIZE) 768 769 /* 770 * Hooks for the pool allocator. 771 */ 772 #define POOL_VTOPHYS(va) vtophys((vaddr_t) (va)) 773 774 #ifndef _LOCORE 775 776 /* 777 * pmap-specific data store in the vm_page structure. 778 */ 779 #define __HAVE_VM_PAGE_MD 780 struct vm_page_md { 781 SLIST_HEAD(,pv_entry) pvh_list; /* pv_entry list */ 782 struct simplelock pvh_slock; /* lock on this head */ 783 int pvh_attrs; /* page attributes */ 784 u_int uro_mappings; 785 u_int urw_mappings; 786 union { 787 u_short s_mappings[2]; /* Assume kernel count <= 65535 */ 788 u_int i_mappings; 789 } k_u; 790 #define kro_mappings k_u.s_mappings[0] 791 #define krw_mappings k_u.s_mappings[1] 792 #define k_mappings k_u.i_mappings 793 }; 794 795 /* 796 * Set the default color of each page. 797 */ 798 #if ARM_MMU_V6 > 0 799 #define VM_MDPAGE_PVH_ATTRS_INIT(pg) \ 800 (pg)->mdpage.pvh_attrs = (pg)->phys_addr & arm_cache_prefer_mask 801 #else 802 #define VM_MDPAGE_PVH_ATTRS_INIT(pg) \ 803 (pg)->mdpage.pvh_attrs = 0 804 #endif 805 806 #define VM_MDPAGE_INIT(pg) \ 807 do { \ 808 SLIST_INIT(&(pg)->mdpage.pvh_list); \ 809 simple_lock_init(&(pg)->mdpage.pvh_slock); \ 810 VM_MDPAGE_PVH_ATTRS_INIT(pg); \ 811 (pg)->mdpage.uro_mappings = 0; \ 812 (pg)->mdpage.urw_mappings = 0; \ 813 (pg)->mdpage.k_mappings = 0; \ 814 } while (/*CONSTCOND*/0) 815 816 #endif /* !_LOCORE */ 817 818 #endif /* _KERNEL */ 819 820 #endif /* _ARM32_PMAP_H_ */ 821
Indexes created Thu Oct 30 16:09:53 GMT 2025