pmap.h revision 1.99
1 /* $NetBSD: pmap.h,v 1.99 2011/03/10 07:47:15 bsh Exp $ */ 2 3 /* 4 * Copyright (c) 2002, 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe & Steve C. Woodford for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Copyright (c) 1994,1995 Mark Brinicombe. 40 * All rights reserved. 41 * 42 * Redistribution and use in source and binary forms, with or without 43 * modification, are permitted provided that the following conditions 44 * are met: 45 * 1. Redistributions of source code must retain the above copyright 46 * notice, this list of conditions and the following disclaimer. 47 * 2. Redistributions in binary form must reproduce the above copyright 48 * notice, this list of conditions and the following disclaimer in the 49 * documentation and/or other materials provided with the distribution. 50 * 3. All advertising materials mentioning features or use of this software 51 * must display the following acknowledgement: 52 * This product includes software developed by Mark Brinicombe 53 * 4. The name of the author may not be used to endorse or promote products 54 * derived from this software without specific prior written permission. 55 * 56 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 57 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 58 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 59 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 60 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 61 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 62 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 63 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 64 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 65 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 #ifndef _ARM32_PMAP_H_ 69 #define _ARM32_PMAP_H_ 70 71 #ifdef _KERNEL 72 73 #include <arm/cpuconf.h> 74 #include <arm/arm32/pte.h> 75 #ifndef _LOCORE 76 #if defined(_KERNEL_OPT) 77 #include "opt_arm32_pmap.h" 78 #endif 79 #include <arm/cpufunc.h> 80 #include <uvm/uvm_object.h> 81 #endif 82 83 /* 84 * a pmap describes a processes' 4GB virtual address space. this 85 * virtual address space can be broken up into 4096 1MB regions which 86 * are described by L1 PTEs in the L1 table. 87 * 88 * There is a line drawn at KERNEL_BASE. Everything below that line 89 * changes when the VM context is switched. Everything above that line 90 * is the same no matter which VM context is running. This is achieved 91 * by making the L1 PTEs for those slots above KERNEL_BASE reference 92 * kernel L2 tables. 93 * 94 * The basic layout of the virtual address space thus looks like this: 95 * 96 * 0xffffffff 97 * . 98 * . 99 * . 100 * KERNEL_BASE 101 * -------------------- 102 * . 103 * . 104 * . 105 * 0x00000000 106 */ 107 108 /* 109 * The number of L2 descriptor tables which can be tracked by an l2_dtable. 110 * A bucket size of 16 provides for 16MB of contiguous virtual address 111 * space per l2_dtable. Most processes will, therefore, require only two or 112 * three of these to map their whole working set. 113 */ 114 #define L2_BUCKET_LOG2 4 115 #define L2_BUCKET_SIZE (1 << L2_BUCKET_LOG2) 116 117 /* 118 * Given the above "L2-descriptors-per-l2_dtable" constant, the number 119 * of l2_dtable structures required to track all possible page descriptors 120 * mappable by an L1 translation table is given by the following constants: 121 */ 122 #define L2_LOG2 ((32 - L1_S_SHIFT) - L2_BUCKET_LOG2) 123 #define L2_SIZE (1 << L2_LOG2) 124 125 /* 126 * tell MI code that the cache is virtually-indexed. 127 * ARMv6 is physically-tagged but all others are virtually-tagged. 128 */ 129 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 130 #define PMAP_CACHE_VIPT 131 #else 132 #define PMAP_CACHE_VIVT 133 #endif 134 135 #ifndef _LOCORE 136 137 struct l1_ttable; 138 struct l2_dtable; 139 140 /* 141 * Track cache/tlb occupancy using the following structure 142 */ 143 union pmap_cache_state { 144 struct { 145 union { 146 u_int8_t csu_cache_b[2]; 147 u_int16_t csu_cache; 148 } cs_cache_u; 149 150 union { 151 u_int8_t csu_tlb_b[2]; 152 u_int16_t csu_tlb; 153 } cs_tlb_u; 154 } cs_s; 155 u_int32_t cs_all; 156 }; 157 #define cs_cache_id cs_s.cs_cache_u.csu_cache_b[0] 158 #define cs_cache_d cs_s.cs_cache_u.csu_cache_b[1] 159 #define cs_cache cs_s.cs_cache_u.csu_cache 160 #define cs_tlb_id cs_s.cs_tlb_u.csu_tlb_b[0] 161 #define cs_tlb_d cs_s.cs_tlb_u.csu_tlb_b[1] 162 #define cs_tlb cs_s.cs_tlb_u.csu_tlb 163 164 /* 165 * Assigned to cs_all to force cacheops to work for a particular pmap 166 */ 167 #define PMAP_CACHE_STATE_ALL 0xffffffffu 168 169 /* 170 * This structure is used by machine-dependent code to describe 171 * static mappings of devices, created at bootstrap time. 172 */ 173 struct pmap_devmap { 174 vaddr_t pd_va; /* virtual address */ 175 paddr_t pd_pa; /* physical address */ 176 psize_t pd_size; /* size of region */ 177 vm_prot_t pd_prot; /* protection code */ 178 int pd_cache; /* cache attributes */ 179 }; 180 181 /* 182 * The pmap structure itself 183 */ 184 struct pmap { 185 u_int8_t pm_domain; 186 bool pm_remove_all; 187 bool pm_activated; 188 struct l1_ttable *pm_l1; 189 pd_entry_t *pm_pl1vec; 190 pd_entry_t pm_l1vec; 191 union pmap_cache_state pm_cstate; 192 struct uvm_object pm_obj; 193 #define pm_lock pm_obj.vmobjlock 194 struct l2_dtable *pm_l2[L2_SIZE]; 195 struct pmap_statistics pm_stats; 196 LIST_ENTRY(pmap) pm_list; 197 }; 198 199 /* 200 * Physical / virtual address structure. In a number of places (particularly 201 * during bootstrapping) we need to keep track of the physical and virtual 202 * addresses of various pages 203 */ 204 typedef struct pv_addr { 205 SLIST_ENTRY(pv_addr) pv_list; 206 paddr_t pv_pa; 207 vaddr_t pv_va; 208 vsize_t pv_size; 209 } pv_addr_t; 210 typedef SLIST_HEAD(, pv_addr) pv_addrqh_t; 211 212 extern pv_addrqh_t pmap_freeq; 213 extern pv_addr_t kernelpages; 214 extern pv_addr_t systempage; 215 extern pv_addr_t kernel_l1pt; 216 217 /* 218 * Determine various modes for PTEs (user vs. kernel, cacheable 219 * vs. non-cacheable). 220 */ 221 #define PTE_KERNEL 0 222 #define PTE_USER 1 223 #define PTE_NOCACHE 0 224 #define PTE_CACHE 1 225 #define PTE_PAGETABLE 2 226 227 /* 228 * Flags that indicate attributes of pages or mappings of pages. 229 * 230 * The PVF_MOD and PVF_REF flags are stored in the mdpage for each 231 * page. PVF_WIRED, PVF_WRITE, and PVF_NC are kept in individual 232 * pv_entry's for each page. They live in the same "namespace" so 233 * that we can clear multiple attributes at a time. 234 * 235 * Note the "non-cacheable" flag generally means the page has 236 * multiple mappings in a given address space. 237 */ 238 #define PVF_MOD 0x01 /* page is modified */ 239 #define PVF_REF 0x02 /* page is referenced */ 240 #define PVF_WIRED 0x04 /* mapping is wired */ 241 #define PVF_WRITE 0x08 /* mapping is writable */ 242 #define PVF_EXEC 0x10 /* mapping is executable */ 243 #ifdef PMAP_CACHE_VIVT 244 #define PVF_UNC 0x20 /* mapping is 'user' non-cacheable */ 245 #define PVF_KNC 0x40 /* mapping is 'kernel' non-cacheable */ 246 #define PVF_NC (PVF_UNC|PVF_KNC) 247 #endif 248 #ifdef PMAP_CACHE_VIPT 249 #define PVF_NC 0x20 /* mapping is 'kernel' non-cacheable */ 250 #define PVF_MULTCLR 0x40 /* mapping is multi-colored */ 251 #endif 252 #define PVF_COLORED 0x80 /* page has or had a color */ 253 #define PVF_KENTRY 0x0100 /* page entered via pmap_kenter_pa */ 254 #define PVF_KMPAGE 0x0200 /* page is used for kmem */ 255 #define PVF_DIRTY 0x0400 /* page may have dirty cache lines */ 256 #define PVF_KMOD 0x0800 /* unmanaged page is modified */ 257 #define PVF_KWRITE (PVF_KENTRY|PVF_WRITE) 258 #define PVF_DMOD (PVF_MOD|PVF_KMOD|PVF_KMPAGE) 259 260 /* 261 * Commonly referenced structures 262 */ 263 extern int pmap_debug_level; /* Only exists if PMAP_DEBUG */ 264 265 /* 266 * Macros that we need to export 267 */ 268 #define pmap_resident_count(pmap) ((pmap)->pm_stats.resident_count) 269 #define pmap_wired_count(pmap) ((pmap)->pm_stats.wired_count) 270 271 #define pmap_is_modified(pg) \ 272 (((pg)->mdpage.pvh_attrs & PVF_MOD) != 0) 273 #define pmap_is_referenced(pg) \ 274 (((pg)->mdpage.pvh_attrs & PVF_REF) != 0) 275 #define pmap_is_page_colored_p(md) \ 276 (((md)->pvh_attrs & PVF_COLORED) != 0) 277 278 #define pmap_copy(dp, sp, da, l, sa) /* nothing */ 279 280 #define pmap_phys_address(ppn) (arm_ptob((ppn))) 281 u_int arm32_mmap_flags(paddr_t); 282 #define ARM32_MMAP_WRITECOMBINE 0x40000000 283 #define ARM32_MMAP_CACHEABLE 0x20000000 284 #define pmap_mmap_flags(ppn) arm32_mmap_flags(ppn) 285 286 /* 287 * Functions that we need to export 288 */ 289 void pmap_procwr(struct proc *, vaddr_t, int); 290 void pmap_remove_all(pmap_t); 291 bool pmap_extract(pmap_t, vaddr_t, paddr_t *); 292 293 #define PMAP_NEED_PROCWR 294 #define PMAP_GROWKERNEL /* turn on pmap_growkernel interface */ 295 #define PMAP_ENABLE_PMAP_KMPAGE /* enable the PMAP_KMPAGE flag */ 296 297 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 298 #define PMAP_PREFER(hint, vap, sz, td) pmap_prefer((hint), (vap), (td)) 299 void pmap_prefer(vaddr_t, vaddr_t *, int); 300 #endif 301 302 void pmap_icache_sync_range(pmap_t, vaddr_t, vaddr_t); 303 304 /* Functions we use internally. */ 305 #ifdef PMAP_STEAL_MEMORY 306 void pmap_boot_pagealloc(psize_t, psize_t, psize_t, pv_addr_t *); 307 void pmap_boot_pageadd(pv_addr_t *); 308 vaddr_t pmap_steal_memory(vsize_t, vaddr_t *, vaddr_t *); 309 #endif 310 void pmap_bootstrap(vaddr_t, vaddr_t); 311 312 void pmap_do_remove(pmap_t, vaddr_t, vaddr_t, int); 313 int pmap_fault_fixup(pmap_t, vaddr_t, vm_prot_t, int); 314 bool pmap_get_pde_pte(pmap_t, vaddr_t, pd_entry_t **, pt_entry_t **); 315 bool pmap_get_pde(pmap_t, vaddr_t, pd_entry_t **); 316 void pmap_set_pcb_pagedir(pmap_t, struct pcb *); 317 318 void pmap_debug(int); 319 void pmap_postinit(void); 320 321 void vector_page_setprot(int); 322 323 const struct pmap_devmap *pmap_devmap_find_pa(paddr_t, psize_t); 324 const struct pmap_devmap *pmap_devmap_find_va(vaddr_t, vsize_t); 325 326 /* Bootstrapping routines. */ 327 void pmap_map_section(vaddr_t, vaddr_t, paddr_t, int, int); 328 void pmap_map_entry(vaddr_t, vaddr_t, paddr_t, int, int); 329 vsize_t pmap_map_chunk(vaddr_t, vaddr_t, paddr_t, vsize_t, int, int); 330 void pmap_link_l2pt(vaddr_t, vaddr_t, pv_addr_t *); 331 void pmap_devmap_bootstrap(vaddr_t, const struct pmap_devmap *); 332 void pmap_devmap_register(const struct pmap_devmap *); 333 334 /* 335 * Special page zero routine for use by the idle loop (no cache cleans). 336 */ 337 bool pmap_pageidlezero(paddr_t); 338 #define PMAP_PAGEIDLEZERO(pa) pmap_pageidlezero((pa)) 339 340 /* 341 * used by dumpsys to record the PA of the L1 table 342 */ 343 uint32_t pmap_kernel_L1_addr(void); 344 /* 345 * The current top of kernel VM 346 */ 347 extern vaddr_t pmap_curmaxkvaddr; 348 349 /* 350 * Useful macros and constants 351 */ 352 353 /* Virtual address to page table entry */ 354 static inline pt_entry_t * 355 vtopte(vaddr_t va) 356 { 357 pd_entry_t *pdep; 358 pt_entry_t *ptep; 359 360 if (pmap_get_pde_pte(pmap_kernel(), va, &pdep, &ptep) == false) 361 return (NULL); 362 return (ptep); 363 } 364 365 /* 366 * Virtual address to physical address 367 */ 368 static inline paddr_t 369 vtophys(vaddr_t va) 370 { 371 paddr_t pa; 372 373 if (pmap_extract(pmap_kernel(), va, &pa) == false) 374 return (0); /* XXXSCW: Panic? */ 375 376 return (pa); 377 } 378 379 /* 380 * The new pmap ensures that page-tables are always mapping Write-Thru. 381 * Thus, on some platforms we can run fast and loose and avoid syncing PTEs 382 * on every change. 383 * 384 * Unfortunately, not all CPUs have a write-through cache mode. So we 385 * define PMAP_NEEDS_PTE_SYNC for C code to conditionally do PTE syncs, 386 * and if there is the chance for PTE syncs to be needed, we define 387 * PMAP_INCLUDE_PTE_SYNC so e.g. assembly code can include (and run) 388 * the code. 389 */ 390 extern int pmap_needs_pte_sync; 391 #if defined(_KERNEL_OPT) 392 /* 393 * StrongARM SA-1 caches do not have a write-through mode. So, on these, 394 * we need to do PTE syncs. If only SA-1 is configured, then evaluate 395 * this at compile time. 396 */ 397 #if (ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7 != 0) && (ARM_NMMUS == 1) 398 #define PMAP_NEEDS_PTE_SYNC 1 399 #define PMAP_INCLUDE_PTE_SYNC 400 #elif (ARM_MMU_SA1 == 0) 401 #define PMAP_NEEDS_PTE_SYNC 0 402 #endif 403 #endif /* _KERNEL_OPT */ 404 405 /* 406 * Provide a fallback in case we were not able to determine it at 407 * compile-time. 408 */ 409 #ifndef PMAP_NEEDS_PTE_SYNC 410 #define PMAP_NEEDS_PTE_SYNC pmap_needs_pte_sync 411 #define PMAP_INCLUDE_PTE_SYNC 412 #endif 413 414 #define PTE_SYNC(pte) \ 415 do { \ 416 if (PMAP_NEEDS_PTE_SYNC) \ 417 cpu_dcache_wb_range((vaddr_t)(pte), sizeof(pt_entry_t));\ 418 } while (/*CONSTCOND*/0) 419 420 #define PTE_SYNC_RANGE(pte, cnt) \ 421 do { \ 422 if (PMAP_NEEDS_PTE_SYNC) { \ 423 cpu_dcache_wb_range((vaddr_t)(pte), \ 424 (cnt) << 2); /* * sizeof(pt_entry_t) */ \ 425 } \ 426 } while (/*CONSTCOND*/0) 427 428 #define l1pte_valid(pde) ((pde) != 0) 429 #define l1pte_section_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_S) 430 #define l1pte_page_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_C) 431 #define l1pte_fpage_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_F) 432 433 #define l2pte_index(v) (((v) & L2_ADDR_BITS) >> L2_S_SHIFT) 434 #define l2pte_valid(pte) (((pte) & L2_TYPE_MASK) != L2_TYPE_INV) 435 #define l2pte_pa(pte) ((pte) & L2_S_FRAME) 436 #define l2pte_minidata(pte) (((pte) & \ 437 (L2_B | L2_C | L2_XS_T_TEX(TEX_XSCALE_X)))\ 438 == (L2_C | L2_XS_T_TEX(TEX_XSCALE_X))) 439 440 /* L1 and L2 page table macros */ 441 #define pmap_pde_v(pde) l1pte_valid(*(pde)) 442 #define pmap_pde_section(pde) l1pte_section_p(*(pde)) 443 #define pmap_pde_page(pde) l1pte_page_p(*(pde)) 444 #define pmap_pde_fpage(pde) l1pte_fpage_p(*(pde)) 445 446 #define pmap_pte_v(pte) l2pte_valid(*(pte)) 447 #define pmap_pte_pa(pte) l2pte_pa(*(pte)) 448 449 /* Size of the kernel part of the L1 page table */ 450 #define KERNEL_PD_SIZE \ 451 (L1_TABLE_SIZE - (KERNEL_BASE >> L1_S_SHIFT) * sizeof(pd_entry_t)) 452 453 /************************* ARM MMU configuration *****************************/ 454 455 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0 456 void pmap_copy_page_generic(paddr_t, paddr_t); 457 void pmap_zero_page_generic(paddr_t); 458 459 void pmap_pte_init_generic(void); 460 #if defined(CPU_ARM8) 461 void pmap_pte_init_arm8(void); 462 #endif 463 #if defined(CPU_ARM9) 464 void pmap_pte_init_arm9(void); 465 #endif /* CPU_ARM9 */ 466 #if defined(CPU_ARM10) 467 void pmap_pte_init_arm10(void); 468 #endif /* CPU_ARM10 */ 469 #if defined(CPU_ARM11) 470 void pmap_pte_init_arm11(void); 471 #endif /* CPU_ARM11 */ 472 #if defined(CPU_ARM11MPCORE) 473 void pmap_pte_init_arm11mpcore(void); 474 #endif 475 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */ 476 477 #if ARM_MMU_SA1 == 1 478 void pmap_pte_init_sa1(void); 479 #endif /* ARM_MMU_SA1 == 1 */ 480 481 #if ARM_MMU_XSCALE == 1 482 void pmap_copy_page_xscale(paddr_t, paddr_t); 483 void pmap_zero_page_xscale(paddr_t); 484 485 void pmap_pte_init_xscale(void); 486 487 void xscale_setup_minidata(vaddr_t, vaddr_t, paddr_t); 488 489 #define PMAP_UAREA(va) pmap_uarea(va) 490 void pmap_uarea(vaddr_t); 491 #endif /* ARM_MMU_XSCALE == 1 */ 492 493 #if ARM_MMU_V7 == 1 494 void pmap_pte_init_armv7(void); 495 #endif /* ARM_MMU_V7 */ 496 497 extern pt_entry_t pte_l1_s_cache_mode; 498 extern pt_entry_t pte_l1_s_cache_mask; 499 500 extern pt_entry_t pte_l2_l_cache_mode; 501 extern pt_entry_t pte_l2_l_cache_mask; 502 503 extern pt_entry_t pte_l2_s_cache_mode; 504 extern pt_entry_t pte_l2_s_cache_mask; 505 506 extern pt_entry_t pte_l1_s_cache_mode_pt; 507 extern pt_entry_t pte_l2_l_cache_mode_pt; 508 extern pt_entry_t pte_l2_s_cache_mode_pt; 509 510 extern pt_entry_t pte_l1_s_wc_mode; 511 extern pt_entry_t pte_l2_l_wc_mode; 512 extern pt_entry_t pte_l2_s_wc_mode; 513 514 extern pt_entry_t pte_l1_s_prot_u; 515 extern pt_entry_t pte_l1_s_prot_w; 516 extern pt_entry_t pte_l1_s_prot_ro; 517 extern pt_entry_t pte_l1_s_prot_mask; 518 519 extern pt_entry_t pte_l2_s_prot_u; 520 extern pt_entry_t pte_l2_s_prot_w; 521 extern pt_entry_t pte_l2_s_prot_ro; 522 extern pt_entry_t pte_l2_s_prot_mask; 523 524 extern pt_entry_t pte_l2_l_prot_u; 525 extern pt_entry_t pte_l2_l_prot_w; 526 extern pt_entry_t pte_l2_l_prot_ro; 527 extern pt_entry_t pte_l2_l_prot_mask; 528 529 extern pt_entry_t pte_l1_s_proto; 530 extern pt_entry_t pte_l1_c_proto; 531 extern pt_entry_t pte_l2_s_proto; 532 533 extern void (*pmap_copy_page_func)(paddr_t, paddr_t); 534 extern void (*pmap_zero_page_func)(paddr_t); 535 536 #endif /* !_LOCORE */ 537 538 /*****************************************************************************/ 539 540 /* 541 * Definitions for MMU domains 542 */ 543 #define PMAP_DOMAINS 15 /* 15 'user' domains (0-14) */ 544 #define PMAP_DOMAIN_KERNEL 15 /* The kernel uses domain #15 */ 545 546 /* 547 * These macros define the various bit masks in the PTE. 548 * 549 * We use these macros since we use different bits on different processor 550 * models. 551 */ 552 #define L1_S_PROT_U_generic (L1_S_AP(AP_U)) 553 #define L1_S_PROT_W_generic (L1_S_AP(AP_W)) 554 #define L1_S_PROT_RO_generic (0) 555 #define L1_S_PROT_MASK_generic (L1_S_PROT_U|L1_S_PROT_W|L1_S_PROT_RO) 556 557 #define L1_S_PROT_U_xscale (L1_S_AP(AP_U)) 558 #define L1_S_PROT_W_xscale (L1_S_AP(AP_W)) 559 #define L1_S_PROT_RO_xscale (0) 560 #define L1_S_PROT_MASK_xscale (L1_S_PROT_U|L1_S_PROT_W|L1_S_PROT_RO) 561 562 #define L1_S_PROT_U_armv6 (L1_S_AP(AP_R) | L1_S_AP(AP_U)) 563 #define L1_S_PROT_W_armv6 (L1_S_AP(AP_W)) 564 #define L1_S_PROT_RO_armv6 (L1_S_AP(AP_R) | L1_S_AP(AP_RO)) 565 #define L1_S_PROT_MASK_armv6 (L1_S_PROT_U|L1_S_PROT_W|L1_S_PROT_RO) 566 567 #define L1_S_PROT_U_armv7 (L1_S_AP(AP_R) | L1_S_AP(AP_U)) 568 #define L1_S_PROT_W_armv7 (L1_S_AP(AP_W)) 569 #define L1_S_PROT_RO_armv7 (L1_S_AP(AP_R) | L1_S_AP(AP_RO)) 570 #define L1_S_PROT_MASK_armv7 (L1_S_PROT_U|L1_S_PROT_W|L1_S_PROT_RO) 571 572 #define L1_S_CACHE_MASK_generic (L1_S_B|L1_S_C) 573 #define L1_S_CACHE_MASK_xscale (L1_S_B|L1_S_C|L1_S_XS_TEX(TEX_XSCALE_X)) 574 #define L1_S_CACHE_MASK_armv6 (L1_S_B|L1_S_C|L1_S_XS_TEX(TEX_ARMV6_TEX)) 575 #define L1_S_CACHE_MASK_armv7 (L1_S_B|L1_S_C) 576 577 #define L2_L_PROT_U_generic (L2_AP(AP_U)) 578 #define L2_L_PROT_W_generic (L2_AP(AP_W)) 579 #define L2_L_PROT_RO_generic (0) 580 #define L2_L_PROT_MASK_generic (L2_L_PROT_U|L2_L_PROT_W|L2_L_PROT_RO) 581 582 #define L2_L_PROT_U_xscale (L2_AP(AP_U)) 583 #define L2_L_PROT_W_xscale (L2_AP(AP_W)) 584 #define L2_L_PROT_RO_xscale (0) 585 #define L2_L_PROT_MASK_xscale (L2_L_PROT_U|L2_L_PROT_W|L2_L_PROT_RO) 586 587 #define L2_L_PROT_U_armv6n (L2_AP0(AP_R) | L2_AP0(AP_U)) 588 #define L2_L_PROT_W_armv6n (L2_AP0(AP_W)) 589 #define L2_L_PROT_RO_armv6n (L2_AP0(AP_R) | L2_AP0(AP_RO)) 590 #define L2_L_PROT_MASK_armv6n (L2_L_PROT_U|L2_L_PROT_W|L2_L_PROT_RO) 591 592 #define L2_L_PROT_U_armv7 (L2_AP0(AP_R) | L2_AP0(AP_U)) 593 #define L2_L_PROT_W_armv7 (L2_AP0(AP_W)) 594 #define L2_L_PROT_RO_armv7 (L2_AP0(AP_R) | L2_AP0(AP_RO)) 595 #define L2_L_PROT_MASK_armv7 (L2_L_PROT_U|L2_L_PROT_W|L2_L_PROT_RO) 596 597 #define L2_L_CACHE_MASK_generic (L2_B|L2_C) 598 #define L2_L_CACHE_MASK_xscale (L2_B|L2_C|L2_XS_L_TEX(TEX_XSCALE_X)) 599 #define L2_L_CACHE_MASK_armv6 (L2_B|L2_C|L2_V6_L_TEX(TEX_ARMV6_TEX)) 600 #define L2_L_CACHE_MASK_armv7 (L2_B|L2_C) 601 602 #define L2_S_PROT_U_generic (L2_AP(AP_U)) 603 #define L2_S_PROT_W_generic (L2_AP(AP_W)) 604 #define L2_S_PROT_RO_generic (0) 605 #define L2_S_PROT_MASK_generic (L2_S_PROT_U|L2_S_PROT_W|L2_S_PROT_RO) 606 607 #define L2_S_PROT_U_xscale (L2_AP0(AP_U)) 608 #define L2_S_PROT_W_xscale (L2_AP0(AP_W)) 609 #define L2_S_PROT_RO_xscale (0) 610 #define L2_S_PROT_MASK_xscale (L2_S_PROT_U|L2_S_PROT_W|L2_S_PROT_RO) 611 612 #define L2_S_PROT_U_armv6n (L2_AP0(AP_R) | L2_AP0(AP_U)) 613 #define L2_S_PROT_W_armv6n (L2_AP0(AP_W)) 614 #define L2_S_PROT_RO_armv6n (L2_AP0(AP_R) | L2_AP0(AP_RO)) 615 #define L2_S_PROT_MASK_armv6n (L2_S_PROT_U|L2_S_PROT_W|L2_S_PROT_RO) 616 617 #define L2_S_PROT_U_armv7 (L2_AP0(AP_R) | L2_AP0(AP_U)) 618 #define L2_S_PROT_W_armv7 (L2_AP0(AP_W)) 619 #define L2_S_PROT_RO_armv7 (L2_AP0(AP_R) | L2_AP0(AP_RO)) 620 #define L2_S_PROT_MASK_armv7 (L2_S_PROT_U|L2_S_PROT_W|L2_S_PROT_RO) 621 622 #define L2_S_CACHE_MASK_generic (L2_B|L2_C) 623 #define L2_S_CACHE_MASK_xscale (L2_B|L2_C|L2_XS_T_TEX(TEX_XSCALE_X)) 624 #define L2_XS_CACHE_MASK_armv6 (L2_B|L2_C|L2_V6_XS_TEX(TEX_ARMV6_TEX)) 625 #define L2_S_CACHE_MASK_armv6n L2_XS_CACHE_MASK_armv6 626 #ifdef ARMV6_EXTENDED_SMALL_PAGE 627 #define L2_S_CACHE_MASK_armv6c L2_XS_CACHE_MASK_armv6 628 #else 629 #define L2_S_CACHE_MASK_armv6c L2_S_CACHE_MASK_generic 630 #endif 631 #define L2_S_CACHE_MASK_armv7 (L2_B|L2_C) 632 633 634 #define L1_S_PROTO_generic (L1_TYPE_S | L1_S_IMP) 635 #define L1_S_PROTO_xscale (L1_TYPE_S) 636 #define L1_S_PROTO_armv6 (L1_TYPE_S) 637 #define L1_S_PROTO_armv7 (L1_TYPE_S) 638 639 #define L1_C_PROTO_generic (L1_TYPE_C | L1_C_IMP2) 640 #define L1_C_PROTO_xscale (L1_TYPE_C) 641 #define L1_C_PROTO_armv6 (L1_TYPE_C) 642 #define L1_C_PROTO_armv7 (L1_TYPE_C) 643 644 #define L2_L_PROTO (L2_TYPE_L) 645 646 #define L2_S_PROTO_generic (L2_TYPE_S) 647 #define L2_S_PROTO_xscale (L2_TYPE_XS) 648 #ifdef ARMV6_EXTENDED_SMALL_PAGE 649 #define L2_S_PROTO_armv6c (L2_TYPE_XS) /* XP=0, extended small page */ 650 #else 651 #define L2_S_PROTO_armv6c (L2_TYPE_S) /* XP=0, subpage APs */ 652 #endif 653 #define L2_S_PROTO_armv6n (L2_TYPE_S) /* with XP=1 */ 654 #define L2_S_PROTO_armv7 (L2_TYPE_S) 655 656 /* 657 * User-visible names for the ones that vary with MMU class. 658 */ 659 660 #if ARM_NMMUS > 1 661 /* More than one MMU class configured; use variables. */ 662 #define L1_S_PROT_U pte_l1_s_prot_u 663 #define L1_S_PROT_W pte_l1_s_prot_w 664 #define L1_S_PROT_RO pte_l1_s_prot_ro 665 #define L1_S_PROT_MASK pte_l1_s_prot_mask 666 667 #define L2_S_PROT_U pte_l2_s_prot_u 668 #define L2_S_PROT_W pte_l2_s_prot_w 669 #define L2_S_PROT_RO pte_l2_s_prot_ro 670 #define L2_S_PROT_MASK pte_l2_s_prot_mask 671 672 #define L2_L_PROT_U pte_l2_l_prot_u 673 #define L2_L_PROT_W pte_l2_l_prot_w 674 #define L2_L_PROT_RO pte_l2_l_prot_ro 675 #define L2_L_PROT_MASK pte_l2_l_prot_mask 676 677 #define L1_S_CACHE_MASK pte_l1_s_cache_mask 678 #define L2_L_CACHE_MASK pte_l2_l_cache_mask 679 #define L2_S_CACHE_MASK pte_l2_s_cache_mask 680 681 #define L1_S_PROTO pte_l1_s_proto 682 #define L1_C_PROTO pte_l1_c_proto 683 #define L2_S_PROTO pte_l2_s_proto 684 685 #define pmap_copy_page(s, d) (*pmap_copy_page_func)((s), (d)) 686 #define pmap_zero_page(d) (*pmap_zero_page_func)((d)) 687 #elif (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 688 #define L1_S_PROT_U L1_S_PROT_U_generic 689 #define L1_S_PROT_W L1_S_PROT_W_generic 690 #define L1_S_PROT_RO L1_S_PROT_RO_generic 691 #define L1_S_PROT_MASK L1_S_PROT_MASK_generic 692 693 #define L2_S_PROT_U L2_S_PROT_U_generic 694 #define L2_S_PROT_W L2_S_PROT_W_generic 695 #define L2_S_PROT_RO L2_S_PROT_RO_generic 696 #define L2_S_PROT_MASK L2_S_PROT_MASK_generic 697 698 #define L2_L_PROT_U L2_L_PROT_U_generic 699 #define L2_L_PROT_W L2_L_PROT_W_generic 700 #define L2_L_PROT_RO L2_L_PROT_RO_generic 701 #define L2_L_PROT_MASK L2_L_PROT_MASK_generic 702 703 #define L1_S_CACHE_MASK L1_S_CACHE_MASK_generic 704 #define L2_L_CACHE_MASK L2_L_CACHE_MASK_generic 705 #define L2_S_CACHE_MASK L2_S_CACHE_MASK_generic 706 707 #define L1_S_PROTO L1_S_PROTO_generic 708 #define L1_C_PROTO L1_C_PROTO_generic 709 #define L2_S_PROTO L2_S_PROTO_generic 710 711 #define pmap_copy_page(s, d) pmap_copy_page_generic((s), (d)) 712 #define pmap_zero_page(d) pmap_zero_page_generic((d)) 713 #elif ARM_MMU_V6N != 0 714 #define L1_S_PROT_U L1_S_PROT_U_armv6 715 #define L1_S_PROT_W L1_S_PROT_W_armv6 716 #define L1_S_PROT_RO L1_S_PROT_RO_armv6 717 #define L1_S_PROT_MASK L1_S_PROT_MASK_armv6 718 719 #define L2_S_PROT_U L2_S_PROT_U_armv6n 720 #define L2_S_PROT_W L2_S_PROT_W_armv6n 721 #define L2_S_PROT_RO L2_S_PROT_RO_armv6n 722 #define L2_S_PROT_MASK L2_S_PROT_MASK_armv6n 723 724 #define L2_L_PROT_U L2_L_PROT_U_armv6n 725 #define L2_L_PROT_W L2_L_PROT_W_armv6n 726 #define L2_L_PROT_RO L2_L_PROT_RO_armv6n 727 #define L2_L_PROT_MASK L2_L_PROT_MASK_armv6n 728 729 #define L1_S_CACHE_MASK L1_S_CACHE_MASK_armv6 730 #define L2_L_CACHE_MASK L2_L_CACHE_MASK_armv6 731 #define L2_S_CACHE_MASK L2_S_CACHE_MASK_armv6n 732 733 /* These prototypes make writeable mappings, while the other MMU types 734 * make read-only mappings. */ 735 #define L1_S_PROTO L1_S_PROTO_armv6 736 #define L1_C_PROTO L1_C_PROTO_armv6 737 #define L2_S_PROTO L2_S_PROTO_armv6n 738 739 #define pmap_copy_page(s, d) pmap_copy_page_generic((s), (d)) 740 #define pmap_zero_page(d) pmap_zero_page_generic((d)) 741 #elif ARM_MMU_V6C != 0 742 #define L1_S_PROT_U L1_S_PROT_U_generic 743 #define L1_S_PROT_W L1_S_PROT_W_generic 744 #define L1_S_PROT_RO L1_S_PROT_RO_generic 745 #define L1_S_PROT_MASK L1_S_PROT_MASK_generic 746 747 #define L2_S_PROT_U L2_S_PROT_U_generic 748 #define L2_S_PROT_W L2_S_PROT_W_generic 749 #define L2_S_PROT_RO L2_S_PROT_RO_generic 750 #define L2_S_PROT_MASK L2_S_PROT_MASK_generic 751 752 #define L2_L_PROT_U L2_L_PROT_U_generic 753 #define L2_L_PROT_W L2_L_PROT_W_generic 754 #define L2_L_PROT_RO L2_L_PROT_RO_generic 755 #define L2_L_PROT_MASK L2_L_PROT_MASK_generic 756 757 #define L1_S_CACHE_MASK L1_S_CACHE_MASK_generic 758 #define L2_L_CACHE_MASK L2_L_CACHE_MASK_generic 759 #define L2_S_CACHE_MASK L2_S_CACHE_MASK_generic 760 761 #define L1_S_PROTO L1_S_PROTO_generic 762 #define L1_C_PROTO L1_C_PROTO_generic 763 #define L2_S_PROTO L2_S_PROTO_generic 764 765 #define pmap_copy_page(s, d) pmap_copy_page_generic((s), (d)) 766 #define pmap_zero_page(d) pmap_zero_page_generic((d)) 767 #elif ARM_MMU_XSCALE == 1 768 #define L1_S_PROT_U L1_S_PROT_U_generic 769 #define L1_S_PROT_W L1_S_PROT_W_generic 770 #define L1_S_PROT_RO L1_S_PROT_RO_generic 771 #define L1_S_PROT_MASK L1_S_PROT_MASK_generic 772 773 #define L2_S_PROT_U L2_S_PROT_U_xscale 774 #define L2_S_PROT_W L2_S_PROT_W_xscale 775 #define L2_S_PROT_RO L2_S_PROT_RO_xscale 776 #define L2_S_PROT_MASK L2_S_PROT_MASK_xscale 777 778 #define L2_L_PROT_U L2_L_PROT_U_generic 779 #define L2_L_PROT_W L2_L_PROT_W_generic 780 #define L2_L_PROT_RO L2_L_PROT_RO_generic 781 #define L2_L_PROT_MASK L2_L_PROT_MASK_generic 782 783 #define L1_S_CACHE_MASK L1_S_CACHE_MASK_xscale 784 #define L2_L_CACHE_MASK L2_L_CACHE_MASK_xscale 785 #define L2_S_CACHE_MASK L2_S_CACHE_MASK_xscale 786 787 #define L1_S_PROTO L1_S_PROTO_xscale 788 #define L1_C_PROTO L1_C_PROTO_xscale 789 #define L2_S_PROTO L2_S_PROTO_xscale 790 791 #define pmap_copy_page(s, d) pmap_copy_page_xscale((s), (d)) 792 #define pmap_zero_page(d) pmap_zero_page_xscale((d)) 793 #elif ARM_MMU_V7 == 1 794 #define L1_S_PROT_U L1_S_PROT_U_armv7 795 #define L1_S_PROT_W L1_S_PROT_W_armv7 796 #define L1_S_PROT_RO L1_S_PROT_RO_armv7 797 #define L1_S_PROT_MASK L1_S_PROT_MASK_armv7 798 799 #define L2_S_PROT_U L2_S_PROT_U_armv7 800 #define L2_S_PROT_W L2_S_PROT_W_armv7 801 #define L2_S_PROT_RO L2_S_PROT_RO_armv7 802 #define L2_S_PROT_MASK L2_S_PROT_MASK_armv7 803 804 #define L2_L_PROT_U L2_L_PROT_U_armv7 805 #define L2_L_PROT_W L2_L_PROT_W_armv7 806 #define L2_L_PROT_RO L2_L_PROT_RO_armv7 807 #define L2_L_PROT_MASK L2_L_PROT_MASK_armv7 808 809 #define L1_S_CACHE_MASK L1_S_CACHE_MASK_armv7 810 #define L2_L_CACHE_MASK L2_L_CACHE_MASK_armv7 811 #define L2_S_CACHE_MASK L2_S_CACHE_MASK_armv7 812 813 /* These prototypes make writeable mappings, while the other MMU types 814 * make read-only mappings. */ 815 #define L1_S_PROTO L1_S_PROTO_armv7 816 #define L1_C_PROTO L1_C_PROTO_armv7 817 #define L2_S_PROTO L2_S_PROTO_armv7 818 819 #define pmap_copy_page(s, d) pmap_copy_page_generic((s), (d)) 820 #define pmap_zero_page(d) pmap_zero_page_generic((d)) 821 #endif /* ARM_NMMUS > 1 */ 822 823 /* 824 * Macros to set and query the write permission on page descriptors. 825 */ 826 #define l1pte_set_writable(pte) (((pte) & ~L1_S_PROT_RO) | L1_S_PROT_W) 827 #define l1pte_set_readonly(pte) (((pte) & ~L1_S_PROT_W) | L1_S_PROT_RO) 828 #define l2pte_set_writable(pte) (((pte) & ~L2_S_PROT_RO) | L2_S_PROT_W) 829 #define l2pte_set_readonly(pte) (((pte) & ~L2_S_PROT_W) | L2_S_PROT_RO) 830 831 #define l2pte_writable_p(pte) (((pte) & L2_S_PROT_W) == L2_S_PROT_W && \ 832 (L2_S_PROT_RO == 0 || \ 833 ((pte) & L2_S_PROT_RO) != L2_S_PROT_RO)) 834 835 /* 836 * These macros return various bits based on kernel/user and protection. 837 * Note that the compiler will usually fold these at compile time. 838 */ 839 #define L1_S_PROT(ku, pr) ((((ku) == PTE_USER) ? L1_S_PROT_U : 0) | \ 840 (((pr) & VM_PROT_WRITE) ? L1_S_PROT_W : L1_S_PROT_RO)) 841 842 #define L2_L_PROT(ku, pr) ((((ku) == PTE_USER) ? L2_L_PROT_U : 0) | \ 843 (((pr) & VM_PROT_WRITE) ? L2_L_PROT_W : L2_L_PROT_RO)) 844 845 #define L2_S_PROT(ku, pr) ((((ku) == PTE_USER) ? L2_S_PROT_U : 0) | \ 846 (((pr) & VM_PROT_WRITE) ? L2_S_PROT_W : L2_S_PROT_RO)) 847 848 /* 849 * Macros to test if a mapping is mappable with an L1 Section mapping 850 * or an L2 Large Page mapping. 851 */ 852 #define L1_S_MAPPABLE_P(va, pa, size) \ 853 ((((va) | (pa)) & L1_S_OFFSET) == 0 && (size) >= L1_S_SIZE) 854 855 #define L2_L_MAPPABLE_P(va, pa, size) \ 856 ((((va) | (pa)) & L2_L_OFFSET) == 0 && (size) >= L2_L_SIZE) 857 858 /* 859 * Hooks for the pool allocator. 860 */ 861 #define POOL_VTOPHYS(va) vtophys((vaddr_t) (va)) 862 863 #ifndef _LOCORE 864 865 /* 866 * pmap-specific data store in the vm_page structure. 867 */ 868 #define __HAVE_VM_PAGE_MD 869 struct vm_page_md { 870 SLIST_HEAD(,pv_entry) pvh_list; /* pv_entry list */ 871 struct simplelock pvh_slock; /* lock on this head */ 872 int pvh_attrs; /* page attributes */ 873 u_int uro_mappings; 874 u_int urw_mappings; 875 union { 876 u_short s_mappings[2]; /* Assume kernel count <= 65535 */ 877 u_int i_mappings; 878 } k_u; 879 #define kro_mappings k_u.s_mappings[0] 880 #define krw_mappings k_u.s_mappings[1] 881 #define k_mappings k_u.i_mappings 882 }; 883 884 /* 885 * Set the default color of each page. 886 */ 887 #if ARM_MMU_V6 > 0 888 #define VM_MDPAGE_PVH_ATTRS_INIT(pg) \ 889 (pg)->mdpage.pvh_attrs = (pg)->phys_addr & arm_cache_prefer_mask 890 #else 891 #define VM_MDPAGE_PVH_ATTRS_INIT(pg) \ 892 (pg)->mdpage.pvh_attrs = 0 893 #endif 894 895 #define VM_MDPAGE_INIT(pg) \ 896 do { \ 897 SLIST_INIT(&(pg)->mdpage.pvh_list); \ 898 simple_lock_init(&(pg)->mdpage.pvh_slock); \ 899 VM_MDPAGE_PVH_ATTRS_INIT(pg); \ 900 (pg)->mdpage.uro_mappings = 0; \ 901 (pg)->mdpage.urw_mappings = 0; \ 902 (pg)->mdpage.k_mappings = 0; \ 903 } while (/*CONSTCOND*/0) 904 905 #endif /* !_LOCORE */ 906 907 #endif /* _KERNEL */ 908 909 #endif /* _ARM32_PMAP_H_ */ 910
Indexes created Mon Sep 29 21:09:56 GMT 2025