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pte.h revision 1.1 
      1 /*	$NetBSD: pte.h,v 1.1 2001/11/23 17:39:04 thorpej Exp $	*/
      2 
      3 /*
      4  * Copyright (c) 1994 Mark Brinicombe.
      5  * All rights reserved.
      6  *
      7  * Redistribution and use in source and binary forms, with or without
      8  * modification, are permitted provided that the following conditions
      9  * are met:
     10  * 1. Redistributions of source code must retain the above copyright
     11  *    notice, this list of conditions and the following disclaimer.
     12  * 2. Redistributions in binary form must reproduce the above copyright
     13  *    notice, this list of conditions and the following disclaimer in the
     14  *    documentation and/or other materials provided with the distribution.
     15  * 3. All advertising materials mentioning features or use of this software
     16  *    must display the following acknowledgement:
     17  *	This product includes software developed by the RiscBSD team.
     18  * 4. The name "RiscBSD" nor the name of the author may be used to
     19  *    endorse or promote products derived from this software without specific
     20  *    prior written permission.
     21  *
     22  * THIS SOFTWARE IS PROVIDED BY RISCBSD ``AS IS'' AND ANY EXPRESS OR IMPLIED
     23  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
     24  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     25  * IN NO EVENT SHALL RISCBSD OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
     26  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
     27  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
     28  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     29  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     30  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     31  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     32  * SUCH DAMAGE.
     33  */
     34 
     35 #ifndef _ARM32_PTE_H_
     36 #define _ARM32_PTE_H_
     37 
     38 #define PDSHIFT		20		/* LOG2(NBPDR) */
     39 #define NBPD		(1 << PDSHIFT)	/* bytes/page dir */
     40 #define NPTEPD		(NBPD / NBPG)
     41 
     42 #ifndef _LOCORE
     43 typedef	int	pd_entry_t;		/* page directory entry */
     44 typedef	int	pt_entry_t;		/* page table entry */
     45 #endif
     46 
     47 #define PD_MASK		0xfff00000	/* page directory address bits */
     48 #define PT_MASK		0x000ff000	/* page table address bits */
     49 
     50 #define PG_FRAME	0xfffff000
     51 
     52 /* The PT_SIZE definition is misleading... A page table is only 0x400
     53  * bytes long. But since VM mapping can only be done to 0x1000 a single
     54  * 1KB blocks cannot be steered to a va by itself. Therefore the
     55  * pages tables are allocated in blocks of 4. i.e. if a 1 KB block
     56  * was allocated for a PT then the other 3KB would also get mapped
     57  * whenever the 1KB was mapped.
     58  */
     59 
     60 #define PT_SIZE		0x1000
     61 #define PD_SIZE		0x4000
     62 
     63 /* Access permissions for L1 sections and L2 pages */
     64 #define AP_KR		0x00
     65 #define AP_KRW		0x01
     66 #define AP_KRWUR	0x02
     67 #define AP_KRWURW	0x03
     68 
     69 #define AP_W		0x01
     70 #define AP_U		0x02
     71 
     72 /* Physical bits in a pte */
     73 #define PT_B		0x04	/* Phys - Buffered (write) */
     74 #define PT_C		0x08	/* Phys - Cacheable */
     75 #define PT_U		0x10	/* Phys - Updateable */
     76 
     77 #ifndef _LOCORE
     78 extern pt_entry_t	pte_cache_mode;
     79 
     80 #define PT_CACHEABLE	(pte_cache_mode)
     81 #endif
     82 
     83 /* Page R/M attributes (in pmseg.attrs). */
     84 #define PT_M		0x01	/* Virt - Modified */
     85 #define PT_H		0x02	/* Virt - Handled (Used) */
     86 /* Mapping wired/writeable/cacheable attributes (in pv_flags). */
     87 #define PT_W		0x04	/* Virt - Wired */
     88 #define PT_Wr		0x08	/* Virt / Phys Write */
     89 #define PT_NC		0x10	/* Cacheing disabled (multi-mapped page) */
     90 
     91 /* access permissions for L2 pages (all sub pages have the same perms) */
     92 #define PT_AP(x)	((x << 10) | (x << 8) | (x << 6)  | (x << 4))
     93 
     94 /* shift for access permissions in a L1 section mapping */
     95 #define AP_SECTION_SHIFT	10
     96 
     97 /* Page table types and masks */
     98 #define L1_PAGE		0x01	/* L1 page table mapping */
     99 #define L1_SECTION	0x02	/* L1 section mapping */
    100 #define L1_FPAGE	0x03	/* L1 fine page mapping */
    101 #define L1_MASK		0x03	/* Mask for L1 entry type */
    102 #define L2_LPAGE	0x01	/* L2 large page (64KB) */
    103 #define L2_SPAGE	0x02	/* L2 small page (4KB) */
    104 #define L2_MASK		0x03	/* Mask for L2 entry type */
    105 #define L2_INVAL	0x00	/* L2 invalid type */
    106 
    107 /* PTE construction macros */
    108 #define	L2_LPTE(p, a, f)	((p) | PT_AP(a) | L2_LPAGE | (f))
    109 #define L2_SPTE(p, a, f)	((p) | PT_AP(a) | L2_SPAGE | (f))
    110 #define L2_PTE(p, a)		L2_SPTE((p), (a), PT_CACHEABLE)
    111 #define L2_PTE_NC(p, a)		L2_SPTE((p), (a), PT_B)
    112 #define L2_PTE_NC_NB(p, a)	L2_SPTE((p), (a), 0)
    113 #define L1_SECPTE(p, a, f)	((p) | ((a) << AP_SECTION_SHIFT) | (f) \
    114 				| L1_SECTION | PT_U)
    115 
    116 #define L1_PTE(p)	((p) | 0x00 | L1_PAGE | PT_U)
    117 #define L1_SEC(p, c)	L1_SECPTE((p), AP_KRW, (c))
    118 
    119 #define L1_SEC_SIZE	(1 << PDSHIFT)
    120 #define L2_LPAGE_SIZE	(NBPG * 16)
    121 
    122 /* Domain types */
    123 #define DOMAIN_FAULT		0x00
    124 #define DOMAIN_CLIENT		0x01
    125 #define DOMAIN_RESERVED		0x02
    126 #define DOMAIN_MANAGER		0x03
    127 
    128 #endif
    129 
    130 /* End of pte.h */
    131