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armreg.h revision 1.18.2.3
      1  1.18.2.3  gehenna /*	$NetBSD: armreg.h,v 1.18.2.3 2002/08/30 00:19:10 gehenna Exp $	*/
      2       1.1    bjh21 
      3       1.1    bjh21 /*
      4       1.1    bjh21  * Copyright (c) 1998, 2001 Ben Harris
      5       1.1    bjh21  * Copyright (c) 1994-1996 Mark Brinicombe.
      6       1.1    bjh21  * Copyright (c) 1994 Brini.
      7       1.1    bjh21  * All rights reserved.
      8       1.1    bjh21  *
      9       1.1    bjh21  * This code is derived from software written for Brini by Mark Brinicombe
     10       1.1    bjh21  *
     11       1.1    bjh21  * Redistribution and use in source and binary forms, with or without
     12       1.1    bjh21  * modification, are permitted provided that the following conditions
     13       1.1    bjh21  * are met:
     14       1.1    bjh21  * 1. Redistributions of source code must retain the above copyright
     15       1.1    bjh21  *    notice, this list of conditions and the following disclaimer.
     16       1.1    bjh21  * 2. Redistributions in binary form must reproduce the above copyright
     17       1.1    bjh21  *    notice, this list of conditions and the following disclaimer in the
     18       1.1    bjh21  *    documentation and/or other materials provided with the distribution.
     19       1.1    bjh21  * 3. All advertising materials mentioning features or use of this software
     20       1.1    bjh21  *    must display the following acknowledgement:
     21       1.1    bjh21  *	This product includes software developed by Brini.
     22       1.1    bjh21  * 4. The name of the company nor the name of the author may be used to
     23       1.1    bjh21  *    endorse or promote products derived from this software without specific
     24       1.1    bjh21  *    prior written permission.
     25       1.1    bjh21  *
     26       1.1    bjh21  * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
     27       1.1    bjh21  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
     28       1.1    bjh21  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     29       1.1    bjh21  * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
     30       1.1    bjh21  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
     31       1.1    bjh21  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
     32       1.1    bjh21  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     33       1.1    bjh21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     34       1.1    bjh21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     35       1.1    bjh21  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     36       1.1    bjh21  * SUCH DAMAGE.
     37       1.1    bjh21  */
     38       1.1    bjh21 
     39       1.1    bjh21 #ifndef _ARM_ARMREG_H
     40       1.1    bjh21 #define _ARM_ARMREG_H
     41       1.1    bjh21 
     42       1.1    bjh21 /*
     43       1.1    bjh21  * ARM Process Status Register
     44       1.1    bjh21  *
     45       1.1    bjh21  * The picture in the ARM manuals looks like this:
     46       1.1    bjh21  *       3 3 2 2 2 2
     47       1.1    bjh21  *       1 0 9 8 7 6                                   8 7 6 5 4       0
     48       1.1    bjh21  *      +-+-+-+-+-+-------------------------------------+-+-+-+---------+
     49       1.1    bjh21  *      |N|Z|C|V|Q|                reserved             |I|F|T|M M M M M|
     50       1.1    bjh21  *      | | | | | |                                     | | | |4 3 2 1 0|
     51       1.1    bjh21  *      +-+-+-+-+-+-------------------------------------+-+-+-+---------+
     52       1.1    bjh21  */
     53       1.1    bjh21 
     54       1.1    bjh21 #define	PSR_FLAGS 0xf0000000	/* flags */
     55       1.1    bjh21 #define PSR_N_bit (1 << 31)	/* negative */
     56       1.1    bjh21 #define PSR_Z_bit (1 << 30)	/* zero */
     57       1.1    bjh21 #define PSR_C_bit (1 << 29)	/* carry */
     58       1.1    bjh21 #define PSR_V_bit (1 << 28)	/* overflow */
     59       1.1    bjh21 
     60       1.1    bjh21 #define PSR_Q_bit (1 << 27)	/* saturation */
     61       1.1    bjh21 
     62       1.1    bjh21 #define I32_bit (1 << 7)	/* IRQ disable */
     63       1.1    bjh21 #define F32_bit (1 << 6)	/* FIQ disable */
     64       1.1    bjh21 
     65       1.1    bjh21 #define PSR_T_bit (1 << 5)	/* Thumb state */
     66       1.8      rjs #define PSR_J_bit (1 << 24)	/* Java mode */
     67       1.1    bjh21 
     68       1.1    bjh21 #define PSR_MODE	0x0000001f	/* mode mask */
     69       1.1    bjh21 #define PSR_USR26_MODE	0x00000000
     70       1.1    bjh21 #define PSR_FIQ26_MODE	0x00000001
     71       1.1    bjh21 #define PSR_IRQ26_MODE	0x00000002
     72       1.1    bjh21 #define PSR_SVC26_MODE	0x00000003
     73       1.1    bjh21 #define PSR_USR32_MODE	0x00000010
     74       1.1    bjh21 #define PSR_FIQ32_MODE	0x00000011
     75       1.1    bjh21 #define PSR_IRQ32_MODE	0x00000012
     76       1.1    bjh21 #define PSR_SVC32_MODE	0x00000013
     77       1.1    bjh21 #define PSR_ABT32_MODE	0x00000017
     78       1.1    bjh21 #define PSR_UND32_MODE	0x0000001b
     79       1.1    bjh21 #define PSR_SYS32_MODE	0x0000001f
     80       1.1    bjh21 #define PSR_32_MODE	0x00000010
     81       1.1    bjh21 
     82       1.1    bjh21 #define PSR_IN_USR_MODE(psr)	(!((psr) & 3))		/* XXX */
     83       1.1    bjh21 #define PSR_IN_32_MODE(psr)	((psr) & PSR_32_MODE)
     84       1.1    bjh21 
     85       1.1    bjh21 /* In 26-bit modes, the PSR is stuffed into R15 along with the PC. */
     86       1.1    bjh21 
     87       1.1    bjh21 #define R15_MODE	0x00000003
     88       1.1    bjh21 #define R15_MODE_USR	0x00000000
     89       1.1    bjh21 #define R15_MODE_FIQ	0x00000001
     90       1.1    bjh21 #define R15_MODE_IRQ	0x00000002
     91       1.1    bjh21 #define R15_MODE_SVC	0x00000003
     92       1.1    bjh21 
     93       1.1    bjh21 #define R15_PC		0x03fffffc
     94       1.1    bjh21 
     95       1.1    bjh21 #define R15_FIQ_DISABLE	0x04000000
     96       1.1    bjh21 #define R15_IRQ_DISABLE	0x08000000
     97       1.1    bjh21 
     98       1.1    bjh21 #define R15_FLAGS	0xf0000000
     99       1.1    bjh21 #define R15_FLAG_N	0x80000000
    100       1.1    bjh21 #define R15_FLAG_Z	0x40000000
    101       1.1    bjh21 #define R15_FLAG_C	0x20000000
    102       1.1    bjh21 #define R15_FLAG_V	0x10000000
    103       1.1    bjh21 
    104       1.1    bjh21 /*
    105       1.1    bjh21  * Co-processor 15:  The system control co-processor.
    106       1.1    bjh21  */
    107       1.1    bjh21 
    108       1.1    bjh21 #define ARM_CP15_CPU_ID		0
    109       1.1    bjh21 
    110       1.1    bjh21 /*
    111       1.1    bjh21  * The CPU ID register is theoretically structured, but the definitions of
    112       1.1    bjh21  * the fields keep changing.
    113       1.1    bjh21  */
    114       1.1    bjh21 
    115       1.1    bjh21 /* The high-order byte is always the implementor */
    116       1.1    bjh21 #define CPU_ID_IMPLEMENTOR_MASK	0xff000000
    117       1.1    bjh21 #define CPU_ID_ARM_LTD		0x41000000 /* 'A' */
    118       1.1    bjh21 #define CPU_ID_DEC		0x44000000 /* 'D' */
    119       1.1    bjh21 #define CPU_ID_INTEL		0x69000000 /* 'i' */
    120       1.1    bjh21 
    121       1.3    bjh21 /* How to decide what format the CPUID is in. */
    122       1.7    bjh21 #define CPU_ID_ISOLD(x)		(((x) & 0x0000f000) == 0x00000000)
    123       1.7    bjh21 #define CPU_ID_IS7(x)		(((x) & 0x0000f000) == 0x00007000)
    124       1.3    bjh21 #define CPU_ID_ISNEW(x)		(!CPU_ID_ISOLD(x) && !CPU_ID_IS7(x))
    125       1.3    bjh21 
    126       1.1    bjh21 /* On ARM3 and ARM6, this byte holds the foundry ID. */
    127       1.1    bjh21 #define CPU_ID_FOUNDRY_MASK	0x00ff0000
    128       1.1    bjh21 #define CPU_ID_FOUNDRY_VLSI	0x00560000
    129       1.1    bjh21 
    130       1.1    bjh21 /* On ARM7 it holds the architecture and variant (sub-model) */
    131       1.1    bjh21 #define CPU_ID_7ARCH_MASK	0x00800000
    132       1.1    bjh21 #define CPU_ID_7ARCH_V3		0x00000000
    133       1.1    bjh21 #define CPU_ID_7ARCH_V4T	0x00800000
    134       1.1    bjh21 #define CPU_ID_7VARIANT_MASK	0x007f0000
    135       1.1    bjh21 
    136       1.1    bjh21 /* On more recent ARMs, it does the same, but in a different format */
    137       1.1    bjh21 #define CPU_ID_ARCH_MASK	0x000f0000
    138       1.1    bjh21 #define CPU_ID_ARCH_V3		0x00000000
    139       1.1    bjh21 #define CPU_ID_ARCH_V4		0x00010000
    140       1.1    bjh21 #define CPU_ID_ARCH_V4T		0x00020000
    141       1.1    bjh21 #define CPU_ID_ARCH_V5		0x00030000
    142       1.1    bjh21 #define CPU_ID_ARCH_V5T		0x00040000
    143       1.1    bjh21 #define CPU_ID_ARCH_V5TE	0x00050000
    144       1.1    bjh21 #define CPU_ID_VARIANT_MASK	0x00f00000
    145       1.1    bjh21 
    146       1.1    bjh21 /* Next three nybbles are part number */
    147       1.1    bjh21 #define CPU_ID_PARTNO_MASK	0x0000fff0
    148       1.1    bjh21 
    149      1.10      rjs #define CPU_ID_XSCALE_COREREV_MASK	0x0000e000
    150      1.10      rjs 
    151       1.1    bjh21 /* And finally, the revision number. */
    152       1.1    bjh21 #define CPU_ID_REVISION_MASK	0x0000000f
    153       1.2    bjh21 
    154       1.2    bjh21 /* Individual CPUs are probably best IDed by everything but the revision. */
    155       1.2    bjh21 #define CPU_ID_CPU_MASK		0xfffffff0
    156       1.1    bjh21 
    157       1.1    bjh21 /* Fake CPU IDs for ARMs without CP15 */
    158       1.1    bjh21 #define CPU_ID_ARM2		0x41560200
    159       1.1    bjh21 #define CPU_ID_ARM250		0x41560250
    160       1.1    bjh21 
    161       1.1    bjh21 /* Pre-ARM7 CPUs -- [15:12] == 0 */
    162       1.1    bjh21 #define CPU_ID_ARM3		0x41560300
    163       1.1    bjh21 #define CPU_ID_ARM600		0x41560600
    164       1.1    bjh21 #define CPU_ID_ARM610		0x41560610
    165       1.1    bjh21 #define CPU_ID_ARM620		0x41560620
    166       1.1    bjh21 
    167       1.1    bjh21 /* ARM7 CPUs -- [15:12] == 7 */
    168       1.4    bjh21 #define CPU_ID_ARM700		0x41007000 /* XXX This is a guess. */
    169       1.1    bjh21 #define CPU_ID_ARM710		0x41007100
    170       1.4    bjh21 #define CPU_ID_ARM7500		0x41027100 /* XXX This is a guess. */
    171       1.5    bjh21 #define CPU_ID_ARM710A		0x41047100 /* inc ARM7100 */
    172       1.6    bjh21 #define CPU_ID_ARM7500FE	0x41077100
    173       1.1    bjh21 #define CPU_ID_ARM710T		0x41807100
    174       1.1    bjh21 #define CPU_ID_ARM720T		0x41807200
    175       1.1    bjh21 #define CPU_ID_ARM740T8K	0x41807400 /* XXX no MMU, 8KB cache */
    176       1.1    bjh21 #define CPU_ID_ARM740T4K	0x41817400 /* XXX no MMU, 4KB cache */
    177       1.1    bjh21 
    178       1.1    bjh21 /* Post-ARM7 CPUs */
    179       1.1    bjh21 #define CPU_ID_ARM810		0x41018100
    180       1.1    bjh21 #define CPU_ID_ARM920T		0x41129200
    181       1.1    bjh21 #define CPU_ID_ARM922T		0x41029220
    182       1.1    bjh21 #define CPU_ID_ARM940T		0x41029400 /* XXX no MMU */
    183       1.1    bjh21 #define CPU_ID_ARM946ES		0x41049460 /* XXX no MMU */
    184       1.1    bjh21 #define	CPU_ID_ARM966ES		0x41049660 /* XXX no MMU */
    185       1.1    bjh21 #define	CPU_ID_ARM966ESR1	0x41059660 /* XXX no MMU */
    186      1.11    bjh21 #define CPU_ID_ARM1022ES	0x4105a220
    187       1.1    bjh21 #define CPU_ID_SA110		0x4401a100
    188       1.1    bjh21 #define CPU_ID_SA1100		0x4401a110
    189       1.1    bjh21 #define CPU_ID_SA1110		0x6901b110
    190      1.18   ichiro #define CPU_ID_IXP1200		0x6901c120
    191      1.13  thorpej #define CPU_ID_80200		0x69052000
    192  1.18.2.2  gehenna #define CPU_ID_PXA250A		0x69052100 /* 1st version Core */
    193  1.18.2.2  gehenna #define CPU_ID_PXA210A		0x69052120 /* 1st version Core */
    194  1.18.2.2  gehenna #define CPU_ID_PXA250B		0x69052900 /* 3rd version Core */
    195  1.18.2.2  gehenna #define CPU_ID_PXA210B		0x69052920 /* 3rd version Core */
    196  1.18.2.1  gehenna #define	CPU_ID_80321_400	0x69052420
    197  1.18.2.1  gehenna #define	CPU_ID_80321_600	0x69052430
    198  1.18.2.3  gehenna #define	CPU_ID_80321_400_B0	0x69052c20
    199  1.18.2.3  gehenna #define	CPU_ID_80321_600_B0	0x69052c30
    200       1.1    bjh21 
    201       1.1    bjh21 /* ARM3-specific coprocessor 15 registers */
    202       1.1    bjh21 #define ARM3_CP15_FLUSH		1
    203       1.1    bjh21 #define ARM3_CP15_CONTROL	2
    204       1.1    bjh21 #define ARM3_CP15_CACHEABLE	3
    205       1.1    bjh21 #define ARM3_CP15_UPDATEABLE	4
    206       1.1    bjh21 #define ARM3_CP15_DISRUPTIVE	5
    207       1.1    bjh21 
    208       1.1    bjh21 /* ARM3 Control register bits */
    209       1.1    bjh21 #define ARM3_CTL_CACHE_ON	0x00000001
    210       1.1    bjh21 #define ARM3_CTL_SHARED		0x00000002
    211       1.1    bjh21 #define ARM3_CTL_MONITOR	0x00000004
    212       1.1    bjh21 
    213       1.1    bjh21 /*
    214       1.1    bjh21  * Post-ARM3 CP15 registers:
    215      1.14  thorpej  *
    216      1.14  thorpej  *	1	Control register
    217      1.14  thorpej  *
    218      1.14  thorpej  *	2	Translation Table Base
    219      1.14  thorpej  *
    220      1.14  thorpej  *	3	Domain Access Control
    221      1.14  thorpej  *
    222      1.14  thorpej  *	4	Reserved
    223      1.14  thorpej  *
    224      1.14  thorpej  *	5	Fault Status
    225      1.14  thorpej  *
    226      1.14  thorpej  *	6	Fault Address
    227      1.14  thorpej  *
    228      1.14  thorpej  *	7	Cache/write-buffer Control
    229      1.14  thorpej  *
    230      1.14  thorpej  *	8	TLB Control
    231      1.14  thorpej  *
    232      1.14  thorpej  *	9	Cache Lockdown
    233      1.14  thorpej  *
    234      1.14  thorpej  *	10	TLB Lockdown
    235      1.14  thorpej  *
    236      1.14  thorpej  *	11	Reserved
    237      1.14  thorpej  *
    238      1.14  thorpej  *	12	Reserved
    239      1.14  thorpej  *
    240      1.14  thorpej  *	13	Process ID (for FCSE)
    241      1.14  thorpej  *
    242      1.14  thorpej  *	14	Reserved
    243      1.14  thorpej  *
    244      1.14  thorpej  *	15	Implementation Dependent
    245       1.1    bjh21  */
    246      1.14  thorpej 
    247       1.1    bjh21 /* Some of the definitions below need cleaning up for V3/V4 architectures */
    248       1.1    bjh21 
    249       1.1    bjh21 /* CPU control register (CP15 register 1) */
    250       1.1    bjh21 #define CPU_CONTROL_MMU_ENABLE	0x00000001 /* M: MMU/Protection unit enable */
    251       1.1    bjh21 #define CPU_CONTROL_AFLT_ENABLE	0x00000002 /* A: Alignment fault enable */
    252       1.1    bjh21 #define CPU_CONTROL_DC_ENABLE	0x00000004 /* C: IDC/DC enable */
    253       1.1    bjh21 #define CPU_CONTROL_WBUF_ENABLE 0x00000008 /* W: Write buffer enable */
    254       1.1    bjh21 #define CPU_CONTROL_32BP_ENABLE 0x00000010 /* P: 32-bit exception handlers */
    255       1.1    bjh21 #define CPU_CONTROL_32BD_ENABLE 0x00000020 /* D: 32-bit addressing */
    256       1.1    bjh21 #define CPU_CONTROL_LABT_ENABLE 0x00000040 /* L: Late abort enable */
    257       1.1    bjh21 #define CPU_CONTROL_BEND_ENABLE 0x00000080 /* B: Big-endian mode */
    258       1.1    bjh21 #define CPU_CONTROL_SYST_ENABLE 0x00000100 /* S: System protection bit */
    259       1.1    bjh21 #define CPU_CONTROL_ROM_ENABLE	0x00000200 /* R: ROM protection bit */
    260       1.1    bjh21 #define CPU_CONTROL_CPCLK	0x00000400 /* F: Implementation defined */
    261       1.1    bjh21 #define CPU_CONTROL_BPRD_ENABLE 0x00000800 /* Z: Branch prediction enable */
    262       1.1    bjh21 #define CPU_CONTROL_IC_ENABLE   0x00001000 /* I: IC enable */
    263       1.1    bjh21 #define CPU_CONTROL_VECRELOC	0x00002000 /* V: Vector relocation */
    264       1.1    bjh21 #define CPU_CONTROL_ROUNDROBIN	0x00004000 /* RR: Predictable replacement */
    265       1.1    bjh21 #define CPU_CONTROL_V4COMPAT	0x00008000 /* L4: ARMv4 compat LDR R15 etc */
    266       1.1    bjh21 
    267       1.1    bjh21 #define CPU_CONTROL_IDC_ENABLE	CPU_CONTROL_DC_ENABLE
    268      1.16  thorpej 
    269      1.16  thorpej /* XScale Auxillary Control Register (CP15 register 1, opcode2 1) */
    270      1.16  thorpej #define	XSCALE_AUXCTL_K		0x00000001 /* dis. write buffer coalescing */
    271      1.16  thorpej #define	XSCALE_AUXCTL_P		0x00000002 /* ECC protect page table access */
    272      1.16  thorpej #define	XSCALE_AUXCTL_MD_WB_RA	0x00000000 /* mini-D$ wb, read-allocate */
    273      1.16  thorpej #define	XSCALE_AUXCTL_MD_WB_RWA	0x00000010 /* mini-D$ wb, read/write-allocate */
    274      1.17  thorpej #define	XSCALE_AUXCTL_MD_WT	0x00000020 /* mini-D$ wt, read-allocate */
    275      1.17  thorpej #define	XSCALE_AUXCTL_MD_MASK	0x00000030
    276       1.1    bjh21 
    277       1.1    bjh21 /* Cache type register definitions */
    278       1.9  thorpej #define	CPU_CT_ISIZE(x)		((x) & 0xfff)		/* I$ info */
    279       1.9  thorpej #define	CPU_CT_DSIZE(x)		(((x) >> 12) & 0xfff)	/* D$ info */
    280       1.9  thorpej #define	CPU_CT_S		(1U << 24)		/* split cache */
    281       1.9  thorpej #define	CPU_CT_CTYPE(x)		(((x) >> 25) & 0xf)	/* cache type */
    282       1.9  thorpej 
    283       1.9  thorpej #define	CPU_CT_CTYPE_WT		0	/* write-through */
    284       1.9  thorpej #define	CPU_CT_CTYPE_WB1	1	/* write-back, clean w/ read */
    285       1.9  thorpej #define	CPU_CT_CTYPE_WB2	2	/* w/b, clean w/ cp15,7 */
    286       1.9  thorpej #define	CPU_CT_CTYPE_WB6	6	/* w/b, cp15,7, lockdown fmt A */
    287       1.9  thorpej #define	CPU_CT_CTYPE_WB7	7	/* w/b, cp15,7, lockdown fmt B */
    288       1.9  thorpej 
    289       1.9  thorpej #define	CPU_CT_xSIZE_LEN(x)	((x) & 0x3)		/* line size */
    290       1.9  thorpej #define	CPU_CT_xSIZE_M		(1U << 2)		/* multiplier */
    291       1.9  thorpej #define	CPU_CT_xSIZE_ASSOC(x)	(((x) >> 3) & 0x7)	/* associativity */
    292       1.9  thorpej #define	CPU_CT_xSIZE_SIZE(x)	(((x) >> 6) & 0x7)	/* size */
    293       1.1    bjh21 
    294       1.1    bjh21 /* Fault status register definitions */
    295       1.1    bjh21 
    296       1.1    bjh21 #define FAULT_TYPE_MASK 0x0f
    297       1.1    bjh21 #define FAULT_USER      0x10
    298       1.1    bjh21 
    299       1.1    bjh21 #define FAULT_WRTBUF_0  0x00 /* Vector Exception */
    300       1.1    bjh21 #define FAULT_WRTBUF_1  0x02 /* Terminal Exception */
    301       1.1    bjh21 #define FAULT_BUSERR_0  0x04 /* External Abort on Linefetch -- Section */
    302       1.1    bjh21 #define FAULT_BUSERR_1  0x06 /* External Abort on Linefetch -- Page */
    303       1.1    bjh21 #define FAULT_BUSERR_2  0x08 /* External Abort on Non-linefetch -- Section */
    304       1.1    bjh21 #define FAULT_BUSERR_3  0x0a /* External Abort on Non-linefetch -- Page */
    305       1.1    bjh21 #define FAULT_BUSTRNL1  0x0c /* External abort on Translation -- Level 1 */
    306       1.1    bjh21 #define FAULT_BUSTRNL2  0x0e /* External abort on Translation -- Level 2 */
    307       1.1    bjh21 #define FAULT_ALIGN_0   0x01 /* Alignment */
    308       1.1    bjh21 #define FAULT_ALIGN_1   0x03 /* Alignment */
    309       1.1    bjh21 #define FAULT_TRANS_S   0x05 /* Translation -- Section */
    310       1.1    bjh21 #define FAULT_TRANS_P   0x07 /* Translation -- Page */
    311       1.1    bjh21 #define FAULT_DOMAIN_S  0x09 /* Domain -- Section */
    312       1.1    bjh21 #define FAULT_DOMAIN_P  0x0b /* Domain -- Page */
    313       1.1    bjh21 #define FAULT_PERM_S    0x0d /* Permission -- Section */
    314       1.1    bjh21 #define FAULT_PERM_P    0x0f /* Permission -- Page */
    315      1.15  thorpej 
    316      1.15  thorpej /*
    317      1.15  thorpej  * Address of the vector page, low and high versions.
    318      1.15  thorpej  */
    319      1.15  thorpej #define	ARM_VECTORS_LOW		0x00000000
    320      1.15  thorpej #define	ARM_VECTORS_HIGH	0xffff0000
    321       1.1    bjh21 
    322       1.1    bjh21 /*
    323       1.1    bjh21  * ARM Instructions
    324       1.1    bjh21  *
    325       1.1    bjh21  *       3 3 2 2 2
    326       1.1    bjh21  *       1 0 9 8 7                                                     0
    327       1.1    bjh21  *      +-------+-------------------------------------------------------+
    328       1.1    bjh21  *      | cond  |              instruction dependant                    |
    329       1.1    bjh21  *      |c c c c|                                                       |
    330       1.1    bjh21  *      +-------+-------------------------------------------------------+
    331       1.1    bjh21  */
    332       1.1    bjh21 
    333       1.1    bjh21 #define INSN_SIZE		4		/* Always 4 bytes */
    334       1.1    bjh21 #define INSN_COND_MASK		0xf0000000	/* Condition mask */
    335       1.1    bjh21 #define INSN_COND_AL		0xe0000000	/* Always condition */
    336       1.1    bjh21 
    337       1.1    bjh21 #endif
    338