armreg.h revision 1.118
1 /* $NetBSD: armreg.h,v 1.118 2018/03/02 22:23:17 christos Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2001 Ben Harris 5 * Copyright (c) 1994-1996 Mark Brinicombe. 6 * Copyright (c) 1994 Brini. 7 * All rights reserved. 8 * 9 * This code is derived from software written for Brini by Mark Brinicombe 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by Brini. 22 * 4. The name of the company nor the name of the author may be used to 23 * endorse or promote products derived from this software without specific 24 * prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 27 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 28 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 29 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 30 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 31 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 32 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 */ 38 39 #ifndef _ARM_ARMREG_H 40 #define _ARM_ARMREG_H 41 42 /* 43 * ARM Process Status Register 44 * 45 * The picture in the ARM manuals looks like this: 46 * 3 3 2 2 2 2 47 * 1 0 9 8 7 6 8 7 6 5 4 0 48 * +-+-+-+-+-+-------------------------------------+-+-+-+---------+ 49 * |N|Z|C|V|Q| reserved |I|F|T|M M M M M| 50 * | | | | | | | | | |4 3 2 1 0| 51 * +-+-+-+-+-+-------------------------------------+-+-+-+---------+ 52 */ 53 54 #define PSR_FLAGS 0xf0000000 /* flags */ 55 #define PSR_N_bit (1 << 31) /* negative */ 56 #define PSR_Z_bit (1 << 30) /* zero */ 57 #define PSR_C_bit (1 << 29) /* carry */ 58 #define PSR_V_bit (1 << 28) /* overflow */ 59 60 #define PSR_Q_bit (1 << 27) /* saturation */ 61 #define PSR_IT1_bit (1 << 26) 62 #define PSR_IT0_bit (1 << 25) 63 #define PSR_J_bit (1 << 24) /* Jazelle mode */ 64 #define PSR_GE_bits (15 << 16) /* SIMD GE bits */ 65 #define PSR_IT7_bit (1 << 15) 66 #define PSR_IT6_bit (1 << 14) 67 #define PSR_IT5_bit (1 << 13) 68 #define PSR_IT4_bit (1 << 12) 69 #define PSR_IT3_bit (1 << 11) 70 #define PSR_IT2_bit (1 << 10) 71 #define PSR_E_BIT (1 << 9) /* Endian state */ 72 #define PSR_A_BIT (1 << 8) /* Async abort disable */ 73 74 #define I32_bit (1 << 7) /* IRQ disable */ 75 #define F32_bit (1 << 6) /* FIQ disable */ 76 #define IF32_bits (3 << 6) /* IRQ/FIQ disable */ 77 78 #define PSR_T_bit (1 << 5) /* Thumb state */ 79 80 #define PSR_MODE 0x0000001f /* mode mask */ 81 #define PSR_USR32_MODE 0x00000010 82 #define PSR_FIQ32_MODE 0x00000011 83 #define PSR_IRQ32_MODE 0x00000012 84 #define PSR_SVC32_MODE 0x00000013 85 #define PSR_MON32_MODE 0x00000016 86 #define PSR_ABT32_MODE 0x00000017 87 #define PSR_HYP32_MODE 0x0000001a 88 #define PSR_UND32_MODE 0x0000001b 89 #define PSR_SYS32_MODE 0x0000001f 90 #define PSR_32_MODE 0x00000010 91 92 #define R15_FLAGS 0xf0000000 93 #define R15_FLAG_N 0x80000000 94 #define R15_FLAG_Z 0x40000000 95 #define R15_FLAG_C 0x20000000 96 #define R15_FLAG_V 0x10000000 97 98 /* 99 * Co-processor 15: The system control co-processor. 100 */ 101 102 #define ARM_CP15_CPU_ID 0 103 104 /* 105 * The CPU ID register is theoretically structured, but the definitions of 106 * the fields keep changing. 107 */ 108 109 /* The high-order byte is always the implementor */ 110 #define CPU_ID_IMPLEMENTOR_MASK 0xff000000 111 #define CPU_ID_ARM_LTD 0x41000000 /* 'A' */ 112 #define CPU_ID_DEC 0x44000000 /* 'D' */ 113 #define CPU_ID_INTEL 0x69000000 /* 'i' */ 114 #define CPU_ID_TI 0x54000000 /* 'T' */ 115 #define CPU_ID_MARVELL 0x56000000 /* 'V' */ 116 #define CPU_ID_FARADAY 0x66000000 /* 'f' */ 117 118 /* How to decide what format the CPUID is in. */ 119 #define CPU_ID_ISOLD(x) (((x) & 0x0000f000) == 0x00000000) 120 #define CPU_ID_IS7(x) (((x) & 0x0000f000) == 0x00007000) 121 #define CPU_ID_ISNEW(x) (!CPU_ID_ISOLD(x) && !CPU_ID_IS7(x)) 122 123 /* On ARM3 and ARM6, this byte holds the foundry ID. */ 124 #define CPU_ID_FOUNDRY_MASK 0x00ff0000 125 #define CPU_ID_FOUNDRY_VLSI 0x00560000 126 127 /* On ARM7 it holds the architecture and variant (sub-model) */ 128 #define CPU_ID_7ARCH_MASK 0x00800000 129 #define CPU_ID_7ARCH_V3 0x00000000 130 #define CPU_ID_7ARCH_V4T 0x00800000 131 #define CPU_ID_7VARIANT_MASK 0x007f0000 132 133 /* On more recent ARMs, it does the same, but in a different format */ 134 #define CPU_ID_ARCH_MASK 0x000f0000 135 #define CPU_ID_ARCH_V3 0x00000000 136 #define CPU_ID_ARCH_V4 0x00010000 137 #define CPU_ID_ARCH_V4T 0x00020000 138 #define CPU_ID_ARCH_V5 0x00030000 139 #define CPU_ID_ARCH_V5T 0x00040000 140 #define CPU_ID_ARCH_V5TE 0x00050000 141 #define CPU_ID_ARCH_V5TEJ 0x00060000 142 #define CPU_ID_ARCH_V6 0x00070000 143 #define CPU_ID_VARIANT_MASK 0x00f00000 144 145 /* Next three nybbles are part number */ 146 #define CPU_ID_PARTNO_MASK 0x0000fff0 147 148 /* Intel XScale has sub fields in part number */ 149 #define CPU_ID_XSCALE_COREGEN_MASK 0x0000e000 /* core generation */ 150 #define CPU_ID_XSCALE_COREREV_MASK 0x00001c00 /* core revision */ 151 #define CPU_ID_XSCALE_PRODUCT_MASK 0x000003f0 /* product number */ 152 153 /* And finally, the revision number. */ 154 #define CPU_ID_REVISION_MASK 0x0000000f 155 156 /* Individual CPUs are probably best IDed by everything but the revision. */ 157 #define CPU_ID_CPU_MASK 0xfffffff0 158 159 /* Fake CPU IDs for ARMs without CP15 */ 160 #define CPU_ID_ARM2 0x41560200 161 #define CPU_ID_ARM250 0x41560250 162 163 /* Pre-ARM7 CPUs -- [15:12] == 0 */ 164 #define CPU_ID_ARM3 0x41560300 165 #define CPU_ID_ARM600 0x41560600 166 #define CPU_ID_ARM610 0x41560610 167 #define CPU_ID_ARM620 0x41560620 168 169 /* ARM7 CPUs -- [15:12] == 7 */ 170 #define CPU_ID_ARM700 0x41007000 /* XXX This is a guess. */ 171 #define CPU_ID_ARM710 0x41007100 172 #define CPU_ID_ARM7500 0x41027100 173 #define CPU_ID_ARM710A 0x41067100 174 #define CPU_ID_ARM7500FE 0x41077100 175 #define CPU_ID_ARM710T 0x41807100 176 #define CPU_ID_ARM720T 0x41807200 177 #define CPU_ID_ARM740T8K 0x41807400 /* XXX no MMU, 8KB cache */ 178 #define CPU_ID_ARM740T4K 0x41817400 /* XXX no MMU, 4KB cache */ 179 180 /* Post-ARM7 CPUs */ 181 #define CPU_ID_ARM810 0x41018100 182 #define CPU_ID_ARM920T 0x41129200 183 #define CPU_ID_ARM922T 0x41029220 184 #define CPU_ID_ARM926EJS 0x41069260 185 #define CPU_ID_ARM940T 0x41029400 /* XXX no MMU */ 186 #define CPU_ID_ARM946ES 0x41049460 /* XXX no MMU */ 187 #define CPU_ID_ARM966ES 0x41049660 /* XXX no MMU */ 188 #define CPU_ID_ARM966ESR1 0x41059660 /* XXX no MMU */ 189 #define CPU_ID_ARM1020E 0x4115a200 /* (AKA arm10 rev 1) */ 190 #define CPU_ID_ARM1022ES 0x4105a220 191 #define CPU_ID_ARM1026EJS 0x4106a260 192 #define CPU_ID_ARM11MPCORE 0x410fb020 193 #define CPU_ID_ARM1136JS 0x4107b360 194 #define CPU_ID_ARM1136JSR1 0x4117b360 195 #define CPU_ID_ARM1156T2S 0x4107b560 /* MPU only */ 196 #define CPU_ID_ARM1176JZS 0x410fb760 197 #define CPU_ID_ARM11_P(n) ((n & 0xff07f000) == 0x4107b000) 198 #define CPU_ID_CORTEXA5R0 0x410fc050 199 #define CPU_ID_CORTEXA7R0 0x410fc070 200 #define CPU_ID_CORTEXA8R1 0x411fc080 201 #define CPU_ID_CORTEXA8R2 0x412fc080 202 #define CPU_ID_CORTEXA8R3 0x413fc080 203 #define CPU_ID_CORTEXA9R1 0x411fc090 204 #define CPU_ID_CORTEXA9R2 0x412fc090 205 #define CPU_ID_CORTEXA9R3 0x413fc090 206 #define CPU_ID_CORTEXA9R4 0x414fc090 207 #define CPU_ID_CORTEXA15R2 0x412fc0f0 208 #define CPU_ID_CORTEXA15R3 0x413fc0f0 209 #define CPU_ID_CORTEXA17R1 0x411fc0e0 210 #define CPU_ID_CORTEXA35R0 0x410fd040 211 #define CPU_ID_CORTEXA53R0 0x410fd030 212 #define CPU_ID_CORTEXA57R0 0x410fd070 213 #define CPU_ID_CORTEXA57R1 0x411fd070 214 #define CPU_ID_CORTEXA72R0 0x410fd080 215 216 #define CPU_ID_CORTEX_P(n) ((n & 0xff0fe000) == 0x410fc000) 217 #define CPU_ID_CORTEX_A5_P(n) ((n & 0xff0ff0f0) == 0x410fc050) 218 #define CPU_ID_CORTEX_A7_P(n) ((n & 0xff0ff0f0) == 0x410fc070) 219 #define CPU_ID_CORTEX_A8_P(n) ((n & 0xff0ff0f0) == 0x410fc080) 220 #define CPU_ID_CORTEX_A9_P(n) ((n & 0xff0ff0f0) == 0x410fc090) 221 #define CPU_ID_CORTEX_A15_P(n) ((n & 0xff0ff0f0) == 0x410fc0f0) 222 #define CPU_ID_CORTEX_A35_P(n) ((n & 0xff0ff0f0) == 0x410fd040) 223 #define CPU_ID_CORTEX_A53_P(n) ((n & 0xff0ff0f0) == 0x410fd030) 224 #define CPU_ID_CORTEX_A57_P(n) ((n & 0xff0ff0f0) == 0x410fd070) 225 #define CPU_ID_CORTEX_A72_P(n) ((n & 0xff0ff0f0) == 0x410fd080) 226 #define CPU_ID_SA110 0x4401a100 227 #define CPU_ID_SA1100 0x4401a110 228 #define CPU_ID_TI925T 0x54029250 229 #define CPU_ID_MV88FR571_VD 0x56155710 230 #define CPU_ID_MV88SV131 0x56251310 231 #define CPU_ID_FA526 0x66015260 232 #define CPU_ID_SA1110 0x6901b110 233 #define CPU_ID_IXP1200 0x6901c120 234 #define CPU_ID_80200 0x69052000 235 #define CPU_ID_PXA250 0x69052100 /* sans core revision */ 236 #define CPU_ID_PXA210 0x69052120 237 #define CPU_ID_PXA250A 0x69052100 /* 1st version Core */ 238 #define CPU_ID_PXA210A 0x69052120 /* 1st version Core */ 239 #define CPU_ID_PXA250B 0x69052900 /* 3rd version Core */ 240 #define CPU_ID_PXA210B 0x69052920 /* 3rd version Core */ 241 #define CPU_ID_PXA250C 0x69052d00 /* 4th version Core */ 242 #define CPU_ID_PXA210C 0x69052d20 /* 4th version Core */ 243 #define CPU_ID_PXA27X 0x69054110 244 #define CPU_ID_80321_400 0x69052420 245 #define CPU_ID_80321_600 0x69052430 246 #define CPU_ID_80321_400_B0 0x69052c20 247 #define CPU_ID_80321_600_B0 0x69052c30 248 #define CPU_ID_80219_400 0x69052e20 249 #define CPU_ID_80219_600 0x69052e30 250 #define CPU_ID_IXP425_533 0x690541c0 251 #define CPU_ID_IXP425_400 0x690541d0 252 #define CPU_ID_IXP425_266 0x690541f0 253 #define CPU_ID_MV88SV58XX_P(n) ((n & 0xff0fff00) == 0x560f5800) 254 #define CPU_ID_MV88SV581X_V6 0x560f5810 /* Marvell Sheeva 88SV581x v6 Core */ 255 #define CPU_ID_MV88SV581X_V7 0x561f5810 /* Marvell Sheeva 88SV581x v7 Core */ 256 #define CPU_ID_MV88SV584X_V6 0x561f5840 /* Marvell Sheeva 88SV584x v6 Core */ 257 #define CPU_ID_MV88SV584X_V7 0x562f5840 /* Marvell Sheeva 88SV584x v7 Core */ 258 /* Marvell's CPUIDs with ARM ID in implementor field */ 259 #define CPU_ID_ARM_88SV581X_V6 0x410fb760 /* Marvell Sheeva 88SV581x v6 Core */ 260 #define CPU_ID_ARM_88SV581X_V7 0x413fc080 /* Marvell Sheeva 88SV581x v7 Core */ 261 #define CPU_ID_ARM_88SV584X_V6 0x410fb020 /* Marvell Sheeva 88SV584x v6 Core */ 262 263 /* CPUID registers */ 264 #define ARM_ISA3_SYNCHPRIM_MASK 0x0000f000 265 #define ARM_ISA4_SYNCHPRIM_MASK 0x00f00000 266 #define ARM_ISA3_SYNCHPRIM_LDREX 0x10 // LDREX 267 #define ARM_ISA3_SYNCHPRIM_LDREXPLUS 0x13 // +CLREX/LDREXB/LDREXH 268 #define ARM_ISA3_SYNCHPRIM_LDREXD 0x20 // +LDREXD 269 #define ARM_PFR0_THUMBEE_MASK 0x0000f000 270 #define ARM_PFR1_GTIMER_MASK 0x000f0000 271 #define ARM_PFR1_VIRT_MASK 0x0000f000 272 #define ARM_PFR1_SEC_MASK 0x000000f0 273 274 /* Media and VFP Feature registers */ 275 #define ARM_MVFR0_ROUNDING_MASK 0xf0000000 276 #define ARM_MVFR0_SHORTVEC_MASK 0x0f000000 277 #define ARM_MVFR0_SQRT_MASK 0x00f00000 278 #define ARM_MVFR0_DIVIDE_MASK 0x000f0000 279 #define ARM_MVFR0_EXCEPT_MASK 0x0000f000 280 #define ARM_MVFR0_DFLOAT_MASK 0x00000f00 281 #define ARM_MVFR0_SFLOAT_MASK 0x000000f0 282 #define ARM_MVFR0_ASIMD_MASK 0x0000000f 283 #define ARM_MVFR1_ASIMD_FMACS_MASK 0xf0000000 284 #define ARM_MVFR1_VFP_HPFP_MASK 0x0f000000 285 #define ARM_MVFR1_ASIMD_HPFP_MASK 0x00f00000 286 #define ARM_MVFR1_ASIMD_SPFP_MASK 0x000f0000 287 #define ARM_MVFR1_ASIMD_INT_MASK 0x0000f000 288 #define ARM_MVFR1_ASIMD_LDST_MASK 0x00000f00 289 #define ARM_MVFR1_D_NAN_MASK 0x000000f0 290 #define ARM_MVFR1_FTZ_MASK 0x0000000f 291 292 /* ARM3-specific coprocessor 15 registers */ 293 #define ARM3_CP15_FLUSH 1 294 #define ARM3_CP15_CONTROL 2 295 #define ARM3_CP15_CACHEABLE 3 296 #define ARM3_CP15_UPDATEABLE 4 297 #define ARM3_CP15_DISRUPTIVE 5 298 299 /* ARM3 Control register bits */ 300 #define ARM3_CTL_CACHE_ON 0x00000001 301 #define ARM3_CTL_SHARED 0x00000002 302 #define ARM3_CTL_MONITOR 0x00000004 303 304 /* 305 * Post-ARM3 CP15 registers: 306 * 307 * 1 Control register 308 * 309 * 2 Translation Table Base 310 * 311 * 3 Domain Access Control 312 * 313 * 4 Reserved 314 * 315 * 5 Fault Status 316 * 317 * 6 Fault Address 318 * 319 * 7 Cache/write-buffer Control 320 * 321 * 8 TLB Control 322 * 323 * 9 Cache Lockdown 324 * 325 * 10 TLB Lockdown 326 * 327 * 11 Reserved 328 * 329 * 12 Reserved 330 * 331 * 13 Process ID (for FCSE) 332 * 333 * 14 Reserved 334 * 335 * 15 Implementation Dependent 336 */ 337 338 /* Some of the definitions below need cleaning up for V3/V4 architectures */ 339 340 /* CPU control register (CP15 register 1) */ 341 #define CPU_CONTROL_MMU_ENABLE 0x00000001 /* M: MMU/Protection unit enable */ 342 #define CPU_CONTROL_AFLT_ENABLE 0x00000002 /* A: Alignment fault enable */ 343 #define CPU_CONTROL_DC_ENABLE 0x00000004 /* C: IDC/DC enable */ 344 #define CPU_CONTROL_WBUF_ENABLE 0x00000008 /* W: Write buffer enable */ 345 #define CPU_CONTROL_32BP_ENABLE 0x00000010 /* P: 32-bit exception handlers */ 346 #define CPU_CONTROL_32BD_ENABLE 0x00000020 /* D: 32-bit addressing */ 347 #define CPU_CONTROL_LABT_ENABLE 0x00000040 /* L: Late abort enable */ 348 #define CPU_CONTROL_BEND_ENABLE 0x00000080 /* B: Big-endian mode */ 349 #define CPU_CONTROL_SYST_ENABLE 0x00000100 /* S: System protection bit */ 350 #define CPU_CONTROL_ROM_ENABLE 0x00000200 /* R: ROM protection bit */ 351 #define CPU_CONTROL_CPCLK 0x00000400 /* F: Implementation defined */ 352 #define CPU_CONTROL_SWP_ENABLE 0x00000400 /* SW: SWP{B} perform normally. */ 353 #define CPU_CONTROL_BPRD_ENABLE 0x00000800 /* Z: Branch prediction enable */ 354 #define CPU_CONTROL_IC_ENABLE 0x00001000 /* I: IC enable */ 355 #define CPU_CONTROL_VECRELOC 0x00002000 /* V: Vector relocation */ 356 #define CPU_CONTROL_ROUNDROBIN 0x00004000 /* RR: Predictable replacement */ 357 #define CPU_CONTROL_V4COMPAT 0x00008000 /* L4: ARMv4 compat LDR R15 etc */ 358 #define CPU_CONTROL_HA_ENABLE 0x00020000 /* HA: Hardware Access flag enable */ 359 #define CPU_CONTROL_WXN_ENABLE 0x00080000 /* WXN: Write Execute Never */ 360 #define CPU_CONTROL_UWXN_ENABLE 0x00100000 /* UWXN: User Write eXecute Never */ 361 #define CPU_CONTROL_FI_ENABLE 0x00200000 /* FI: Low interrupt latency */ 362 #define CPU_CONTROL_UNAL_ENABLE 0x00400000 /* U: unaligned data access */ 363 #define CPU_CONTROL_XP_ENABLE 0x00800000 /* XP: extended page table */ 364 #define CPU_CONTROL_V_ENABLE 0x01000000 /* VE: Interrupt vectors enable */ 365 #define CPU_CONTROL_EX_BEND 0x02000000 /* EE: exception endianness */ 366 #define CPU_CONTROL_NMFI 0x08000000 /* NMFI: Non maskable FIQ */ 367 #define CPU_CONTROL_TR_ENABLE 0x10000000 /* TRE: */ 368 #define CPU_CONTROL_AF_ENABLE 0x20000000 /* AFE: Access flag enable */ 369 #define CPU_CONTROL_TE_ENABLE 0x40000000 /* TE: Thumb Exception enable */ 370 371 #define CPU_CONTROL_IDC_ENABLE CPU_CONTROL_DC_ENABLE 372 373 /* ARMv6/ARMv7 Co-Processor Access Control Register (CP15, 0, c1, c0, 2) */ 374 #define CPACR_V7_ASEDIS 0x80000000 /* Disable Advanced SIMD Ext. */ 375 #define CPACR_V7_D32DIS 0x40000000 /* Disable VFP regs 15-31 */ 376 #define CPACR_CPn(n) (3 << (2*n)) 377 #define CPACR_NOACCESS 0 /* reset value */ 378 #define CPACR_PRIVED 1 /* Privileged mode access */ 379 #define CPACR_RESERVED 2 380 #define CPACR_ALL 3 /* Privileged and User mode access */ 381 382 /* ARMv6/ARMv7 Non-Secure Access Control Register (CP15, 0, c1, c1, 2) */ 383 #define NSACR_SMP 0x00040000 /* ACTRL.SMP is writeable (!A8) */ 384 #define NSACR_L2ERR 0x00020000 /* L2ECTRL is writeable (!A8) */ 385 #define NSACR_ASEDIS 0x00008000 /* Deny Advanced SIMD Ext. */ 386 #define NSACR_D32DIS 0x00004000 /* Deny VFP regs 15-31 */ 387 #define NSACR_CPn(n) (1 << (n)) /* NonSecure access allowed */ 388 389 /* ARM11x6 Auxiliary Control Register (CP15 register 1, opcode2 1) */ 390 #define ARM11X6_AUXCTL_RS 0x00000001 /* return stack */ 391 #define ARM11X6_AUXCTL_DB 0x00000002 /* dynamic branch prediction */ 392 #define ARM11X6_AUXCTL_SB 0x00000004 /* static branch prediction */ 393 #define ARM11X6_AUXCTL_TR 0x00000008 /* MicroTLB replacement strat. */ 394 #define ARM11X6_AUXCTL_EX 0x00000010 /* exclusive L1/L2 cache */ 395 #define ARM11X6_AUXCTL_RA 0x00000020 /* clean entire cache disable */ 396 #define ARM11X6_AUXCTL_RV 0x00000040 /* block transfer cache disable */ 397 #define ARM11X6_AUXCTL_CZ 0x00000080 /* restrict cache size */ 398 399 /* ARM1136 Auxiliary Control Register (CP15 register 1, opcode2 1) */ 400 #define ARM1136_AUXCTL_PFI 0x80000000 /* PFI: partial FI mode. */ 401 /* This is an undocumented flag 402 * used to work around a cache bug 403 * in r0 steppings. See errata 404 * 364296. 405 */ 406 /* ARM1176 Auxiliary Control Register (CP15 register 1, opcode2 1) */ 407 #define ARM1176_AUXCTL_PHD 0x10000000 /* inst. prefetch halting disable */ 408 #define ARM1176_AUXCTL_BFD 0x20000000 /* branch folding disable */ 409 #define ARM1176_AUXCTL_FSD 0x40000000 /* force speculative ops disable */ 410 #define ARM1176_AUXCTL_FIO 0x80000000 /* low intr latency override */ 411 412 /* XScale Auxiliary Control Register (CP15 register 1, opcode2 1) */ 413 #define XSCALE_AUXCTL_K 0x00000001 /* dis. write buffer coalescing */ 414 #define XSCALE_AUXCTL_P 0x00000002 /* ECC protect page table access */ 415 #define XSCALE_AUXCTL_MD_WB_RA 0x00000000 /* mini-D$ wb, read-allocate */ 416 #define XSCALE_AUXCTL_MD_WB_RWA 0x00000010 /* mini-D$ wb, read/write-allocate */ 417 #define XSCALE_AUXCTL_MD_WT 0x00000020 /* mini-D$ wt, read-allocate */ 418 #define XSCALE_AUXCTL_MD_MASK 0x00000030 419 420 /* ARM11 MPCore Auxiliary Control Register (CP15 register 1, opcode2 1) */ 421 #define MPCORE_AUXCTL_RS 0x00000001 /* return stack */ 422 #define MPCORE_AUXCTL_DB 0x00000002 /* dynamic branch prediction */ 423 #define MPCORE_AUXCTL_SB 0x00000004 /* static branch prediction */ 424 #define MPCORE_AUXCTL_F 0x00000008 /* instruction folding enable */ 425 #define MPCORE_AUXCTL_EX 0x00000010 /* exclusive L1/L2 cache */ 426 #define MPCORE_AUXCTL_SA 0x00000020 /* SMP/AMP */ 427 428 /* Marvell PJ4B Auxillary Control Register (CP15.0.R1.c0.1) */ 429 #define PJ4B_AUXCTL_FW __BIT(0) /* Cache and TLB updates broadcast */ 430 #define PJ4B_AUXCTL_SMPNAMP __BIT(6) /* 0 = AMP, 1 = SMP */ 431 #define PJ4B_AUXCTL_L1PARITY __BIT(9) /* L1 parity checking */ 432 433 /* Marvell PJ4B Auxialiary Function Modes Control 0 (CP15.1.R15.c2.0) */ 434 #define PJ4B_AUXFMC0_L2EN __BIT(0) /* Tightly-Coupled L2 cache enable */ 435 #define PJ4B_AUXFMC0_SMPNAMP __BIT(1) /* 0 = AMP, 1 = SMP */ 436 #define PJ4B_AUXFMC0_L1PARITY __BIT(2) /* alias of PJ4B_AUXCTL_L1PARITY */ 437 #define PJ4B_AUXFMC0_DCSLFD __BIT(2) /* Disable DC Speculative linefill */ 438 #define PJ4B_AUXFMC0_FW __BIT(8) /* alias of PJ4B_AUXCTL_FW*/ 439 440 /* Cortex-A9 Auxiliary Control Register (CP15 register 1, opcode 1) */ 441 #define CORTEXA9_AUXCTL_FW 0x00000001 /* Cache and TLB updates broadcast */ 442 #define CORTEXA9_AUXCTL_L2PE 0x00000002 /* Prefetch hint enable */ 443 #define CORTEXA9_AUXCTL_L1PE 0x00000004 /* Data prefetch hint enable */ 444 #define CORTEXA9_AUXCTL_WR_ZERO 0x00000008 /* Ena. write full line of 0s mode */ 445 #define CORTEXA9_AUXCTL_SMP 0x00000040 /* Coherency is active */ 446 #define CORTEXA9_AUXCTL_EXCL 0x00000080 /* Exclusive cache bit */ 447 #define CORTEXA9_AUXCTL_ONEWAY 0x00000100 /* Allocate in on cache way only */ 448 #define CORTEXA9_AUXCTL_PARITY 0x00000200 /* Support parity checking */ 449 450 /* Cortex-A15 Auxiliary Control Register (CP15 register 1, opcode 1) */ 451 #define CORTEXA15_ACTLR_BTB __BIT(0) /* Cache and TLB updates broadcast */ 452 #define CORTEXA15_ACTLR_SMP __BIT(6) /* SMP */ 453 #define CORTEXA15_ACTLR_IOBEU __BIT(15) /* In order issue in Branch Exec Unit */ 454 455 /* Marvell Feroceon Extra Features Register (CP15 register 1, opcode2 0) */ 456 #define FC_DCACHE_REPL_LOCK 0x80000000 /* Replace DCache Lock */ 457 #define FC_DCACHE_STREAM_EN 0x20000000 /* DCache Streaming Switch */ 458 #define FC_WR_ALLOC_EN 0x10000000 /* Enable Write Allocate */ 459 #define FC_L2_PREF_DIS 0x01000000 /* L2 Cache Prefetch Disable */ 460 #define FC_L2_INV_EVICT_LINE 0x00800000 /* L2 Invalidates Uncorrectable Error Line Eviction */ 461 #define FC_L2CACHE_EN 0x00400000 /* L2 enable */ 462 #define FC_ICACHE_REPL_LOCK 0x00080000 /* Replace ICache Lock */ 463 #define FC_GLOB_HIST_REG_EN 0x00040000 /* Branch Global History Register Enable */ 464 #define FC_BRANCH_TARG_BUF_DIS 0x00020000 /* Branch Target Buffer Disable */ 465 #define FC_L1_PAR_ERR_EN 0x00010000 /* L1 Parity Error Enable */ 466 467 /* Cache type register definitions 0 */ 468 #define CPU_CT_FORMAT(x) (((x) >> 29) & 0x7) /* reg format */ 469 #define CPU_CT_ISIZE(x) ((x) & 0xfff) /* I$ info */ 470 #define CPU_CT_DSIZE(x) (((x) >> 12) & 0xfff) /* D$ info */ 471 #define CPU_CT_S (1U << 24) /* split cache */ 472 #define CPU_CT_CTYPE(x) (((x) >> 25) & 0xf) /* cache type */ 473 474 #define CPU_CT_CTYPE_WT 0 /* write-through */ 475 #define CPU_CT_CTYPE_WB1 1 /* write-back, clean w/ read */ 476 #define CPU_CT_CTYPE_WB2 2 /* w/b, clean w/ cp15,7 */ 477 #define CPU_CT_CTYPE_WB6 6 /* w/b, cp15,7, lockdown fmt A */ 478 #define CPU_CT_CTYPE_WB7 7 /* w/b, cp15,7, lockdown fmt B */ 479 #define CPU_CT_CTYPE_WB14 14 /* w/b, cp15,7, lockdown fmt C */ 480 481 #define CPU_CT_xSIZE_LEN(x) ((x) & 0x3) /* line size */ 482 #define CPU_CT_xSIZE_M (1U << 2) /* multiplier */ 483 #define CPU_CT_xSIZE_ASSOC(x) (((x) >> 3) & 0x7) /* associativity */ 484 #define CPU_CT_xSIZE_SIZE(x) (((x) >> 6) & 0x7) /* size */ 485 #define CPU_CT_xSIZE_P (1U << 11) /* need to page-color */ 486 487 /* format 4 definitions */ 488 #define CPU_CT4_ILINE(x) ((x) & 0xf) /* I$ line size */ 489 #define CPU_CT4_DLINE(x) (((x) >> 16) & 0xf) /* D$ line size */ 490 #define CPU_CT4_L1IPOLICY(x) (((x) >> 14) & 0x3) /* I$ policy */ 491 #define CPU_CT4_L1_AIVIVT 1 /* ASID tagged VIVT */ 492 #define CPU_CT4_L1_VIPT 2 /* VIPT */ 493 #define CPU_CT4_L1_PIPT 3 /* PIPT */ 494 #define CPU_CT4_ERG(x) (((x) >> 20) & 0xf) /* Cache WriteBack Granule */ 495 #define CPU_CT4_CWG(x) (((x) >> 24) & 0xf) /* Exclusive Resv. Granule */ 496 497 /* Cache size identifaction register definitions 1, Rd, c0, c0, 0 */ 498 #define CPU_CSID_CTYPE_WT 0x80000000 /* write-through avail */ 499 #define CPU_CSID_CTYPE_WB 0x40000000 /* write-back avail */ 500 #define CPU_CSID_CTYPE_RA 0x20000000 /* read-allocation avail */ 501 #define CPU_CSID_CTYPE_WA 0x10000000 /* write-allocation avail */ 502 #define CPU_CSID_NUMSETS(x) (((x) >> 13) & 0x7fff) 503 #define CPU_CSID_ASSOC(x) (((x) >> 3) & 0x1ff) 504 #define CPU_CSID_LEN(x) ((x) & 0x07) 505 506 /* Cache size selection register definitions 2, Rd, c0, c0, 0 */ 507 #define CPU_CSSR_L2 0x00000002 508 #define CPU_CSSR_L1 0x00000000 509 #define CPU_CSSR_InD 0x00000001 510 511 /* Fault status register definitions */ 512 513 #define FAULT_TYPE_MASK 0x0f 514 #define FAULT_USER 0x10 515 516 #define FAULT_WRTBUF_0 0x00 /* Vector Exception */ 517 #define FAULT_WRTBUF_1 0x02 /* Terminal Exception */ 518 #define FAULT_BUSERR_0 0x04 /* External Abort on Linefetch -- Section */ 519 #define FAULT_BUSERR_1 0x06 /* External Abort on Linefetch -- Page */ 520 #define FAULT_BUSERR_2 0x08 /* External Abort on Non-linefetch -- Section */ 521 #define FAULT_BUSERR_3 0x0a /* External Abort on Non-linefetch -- Page */ 522 #define FAULT_BUSTRNL1 0x0c /* External abort on Translation -- Level 1 */ 523 #define FAULT_BUSTRNL2 0x0e /* External abort on Translation -- Level 2 */ 524 #define FAULT_ALIGN_0 0x01 /* Alignment */ 525 #define FAULT_ALIGN_1 0x03 /* Alignment */ 526 #define FAULT_TRANS_S 0x05 /* Translation -- Section */ 527 #define FAULT_TRANS_P 0x07 /* Translation -- Page */ 528 #define FAULT_DOMAIN_S 0x09 /* Domain -- Section */ 529 #define FAULT_DOMAIN_P 0x0b /* Domain -- Page */ 530 #define FAULT_PERM_S 0x0d /* Permission -- Section */ 531 #define FAULT_PERM_P 0x0f /* Permission -- Page */ 532 533 #define FAULT_LPAE 0x0200 /* (SW) used long descriptors */ 534 #define FAULT_IMPRECISE 0x0400 /* Imprecise exception (XSCALE) */ 535 #define FAULT_WRITE 0x0800 /* fault was due to write (ARMv6+) */ 536 #define FAULT_EXT 0x1000 /* fault was due to external abort (ARMv6+) */ 537 #define FAULT_CM 0x2000 /* fault was due to cache maintenance (ARMv7+) */ 538 539 /* 540 * Address of the vector page, low and high versions. 541 */ 542 #define ARM_VECTORS_LOW 0x00000000U 543 #define ARM_VECTORS_HIGH 0xffff0000U 544 545 /* 546 * ARM Instructions 547 * 548 * 3 3 2 2 2 549 * 1 0 9 8 7 0 550 * +-------+-------------------------------------------------------+ 551 * | cond | instruction dependent | 552 * |c c c c| | 553 * +-------+-------------------------------------------------------+ 554 */ 555 556 #define INSN_SIZE 4 /* Always 4 bytes */ 557 #define INSN_COND_MASK 0xf0000000 /* Condition mask */ 558 #define INSN_COND_EQ 0 /* Z == 1 */ 559 #define INSN_COND_NE 1 /* Z == 0 */ 560 #define INSN_COND_CS 2 /* C == 1 */ 561 #define INSN_COND_CC 3 /* C == 0 */ 562 #define INSN_COND_MI 4 /* N == 1 */ 563 #define INSN_COND_PL 5 /* N == 0 */ 564 #define INSN_COND_VS 6 /* V == 1 */ 565 #define INSN_COND_VC 7 /* V == 0 */ 566 #define INSN_COND_HI 8 /* C == 1 && Z == 0 */ 567 #define INSN_COND_LS 9 /* C == 0 || Z == 1 */ 568 #define INSN_COND_GE 10 /* N == V */ 569 #define INSN_COND_LT 11 /* N != V */ 570 #define INSN_COND_GT 12 /* Z == 0 && N == V */ 571 #define INSN_COND_LE 13 /* Z == 1 || N != V */ 572 #define INSN_COND_AL 14 /* Always condition */ 573 574 #define THUMB_INSN_SIZE 2 /* Some are 4 bytes. */ 575 576 /* 577 * Defines and such for arm11 Performance Monitor Counters (p15, c15, c12, 0) 578 */ 579 #define ARM11_PMCCTL_E __BIT(0) /* enable all three counters */ 580 #define ARM11_PMCCTL_P __BIT(1) /* reset both Count Registers to zero */ 581 #define ARM11_PMCCTL_C __BIT(2) /* reset the Cycle Counter Register to zero */ 582 #define ARM11_PMCCTL_D __BIT(3) /* cycle count divide by 64 */ 583 #define ARM11_PMCCTL_EC0 __BIT(4) /* Enable Counter Register 0 interrupt */ 584 #define ARM11_PMCCTL_EC1 __BIT(5) /* Enable Counter Register 1 interrupt */ 585 #define ARM11_PMCCTL_ECC __BIT(6) /* Enable Cycle Counter interrupt */ 586 #define ARM11_PMCCTL_SBZa __BIT(7) /* UNP/SBZ */ 587 #define ARM11_PMCCTL_CR0 __BIT(8) /* Count Register 0 overflow flag */ 588 #define ARM11_PMCCTL_CR1 __BIT(9) /* Count Register 1 overflow flag */ 589 #define ARM11_PMCCTL_CCR __BIT(10) /* Cycle Count Register overflow flag */ 590 #define ARM11_PMCCTL_X __BIT(11) /* Enable Export of the events to the event bus */ 591 #define ARM11_PMCCTL_EVT1 __BITS(19,12) /* source of events for Count Register 1 */ 592 #define ARM11_PMCCTL_EVT0 __BITS(27,20) /* source of events for Count Register 0 */ 593 #define ARM11_PMCCTL_SBZb __BITS(31,28) /* UNP/SBZ */ 594 #define ARM11_PMCCTL_SBZ \ 595 (ARM11_PMCCTL_SBZa | ARM11_PMCCTL_SBZb) 596 597 #define ARM11_PMCEVT_ICACHE_MISS 0 /* Instruction Cache Miss */ 598 #define ARM11_PMCEVT_ISTREAM_STALL 1 /* Instruction Stream Stall */ 599 #define ARM11_PMCEVT_IUTLB_MISS 2 /* Instruction uTLB Miss */ 600 #define ARM11_PMCEVT_DUTLB_MISS 3 /* Data uTLB Miss */ 601 #define ARM11_PMCEVT_BRANCH 4 /* Branch Inst. Executed */ 602 #define ARM11_PMCEVT_BRANCH_MISS 6 /* Branch mispredicted */ 603 #define ARM11_PMCEVT_INST_EXEC 7 /* Instruction Executed */ 604 #define ARM11_PMCEVT_DCACHE_ACCESS0 9 /* Data Cache Access */ 605 #define ARM11_PMCEVT_DCACHE_ACCESS1 10 /* Data Cache Access */ 606 #define ARM11_PMCEVT_DCACHE_MISS 11 /* Data Cache Miss */ 607 #define ARM11_PMCEVT_DCACHE_WRITEBACK 12 /* Data Cache Writeback */ 608 #define ARM11_PMCEVT_PC_CHANGE 13 /* Software PC change */ 609 #define ARM11_PMCEVT_TLB_MISS 15 /* Main TLB Miss */ 610 #define ARM11_PMCEVT_DATA_ACCESS 16 /* non-cached data access */ 611 #define ARM11_PMCEVT_LSU_STALL 17 /* Load/Store Unit stall */ 612 #define ARM11_PMCEVT_WBUF_DRAIN 18 /* Write buffer drained */ 613 #define ARM11_PMCEVT_ETMEXTOUT0 32 /* ETMEXTOUT[0] asserted */ 614 #define ARM11_PMCEVT_ETMEXTOUT1 33 /* ETMEXTOUT[1] asserted */ 615 #define ARM11_PMCEVT_ETMEXTOUT 34 /* ETMEXTOUT[0 & 1] */ 616 #define ARM11_PMCEVT_CALL_EXEC 35 /* Procedure call executed */ 617 #define ARM11_PMCEVT_RETURN_EXEC 36 /* Return executed */ 618 #define ARM11_PMCEVT_RETURN_HIT 37 /* return address predicted */ 619 #define ARM11_PMCEVT_RETURN_MISS 38 /* return addr. mispredicted */ 620 #define ARM11_PMCEVT_CYCLE 255 /* Increment each cycle */ 621 622 /* Defines for ARM CORTEX performance counters */ 623 #define CORTEX_CNTENS_C __BIT(31) /* Enables the cycle counter */ 624 #define CORTEX_CNTENC_C __BIT(31) /* Disables the cycle counter */ 625 #define CORTEX_CNTOFL_C __BIT(31) /* Cycle counter overflow flag */ 626 627 /* Defines for ARM Cortex A7/A15 L2CTRL */ 628 #define L2CTRL_NUMCPU __BITS(25,24) // numcpus - 1 629 #define L2CTRL_ICPRES __BIT(23) // Interrupt Controller is present 630 631 /* Translation Table Base Register */ 632 #define TTBR_C __BIT(0) /* without MPE */ 633 #define TTBR_S __BIT(1) 634 #define TTBR_IMP __BIT(2) 635 #define TTBR_RGN_MASK __BITS(4,3) 636 #define TTBR_RGN_NC __SHIFTIN(0, TTBR_RGN_MASK) 637 #define TTBR_RGN_WBWA __SHIFTIN(1, TTBR_RGN_MASK) 638 #define TTBR_RGN_WT __SHIFTIN(2, TTBR_RGN_MASK) 639 #define TTBR_RGN_WBNWA __SHIFTIN(3, TTBR_RGN_MASK) 640 #define TTBR_NOS __BIT(5) 641 #define TTBR_IRGN_MASK (__BIT(6) | __BIT(0)) 642 #define TTBR_IRGN_NC 0 643 #define TTBR_IRGN_WBWA __BIT(6) 644 #define TTBR_IRGN_WT __BIT(0) 645 #define TTBR_IRGN_WBNWA (__BIT(0) | __BIT(6)) 646 647 /* Translate Table Base Control Register */ 648 #define TTBCR_S_EAE __BIT(31) // Extended Address Extension 649 #define TTBCR_S_PD1 __BIT(5) // Don't use TTBR1 650 #define TTBCR_S_PD0 __BIT(4) // Don't use TTBR0 651 #define TTBCR_S_N __BITS(2,0) // Width of base address in TTB0 652 653 #define TTBCR_L_EAE __BIT(31) // Extended Address Extension 654 #define TTBCR_L_SH1 __BITS(29,28) // TTBR1 Shareability 655 #define TTBCR_L_ORGN1 __BITS(27,26) // TTBR1 Outer cacheability 656 #define TTBCR_L_IRGN1 __BITS(25,24) // TTBR1 inner cacheability 657 #define TTBCR_L_EPD1 __BIT(23) // Don't use TTBR1 658 #define TTBCR_L_A1 __BIT(22) // ASID is in TTBR1 659 #define TTBCR_L_T1SZ __BITS(18,16) // TTBR1 size offset 660 #define TTBCR_L_SH0 __BITS(13,12) // TTBR0 Shareability 661 #define TTBCR_L_ORGN0 __BITS(11,10) // TTBR0 Outer cacheability 662 #define TTBCR_L_IRGN0 __BITS(9,8) // TTBR0 inner cacheability 663 #define TTBCR_L_EPD0 __BIT(7) // Don't use TTBR0 664 #define TTBCR_L_T0SZ __BITS(2,0) // TTBR0 size offset 665 666 #define NRRR_ORn(n) __BITS(17+2*(n),16+2*(n)) // Outer Cacheable mappings 667 #define NRRR_IRn(n) __BITS(1+2*(n),0+2*(n)) // Inner Cacheable mappings 668 #define NRRR_NC 0 // non-cacheable 669 #define NRRR_WB_WA 1 // write-back write-allocate 670 #define NRRR_WT 2 // write-through 671 #define NRRR_WB 3 // write-back 672 #define PRRR_NOSn(n) __BITS(24+2*(n))// Memory region is Inner Shareable 673 #define PRRR_NS1 __BIT(19) // Normal Shareable S=1 is Shareable 674 #define PRRR_NS0 __BIT(18) // Normal Shareable S=0 is Shareable 675 #define PRRR_DS1 __BIT(17) // Device Shareable S=1 is Shareable 676 #define PRRR_DS0 __BIT(16) // Device Shareable S=0 is Shareable 677 #define PRRR_TRn(n) __BITS(1+2*(n),0+2*(n)) 678 #define PRRR_TR_STRONG 0 // Strongly Ordered 679 #define PRRR_TR_DEVICE 1 // Device 680 #define PRRR_TR_NORMAL 2 // Normal Memory 681 682 /* ARMv7 MPIDR, Multiprocessor Affinity Register generic format */ 683 #define MPIDR_MP __BIT(31) /* 1 = Have MP Extention */ 684 #define MPIDR_U __BIT(30) /* 1 = Uni-Processor System */ 685 #define MPIDR_MT __BIT(24) /* 1 = SMT(AFF0 is logical) */ 686 #define MPIDR_AFF2 __BITS(23,16) /* Affinity Level 2 */ 687 #define MPIDR_AFF1 __BITS(15,8) /* Affinity Level 1 */ 688 #define MPIDR_AFF0 __BITS(7,0) /* Affinity Level 0 */ 689 690 /* MPIDR implementation of ARM Cortex A9: SMT and AFF2 is not used */ 691 #define CORTEXA9_MPIDR_MP MPIDR_MP 692 #define CORTEXA9_MPIDR_U MPIDR_U 693 #define CORTEXA9_MPIDR_CLID __BITS(11,8) /* AFF1 = cluster id */ 694 #define CORTEXA9_MPIDR_CPUID __BITS(0,1) /* AFF0 = physical core id */ 695 696 /* MPIDR implementation of Marvell PJ4B-MP: AFF2 is not used */ 697 #define PJ4B_MPIDR_MP MPIDR_MP 698 #define PJ4B_MPIDR_U MPIDR_U 699 #define PJ4B_MPIDR_MT MPIDR_MT /* 1 = SMT(AFF0 is logical) */ 700 #define PJ4B_MPIDR_CLID __BITS(11,8) /* AFF1 = cluster id */ 701 #define PJ4B_MPIDR_CPUID __BITS(0,3) /* AFF0 = core id */ 702 703 /* Defines for ARM Generic Timer */ 704 #define ARM_CNTCTL_ISTATUS __BIT(2) // Interrupt is pending 705 #define ARM_CNTCTL_IMASK __BIT(1) // Mask Interrupt 706 #define ARM_CNTCTL_ENABLE __BIT(0) // Timer Enabled 707 708 #define ARM_CNTKCTL_PL0PTEN __BIT(9) /* PL0 Physical Timer Enable */ 709 #define ARM_CNTKCTL_PL0VTEN __BIT(8) /* PL0 Virtual Timer Enable */ 710 #define ARM_CNTKCTL_EVNTI __BITS(7,4) /* CNTVCT Event Bit Select */ 711 #define ARM_CNTKCTL_EVNTDIR __BIT(3) /* CNTVCT Event Dir (1->0) */ 712 #define ARM_CNTKCTL_EVNTEN __BIT(2) /* CNTVCT Event Enable */ 713 #define ARM_CNTKCTL_PL0VCTEN __BIT(1) /* PL0 Virtual Counter Enable */ 714 #define ARM_CNTKCTL_PL0PCTEN __BIT(0) /* PL0 Physical Counter Enable */ 715 716 /* CNCHCTL, Timer PL2 Control register, Virtualization Extensions */ 717 #define ARM_CNTHCTL_EVNTI __BITS(7,4) 718 #define ARM_CNTHCTL_EVNTDIR __BIT(3) 719 #define ARM_CNTHCTL_EVNTEN __BIT(2) 720 #define ARM_CNTHCTL_PL1PCEN __BIT(1) 721 #define ARM_CNTHCTL_PL1PCTEN __BIT(0) 722 723 #define ARM_A5_TLBDATA_DOM __BITS(62,59) 724 #define ARM_A5_TLBDATA_AP __BITS(58,56) 725 #define ARM_A5_TLBDATA_NS_WALK __BIT(55) 726 #define ARM_A5_TLBDATA_NS_PAGE __BIT(54) 727 #define ARM_A5_TLBDATA_XN __BIT(53) 728 #define ARM_A5_TLBDATA_TEX __BITS(52,50) 729 #define ARM_A5_TLBDATA_B __BIT(49) 730 #define ARM_A5_TLBDATA_C __BIT(48) 731 #define ARM_A5_TLBDATA_S __BIT(47) 732 #define ARM_A5_TLBDATA_ASID __BITS(46,39) 733 #define ARM_A5_TLBDATA_SIZE __BITS(38,37) 734 #define ARM_A5_TLBDATA_SIZE_4KB 0 735 #define ARM_A5_TLBDATA_SIZE_16KB 1 736 #define ARM_A5_TLBDATA_SIZE_1MB 2 737 #define ARM_A5_TLBDATA_SIZE_16MB 3 738 #define ARM_A5_TLBDATA_VA __BITS(36,22) 739 #define ARM_A5_TLBDATA_PA __BITS(21,2) 740 #define ARM_A5_TLBDATA_nG __BIT(1) 741 #define ARM_A5_TLBDATA_VALID __BIT(0) 742 743 #define ARM_A7_TLBDATA2_S2_LEVEL __BITS(85-64,84-64) 744 #define ARM_A7_TLBDATA2_S1_SIZE __BITS(83-64,82-64) 745 #define ARM_A7_TLBDATA2_S1_SIZE_4KB 0 746 #define ARM_A7_TLBDATA2_S1_SIZE_64KB 1 747 #define ARM_A7_TLBDATA2_S1_SIZE_1MB 2 748 #define ARM_A7_TLBDATA2_S1_SIZE_16MB 3 749 #define ARM_A7_TLBDATA2_DOM __BITS(81-64,78-64) 750 #define ARM_A7_TLBDATA2_IS __BITS(77-64,76-64) 751 #define ARM_A7_TLBDATA2_IS_NC 0 752 #define ARM_A7_TLBDATA2_IS_WB_WA 1 753 #define ARM_A7_TLBDATA2_IS_WT 2 754 #define ARM_A7_TLBDATA2_IS_DSO 3 755 #define ARM_A7_TLBDATA2_S2OVR __BIT(75-64) 756 #define ARM_A7_TLBDATA2_SDO_MT __BITS(74-64,72-64) 757 #define ARM_A7_TLBDATA2_SDO_MT_D 2 758 #define ARM_A7_TLBDATA2_SDO_MT_SO 6 759 #define ARM_A7_TLBDATA2_OS __BITS(75-64,74-64) 760 #define ARM_A7_TLBDATA2_OS_NC 0 761 #define ARM_A7_TLBDATA2_OS_WB_WA 1 762 #define ARM_A7_TLBDATA2_OS_WT 2 763 #define ARM_A7_TLBDATA2_OS_WB 3 764 #define ARM_A7_TLBDATA2_SH __BITS(73-64,72-64) 765 #define ARM_A7_TLBDATA2_SH_NONE 0 766 #define ARM_A7_TLBDATA2_SH_UNUSED 1 767 #define ARM_A7_TLBDATA2_SH_OS 2 768 #define ARM_A7_TLBDATA2_SH_IS 3 769 #define ARM_A7_TLBDATA2_XN2 __BIT(71-64) 770 #define ARM_A7_TLBDATA2_XN1 __BIT(70-64) 771 #define ARM_A7_TLBDATA2_PXN __BIT(69-64) 772 773 #define ARM_A7_TLBDATA12_PA __BITS(68-32,41-32) 774 775 #define ARM_A7_TLBDATA1_NS __BIT(40-32) 776 #define ARM_A7_TLBDATA1_HAP __BITS(39-32,38-32) 777 #define ARM_A7_TLBDATA1_AP __BITS(37-32,35-32) 778 #define ARM_A7_TLBDATA1_nG __BIT(34-32) 779 780 #define ARM_A7_TLBDATA01_ASID __BITS(33,26) 781 782 #define ARM_A7_TLBDATA0_VMID __BITS(25,18) 783 #define ARM_A7_TLBDATA0_VA __BITS(17,5) 784 #define ARM_A7_TLBDATA0_NS_WALK __BIT(4) 785 #define ARM_A7_TLBDATA0_SIZE __BITS(3,1) 786 #define ARM_A7_TLBDATA0_SIZE_V7_4KB 0 787 #define ARM_A7_TLBDATA0_SIZE_LPAE_4KB 1 788 #define ARM_A7_TLBDATA0_SIZE_V7_64KB 2 789 #define ARM_A7_TLBDATA0_SIZE_LPAE_64KB 3 790 #define ARM_A7_TLBDATA0_SIZE_V7_1MB 4 791 #define ARM_A7_TLBDATA0_SIZE_LPAE_2MB 5 792 #define ARM_A7_TLBDATA0_SIZE_V7_16MB 6 793 #define ARM_A7_TLBDATA0_SIZE_LPAE_1GB 7 794 795 #define ARM_TLBDATA_VALID __BIT(0) 796 797 #define ARM_TLBDATAOP_WAY __BIT(31) 798 #define ARM_A5_TLBDATAOP_INDEX __BITS(5,0) 799 #define ARM_A7_TLBDATAOP_INDEX __BITS(6,0) 800 801 #if !defined(__ASSEMBLER__) && defined(_KERNEL) 802 static inline bool 803 arm_cond_ok_p(uint32_t insn, uint32_t psr) 804 { 805 const uint32_t __cond = __SHIFTOUT(insn, INSN_COND_MASK); 806 807 bool __ok; 808 const bool __z = (psr & PSR_Z_bit); 809 const bool __n = (psr & PSR_N_bit); 810 const bool __c = (psr & PSR_C_bit); 811 const bool __v = (psr & PSR_V_bit); 812 switch (__cond & ~1) { 813 case INSN_COND_EQ: // Z == 1 814 __ok = __z; 815 break; 816 case INSN_COND_CS: // C == 1 817 __ok = __c; 818 break; 819 case INSN_COND_MI: // N == 1 820 __ok = __n; 821 break; 822 case INSN_COND_VS: // V == 1 823 __ok = __v; 824 break; 825 case INSN_COND_HI: // C == 1 && Z == 0 826 __ok = __c && !__z; 827 break; 828 case INSN_COND_GE: // N == V 829 __ok = __n == __v; 830 break; 831 case INSN_COND_GT: // N == V && Z == 0 832 __ok = __n == __v && !__z; 833 break; 834 default: /* INSN_COND_AL or unconditional */ 835 return true; 836 } 837 838 return (__cond & 1) ? !__ok : __ok; 839 } 840 #endif /* !__ASSEMBLER && _KERNEL */ 841 842 #if !defined(__ASSEMBLER__) && !defined(_RUMPKERNEL) 843 #define ARMREG_READ_INLINE(name, __insnstring) \ 844 static inline uint32_t armreg_##name##_read(void) \ 845 { \ 846 uint32_t __rv; \ 847 __asm __volatile("mrc " __insnstring : "=r"(__rv)); \ 848 return __rv; \ 849 } 850 851 #define ARMREG_WRITE_INLINE(name, __insnstring) \ 852 static inline void armreg_##name##_write(uint32_t __val) \ 853 { \ 854 __asm __volatile("mcr " __insnstring :: "r"(__val)); \ 855 } 856 857 #define ARMREG_READ_INLINE2(name, __insnstring) \ 858 static inline uint32_t armreg_##name##_read(void) \ 859 { \ 860 uint32_t __rv; \ 861 __asm __volatile(".fpu vfp"); \ 862 __asm __volatile(__insnstring : "=r"(__rv)); \ 863 return __rv; \ 864 } 865 866 #define ARMREG_WRITE_INLINE2(name, __insnstring) \ 867 static inline void armreg_##name##_write(uint32_t __val) \ 868 { \ 869 __asm __volatile(".fpu vfp"); \ 870 __asm __volatile(__insnstring :: "r"(__val)); \ 871 } 872 873 #define ARMREG_READ64_INLINE(name, __insnstring) \ 874 static inline uint64_t armreg_##name##_read(void) \ 875 { \ 876 uint64_t __rv; \ 877 __asm __volatile("mrrc " __insnstring : "=r"(__rv)); \ 878 return __rv; \ 879 } 880 881 #define ARMREG_WRITE64_INLINE(name, __insnstring) \ 882 static inline void armreg_##name##_write(uint64_t __val) \ 883 { \ 884 __asm __volatile("mcrr " __insnstring :: "r"(__val)); \ 885 } 886 887 /* cp10 registers */ 888 ARMREG_READ_INLINE2(fpsid, "vmrs\t%0, fpsid") /* VFP System ID */ 889 ARMREG_READ_INLINE2(fpscr, "vmrs\t%0, fpscr") /* VFP Status/Control Register */ 890 ARMREG_WRITE_INLINE2(fpscr, "vmsr\tfpscr, %0") /* VFP Status/Control Register */ 891 ARMREG_READ_INLINE2(mvfr1, "vmrs\t%0, mvfr1") /* Media and VFP Feature Register 1 */ 892 ARMREG_READ_INLINE2(mvfr0, "vmrs\t%0, mvfr0") /* Media and VFP Feature Register 0 */ 893 ARMREG_READ_INLINE2(fpexc, "vmrs\t%0, fpexc") /* VFP Exception Register */ 894 ARMREG_WRITE_INLINE2(fpexc, "vmsr\tfpexc, %0") /* VFP Exception Register */ 895 ARMREG_READ_INLINE2(fpinst, "fmrx\t%0, fpinst") /* VFP Exception Instruction */ 896 ARMREG_WRITE_INLINE2(fpinst, "fmxr\tfpinst, %0") /* VFP Exception Instruction */ 897 ARMREG_READ_INLINE2(fpinst2, "fmrx\t%0, fpinst2") /* VFP Exception Instruction 2 */ 898 ARMREG_WRITE_INLINE2(fpinst2, "fmxr\tfpinst2, %0") /* VFP Exception Instruction 2 */ 899 900 /* cp15 c0 registers */ 901 ARMREG_READ_INLINE(midr, "p15,0,%0,c0,c0,0") /* Main ID Register */ 902 ARMREG_READ_INLINE(ctr, "p15,0,%0,c0,c0,1") /* Cache Type Register */ 903 ARMREG_READ_INLINE(tlbtr, "p15,0,%0,c0,c0,3") /* TLB Type Register */ 904 ARMREG_READ_INLINE(mpidr, "p15,0,%0,c0,c0,5") /* Multiprocess Affinity Register */ 905 ARMREG_READ_INLINE(revidr, "p15,0,%0,c0,c0,6") /* Revision ID Register */ 906 ARMREG_READ_INLINE(pfr0, "p15,0,%0,c0,c1,0") /* Processor Feature Register 0 */ 907 ARMREG_READ_INLINE(pfr1, "p15,0,%0,c0,c1,1") /* Processor Feature Register 1 */ 908 ARMREG_READ_INLINE(mmfr0, "p15,0,%0,c0,c1,4") /* Memory Model Feature Register 0 */ 909 ARMREG_READ_INLINE(mmfr1, "p15,0,%0,c0,c1,5") /* Memory Model Feature Register 1 */ 910 ARMREG_READ_INLINE(mmfr2, "p15,0,%0,c0,c1,6") /* Memory Model Feature Register 2 */ 911 ARMREG_READ_INLINE(mmfr3, "p15,0,%0,c0,c1,7") /* Memory Model Feature Register 3 */ 912 ARMREG_READ_INLINE(isar0, "p15,0,%0,c0,c2,0") /* Instruction Set Attribute Register 0 */ 913 ARMREG_READ_INLINE(isar1, "p15,0,%0,c0,c2,1") /* Instruction Set Attribute Register 1 */ 914 ARMREG_READ_INLINE(isar2, "p15,0,%0,c0,c2,2") /* Instruction Set Attribute Register 2 */ 915 ARMREG_READ_INLINE(isar3, "p15,0,%0,c0,c2,3") /* Instruction Set Attribute Register 3 */ 916 ARMREG_READ_INLINE(isar4, "p15,0,%0,c0,c2,4") /* Instruction Set Attribute Register 4 */ 917 ARMREG_READ_INLINE(isar5, "p15,0,%0,c0,c2,5") /* Instruction Set Attribute Register 5 */ 918 ARMREG_READ_INLINE(ccsidr, "p15,1,%0,c0,c0,0") /* Cache Size ID Register */ 919 ARMREG_READ_INLINE(clidr, "p15,1,%0,c0,c0,1") /* Cache Level ID Register */ 920 ARMREG_READ_INLINE(csselr, "p15,2,%0,c0,c0,0") /* Cache Size Selection Register */ 921 ARMREG_WRITE_INLINE(csselr, "p15,2,%0,c0,c0,0") /* Cache Size Selection Register */ 922 /* cp15 c1 registers */ 923 ARMREG_READ_INLINE(sctlr, "p15,0,%0,c1,c0,0") /* System Control Register */ 924 ARMREG_WRITE_INLINE(sctlr, "p15,0,%0,c1,c0,0") /* System Control Register */ 925 ARMREG_READ_INLINE(auxctl, "p15,0,%0,c1,c0,1") /* Auxiliary Control Register */ 926 ARMREG_WRITE_INLINE(auxctl, "p15,0,%0,c1,c0,1") /* Auxiliary Control Register */ 927 ARMREG_READ_INLINE(cpacr, "p15,0,%0,c1,c0,2") /* Co-Processor Access Control Register */ 928 ARMREG_WRITE_INLINE(cpacr, "p15,0,%0,c1,c0,2") /* Co-Processor Access Control Register */ 929 ARMREG_READ_INLINE(scr, "p15,0,%0,c1,c1,0") /* Secure Configuration Register */ 930 ARMREG_READ_INLINE(nsacr, "p15,0,%0,c1,c1,2") /* Non-Secure Access Control Register */ 931 /* cp15 c2 registers */ 932 ARMREG_READ_INLINE(ttbr, "p15,0,%0,c2,c0,0") /* Translation Table Base Register 0 */ 933 ARMREG_WRITE_INLINE(ttbr, "p15,0,%0,c2,c0,0") /* Translation Table Base Register 0 */ 934 ARMREG_READ_INLINE(ttbr1, "p15,0,%0,c2,c0,1") /* Translation Table Base Register 1 */ 935 ARMREG_WRITE_INLINE(ttbr1, "p15,0,%0,c2,c0,1") /* Translation Table Base Register 1 */ 936 ARMREG_READ_INLINE(ttbcr, "p15,0,%0,c2,c0,2") /* Translation Table Base Register */ 937 ARMREG_WRITE_INLINE(ttbcr, "p15,0,%0,c2,c0,2") /* Translation Table Base Register */ 938 /* cp15 c3 registers */ 939 ARMREG_READ_INLINE(dacr, "p15,0,%0,c3,c0,0") /* Domain Access Control Register */ 940 ARMREG_WRITE_INLINE(dacr, "p15,0,%0,c3,c0,0") /* Domain Access Control Register */ 941 /* cp15 c5 registers */ 942 ARMREG_READ_INLINE(dfsr, "p15,0,%0,c5,c0,0") /* Data Fault Status Register */ 943 ARMREG_READ_INLINE(ifsr, "p15,0,%0,c5,c0,1") /* Instruction Fault Status Register */ 944 /* cp15 c6 registers */ 945 ARMREG_READ_INLINE(dfar, "p15,0,%0,c6,c0,0") /* Data Fault Address Register */ 946 ARMREG_READ_INLINE(ifar, "p15,0,%0,c6,c0,2") /* Instruction Fault Address Register */ 947 /* cp15 c7 registers */ 948 ARMREG_WRITE_INLINE(icialluis, "p15,0,%0,c7,c1,0") /* Instruction Inv All (IS) */ 949 ARMREG_WRITE_INLINE(bpiallis, "p15,0,%0,c7,c1,6") /* Branch Predictor Invalidate All (IS) */ 950 ARMREG_READ_INLINE(par, "p15,0,%0,c7,c4,0") /* Physical Address Register */ 951 ARMREG_WRITE_INLINE(iciallu, "p15,0,%0,c7,c5,0") /* Instruction Invalidate All */ 952 ARMREG_WRITE_INLINE(icimvau, "p15,0,%0,c7,c5,1") /* Instruction Invalidate MVA */ 953 ARMREG_WRITE_INLINE(isb, "p15,0,%0,c7,c5,4") /* Instruction Synchronization Barrier */ 954 ARMREG_WRITE_INLINE(bpiall, "p15,0,%0,c7,c5,6") /* Branch Predictor Invalidate All */ 955 ARMREG_WRITE_INLINE(bpimva, "p15,0,%0,c7,c5,7") /* Branch Predictor invalidate by MVA */ 956 ARMREG_WRITE_INLINE(dcimvac, "p15,0,%0,c7,c6,1") /* Data Invalidate MVA to PoC */ 957 ARMREG_WRITE_INLINE(dcisw, "p15,0,%0,c7,c6,2") /* Data Invalidate Set/Way */ 958 ARMREG_WRITE_INLINE(ats1cpr, "p15,0,%0,c7,c8,0") /* AddrTrans CurState PL1 Read */ 959 ARMREG_WRITE_INLINE(ats1cpw, "p15,0,%0,c7,c8,1") /* AddrTrans CurState PL1 Write */ 960 ARMREG_WRITE_INLINE(ats1cur, "p15,0,%0,c7,c8,2") /* AddrTrans CurState PL0 Read */ 961 ARMREG_WRITE_INLINE(ats1cuw, "p15,0,%0,c7,c8,3") /* AddrTrans CurState PL0 Write */ 962 ARMREG_WRITE_INLINE(dccmvac, "p15,0,%0,c7,c10,1") /* Data Clean MVA to PoC */ 963 ARMREG_WRITE_INLINE(dccsw, "p15,0,%0,c7,c10,2") /* Data Clean Set/Way */ 964 ARMREG_WRITE_INLINE(dsb, "p15,0,%0,c7,c10,4") /* Data Synchronization Barrier */ 965 ARMREG_WRITE_INLINE(dmb, "p15,0,%0,c7,c10,5") /* Data Memory Barrier */ 966 ARMREG_WRITE_INLINE(dccmvau, "p15,0,%0,c7,c11,1") /* Data Clean MVA to PoU */ 967 ARMREG_WRITE_INLINE(dccimvac, "p15,0,%0,c7,c14,1") /* Data Clean&Inv MVA to PoC */ 968 ARMREG_WRITE_INLINE(dccisw, "p15,0,%0,c7,c14,2") /* Data Clean&Inv Set/Way */ 969 /* cp15 c8 registers */ 970 ARMREG_WRITE_INLINE(tlbiallis, "p15,0,%0,c8,c3,0") /* Invalidate entire unified TLB, inner shareable */ 971 ARMREG_WRITE_INLINE(tlbimvais, "p15,0,%0,c8,c3,1") /* Invalidate unified TLB by MVA, inner shareable */ 972 ARMREG_WRITE_INLINE(tlbiasidis, "p15,0,%0,c8,c3,2") /* Invalidate unified TLB by ASID, inner shareable */ 973 ARMREG_WRITE_INLINE(tlbimvaais, "p15,0,%0,c8,c3,3") /* Invalidate unified TLB by MVA, all ASID, inner shareable */ 974 ARMREG_WRITE_INLINE(itlbiall, "p15,0,%0,c8,c5,0") /* Invalidate entire instruction TLB */ 975 ARMREG_WRITE_INLINE(itlbimva, "p15,0,%0,c8,c5,1") /* Invalidate instruction TLB by MVA */ 976 ARMREG_WRITE_INLINE(itlbiasid, "p15,0,%0,c8,c5,2") /* Invalidate instruction TLB by ASID */ 977 ARMREG_WRITE_INLINE(dtlbiall, "p15,0,%0,c8,c6,0") /* Invalidate entire data TLB */ 978 ARMREG_WRITE_INLINE(dtlbimva, "p15,0,%0,c8,c6,1") /* Invalidate data TLB by MVA */ 979 ARMREG_WRITE_INLINE(dtlbiasid, "p15,0,%0,c8,c6,2") /* Invalidate data TLB by ASID */ 980 ARMREG_WRITE_INLINE(tlbiall, "p15,0,%0,c8,c7,0") /* Invalidate entire unified TLB */ 981 ARMREG_WRITE_INLINE(tlbimva, "p15,0,%0,c8,c7,1") /* Invalidate unified TLB by MVA */ 982 ARMREG_WRITE_INLINE(tlbiasid, "p15,0,%0,c8,c7,2") /* Invalidate unified TLB by ASID */ 983 ARMREG_WRITE_INLINE(tlbimvaa, "p15,0,%0,c8,c7,3") /* Invalidate unified TLB by MVA, all ASID */ 984 /* cp15 c9 registers */ 985 ARMREG_READ_INLINE(pmcr, "p15,0,%0,c9,c12,0") /* PMC Control Register */ 986 ARMREG_WRITE_INLINE(pmcr, "p15,0,%0,c9,c12,0") /* PMC Control Register */ 987 ARMREG_READ_INLINE(pmcntenset, "p15,0,%0,c9,c12,1") /* PMC Count Enable Set */ 988 ARMREG_WRITE_INLINE(pmcntenset, "p15,0,%0,c9,c12,1") /* PMC Count Enable Set */ 989 ARMREG_READ_INLINE(pmcntenclr, "p15,0,%0,c9,c12,2") /* PMC Count Enable Clear */ 990 ARMREG_WRITE_INLINE(pmcntenclr, "p15,0,%0,c9,c12,2") /* PMC Count Enable Clear */ 991 ARMREG_READ_INLINE(pmovsr, "p15,0,%0,c9,c12,3") /* PMC Overflow Flag Status */ 992 ARMREG_WRITE_INLINE(pmovsr, "p15,0,%0,c9,c12,3") /* PMC Overflow Flag Status */ 993 ARMREG_READ_INLINE(pmccntr, "p15,0,%0,c9,c13,0") /* PMC Cycle Counter */ 994 ARMREG_WRITE_INLINE(pmccntr, "p15,0,%0,c9,c13,0") /* PMC Cycle Counter */ 995 ARMREG_READ_INLINE(pmuserenr, "p15,0,%0,c9,c14,0") /* PMC User Enable */ 996 ARMREG_WRITE_INLINE(pmuserenr, "p15,0,%0,c9,c14,0") /* PMC User Enable */ 997 ARMREG_READ_INLINE(pmintenset, "p15,0,%0,c9,c14,1") /* PMC Interrupt Enable Set */ 998 ARMREG_WRITE_INLINE(pmintenset, "p15,0,%0,c9,c14,1") /* PMC Interrupt Enable Set */ 999 ARMREG_READ_INLINE(pmintenclr, "p15,0,%0,c9,c14,2") /* PMC Interrupt Enable Clear */ 1000 ARMREG_WRITE_INLINE(pmintenclr, "p15,0,%0,c9,c14,2") /* PMC Interrupt Enable Clear */ 1001 ARMREG_READ_INLINE(l2ctrl, "p15,1,%0,c9,c0,2") /* A7/A15 L2 Control Register */ 1002 /* cp10 c10 registers */ 1003 ARMREG_READ_INLINE(prrr, "p15,0,%0,c10,c2,0") /* Primary Region Remap Register */ 1004 ARMREG_WRITE_INLINE(prrr, "p15,0,%0,c10,c2,0") /* Primary Region Remap Register */ 1005 ARMREG_READ_INLINE(nrrr, "p15,0,%0,c10,c2,1") /* Normal Region Remap Register */ 1006 ARMREG_WRITE_INLINE(nrrr, "p15,0,%0,c10,c2,1") /* Normal Region Remap Register */ 1007 /* cp15 c13 registers */ 1008 ARMREG_READ_INLINE(contextidr, "p15,0,%0,c13,c0,1") /* Context ID Register */ 1009 ARMREG_WRITE_INLINE(contextidr, "p15,0,%0,c13,c0,1") /* Context ID Register */ 1010 ARMREG_READ_INLINE(tpidrurw, "p15,0,%0,c13,c0,2") /* User read-write Thread ID Register */ 1011 ARMREG_WRITE_INLINE(tpidrurw, "p15,0,%0,c13,c0,2") /* User read-write Thread ID Register */ 1012 ARMREG_READ_INLINE(tpidruro, "p15,0,%0,c13,c0,3") /* User read-only Thread ID Register */ 1013 ARMREG_WRITE_INLINE(tpidruro, "p15,0,%0,c13,c0,3") /* User read-only Thread ID Register */ 1014 ARMREG_READ_INLINE(tpidrprw, "p15,0,%0,c13,c0,4") /* PL1 only Thread ID Register */ 1015 ARMREG_WRITE_INLINE(tpidrprw, "p15,0,%0,c13,c0,4") /* PL1 only Thread ID Register */ 1016 /* cp14 c12 registers */ 1017 ARMREG_READ_INLINE(vbar, "p15,0,%0,c12,c0,0") /* Vector Base Address Register */ 1018 ARMREG_WRITE_INLINE(vbar, "p15,0,%0,c12,c0,0") /* Vector Base Address Register */ 1019 /* cp15 c14 registers */ 1020 /* cp15 Global Timer Registers */ 1021 ARMREG_READ_INLINE(cnt_frq, "p15,0,%0,c14,c0,0") /* Counter Frequency Register */ 1022 ARMREG_WRITE_INLINE(cnt_frq, "p15,0,%0,c14,c0,0") /* Counter Frequency Register */ 1023 ARMREG_READ_INLINE(cntk_ctl, "p15,0,%0,c14,c1,0") /* Timer PL1 Control Register */ 1024 ARMREG_WRITE_INLINE(cntk_ctl, "p15,0,%0,c14,c1,0") /* Timer PL1 Control Register */ 1025 ARMREG_READ_INLINE(cntp_tval, "p15,0,%0,c14,c2,0") /* PL1 Physical TimerValue Register */ 1026 ARMREG_WRITE_INLINE(cntp_tval, "p15,0,%0,c14,c2,0") /* PL1 Physical TimerValue Register */ 1027 ARMREG_READ_INLINE(cntp_ctl, "p15,0,%0,c14,c2,1") /* PL1 Physical Timer Control Register */ 1028 ARMREG_WRITE_INLINE(cntp_ctl, "p15,0,%0,c14,c2,1") /* PL1 Physical Timer Control Register */ 1029 ARMREG_READ_INLINE(cntv_tval, "p15,0,%0,c14,c3,0") /* Virtual TimerValue Register */ 1030 ARMREG_WRITE_INLINE(cntv_tval, "p15,0,%0,c14,c3,0") /* Virtual TimerValue Register */ 1031 ARMREG_READ_INLINE(cntv_ctl, "p15,0,%0,c14,c3,1") /* Virtual Timer Control Register */ 1032 ARMREG_WRITE_INLINE(cntv_ctl, "p15,0,%0,c14,c3,1") /* Virtual Timer Control Register */ 1033 ARMREG_READ64_INLINE(cntp_ct, "p15,0,%Q0,%R0,c14") /* Physical Count Register */ 1034 ARMREG_WRITE64_INLINE(cntp_ct, "p15,0,%Q0,%R0,c14") /* Physical Count Register */ 1035 ARMREG_READ64_INLINE(cntv_ct, "p15,1,%Q0,%R0,c14") /* Virtual Count Register */ 1036 ARMREG_WRITE64_INLINE(cntv_ct, "p15,1,%Q0,%R0,c14") /* Virtual Count Register */ 1037 ARMREG_READ64_INLINE(cntp_cval, "p15,2,%Q0,%R0,c14") /* PL1 Physical Timer CompareValue Register */ 1038 ARMREG_WRITE64_INLINE(cntp_cval, "p15,2,%Q0,%R0,c14") /* PL1 Physical Timer CompareValue Register */ 1039 ARMREG_READ64_INLINE(cntv_cval, "p15,3,%Q0,%R0,c14") /* PL1 Virtual Timer CompareValue Register */ 1040 ARMREG_WRITE64_INLINE(cntv_cval, "p15,3,%Q0,%R0,c14") /* PL1 Virtual Timer CompareValue Register */ 1041 ARMREG_READ64_INLINE(cntvoff, "p15,4,%Q0,%R0,c14") /* Virtual Offset Register */ 1042 ARMREG_WRITE64_INLINE(cntvoff, "p15,4,%Q0,%R0,c14") /* Virtual Offset Register */ 1043 /* cp15 c15 registers */ 1044 ARMREG_READ_INLINE(cbar, "p15,4,%0,c15,c0,0") /* Configuration Base Address Register */ 1045 ARMREG_READ_INLINE(pmcrv6, "p15,0,%0,c15,c12,0") /* PMC Control Register (armv6) */ 1046 ARMREG_WRITE_INLINE(pmcrv6, "p15,0,%0,c15,c12,0") /* PMC Control Register (armv6) */ 1047 ARMREG_READ_INLINE(pmccntrv6, "p15,0,%0,c15,c12,1") /* PMC Cycle Counter (armv6) */ 1048 ARMREG_WRITE_INLINE(pmccntrv6, "p15,0,%0,c15,c12,1") /* PMC Cycle Counter (armv6) */ 1049 1050 ARMREG_READ_INLINE(tlbdata0, "p15,3,%0,c15,c0,0") /* TLB Data Register 0 (cortex) */ 1051 ARMREG_READ_INLINE(tlbdata1, "p15,3,%0,c15,c0,1") /* TLB Data Register 1 (cortex) */ 1052 ARMREG_READ_INLINE(tlbdata2, "p15,3,%0,c15,c0,2") /* TLB Data Register 2 (cortex) */ 1053 ARMREG_WRITE_INLINE(tlbdataop, "p15,3,%0,c15,c4,2") /* TLB Data Read Operation (cortex) */ 1054 1055 ARMREG_READ_INLINE(sheeva_xctrl, "p15,1,%0,c15,c1,0") /* Sheeva eXtra Control register */ 1056 ARMREG_WRITE_INLINE(sheeva_xctrl, "p15,1,%0,c15,c1,0") /* Sheeva eXtra Control register */ 1057 1058 #endif /* !__ASSEMBLER__ */ 1059 1060 #endif /* _ARM_ARMREG_H */ 1061
Indexes created Sun Sep 28 16:09:52 GMT 2025