armreg.h revision 1.119
1 /* $NetBSD: armreg.h,v 1.119 2018/03/20 10:14:29 ryo Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2001 Ben Harris 5 * Copyright (c) 1994-1996 Mark Brinicombe. 6 * Copyright (c) 1994 Brini. 7 * All rights reserved. 8 * 9 * This code is derived from software written for Brini by Mark Brinicombe 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by Brini. 22 * 4. The name of the company nor the name of the author may be used to 23 * endorse or promote products derived from this software without specific 24 * prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 27 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 28 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 29 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 30 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 31 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 32 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 */ 38 39 #ifndef _ARM_ARMREG_H 40 #define _ARM_ARMREG_H 41 42 #include <arm/cputypes.h> 43 44 /* 45 * ARM Process Status Register 46 * 47 * The picture in the ARM manuals looks like this: 48 * 3 3 2 2 2 2 49 * 1 0 9 8 7 6 8 7 6 5 4 0 50 * +-+-+-+-+-+-------------------------------------+-+-+-+---------+ 51 * |N|Z|C|V|Q| reserved |I|F|T|M M M M M| 52 * | | | | | | | | | |4 3 2 1 0| 53 * +-+-+-+-+-+-------------------------------------+-+-+-+---------+ 54 */ 55 56 #define PSR_FLAGS 0xf0000000 /* flags */ 57 #define PSR_N_bit (1 << 31) /* negative */ 58 #define PSR_Z_bit (1 << 30) /* zero */ 59 #define PSR_C_bit (1 << 29) /* carry */ 60 #define PSR_V_bit (1 << 28) /* overflow */ 61 62 #define PSR_Q_bit (1 << 27) /* saturation */ 63 #define PSR_IT1_bit (1 << 26) 64 #define PSR_IT0_bit (1 << 25) 65 #define PSR_J_bit (1 << 24) /* Jazelle mode */ 66 #define PSR_GE_bits (15 << 16) /* SIMD GE bits */ 67 #define PSR_IT7_bit (1 << 15) 68 #define PSR_IT6_bit (1 << 14) 69 #define PSR_IT5_bit (1 << 13) 70 #define PSR_IT4_bit (1 << 12) 71 #define PSR_IT3_bit (1 << 11) 72 #define PSR_IT2_bit (1 << 10) 73 #define PSR_E_BIT (1 << 9) /* Endian state */ 74 #define PSR_A_BIT (1 << 8) /* Async abort disable */ 75 76 #define I32_bit (1 << 7) /* IRQ disable */ 77 #define F32_bit (1 << 6) /* FIQ disable */ 78 #define IF32_bits (3 << 6) /* IRQ/FIQ disable */ 79 80 #define PSR_T_bit (1 << 5) /* Thumb state */ 81 82 #define PSR_MODE 0x0000001f /* mode mask */ 83 #define PSR_USR32_MODE 0x00000010 84 #define PSR_FIQ32_MODE 0x00000011 85 #define PSR_IRQ32_MODE 0x00000012 86 #define PSR_SVC32_MODE 0x00000013 87 #define PSR_MON32_MODE 0x00000016 88 #define PSR_ABT32_MODE 0x00000017 89 #define PSR_HYP32_MODE 0x0000001a 90 #define PSR_UND32_MODE 0x0000001b 91 #define PSR_SYS32_MODE 0x0000001f 92 #define PSR_32_MODE 0x00000010 93 94 #define R15_FLAGS 0xf0000000 95 #define R15_FLAG_N 0x80000000 96 #define R15_FLAG_Z 0x40000000 97 #define R15_FLAG_C 0x20000000 98 #define R15_FLAG_V 0x10000000 99 100 /* 101 * Co-processor 15: The system control co-processor. 102 */ 103 104 #define ARM_CP15_CPU_ID 0 105 106 /* CPUID registers */ 107 #define ARM_ISA3_SYNCHPRIM_MASK 0x0000f000 108 #define ARM_ISA4_SYNCHPRIM_MASK 0x00f00000 109 #define ARM_ISA3_SYNCHPRIM_LDREX 0x10 // LDREX 110 #define ARM_ISA3_SYNCHPRIM_LDREXPLUS 0x13 // +CLREX/LDREXB/LDREXH 111 #define ARM_ISA3_SYNCHPRIM_LDREXD 0x20 // +LDREXD 112 #define ARM_PFR0_THUMBEE_MASK 0x0000f000 113 #define ARM_PFR1_GTIMER_MASK 0x000f0000 114 #define ARM_PFR1_VIRT_MASK 0x0000f000 115 #define ARM_PFR1_SEC_MASK 0x000000f0 116 117 /* Media and VFP Feature registers */ 118 #define ARM_MVFR0_ROUNDING_MASK 0xf0000000 119 #define ARM_MVFR0_SHORTVEC_MASK 0x0f000000 120 #define ARM_MVFR0_SQRT_MASK 0x00f00000 121 #define ARM_MVFR0_DIVIDE_MASK 0x000f0000 122 #define ARM_MVFR0_EXCEPT_MASK 0x0000f000 123 #define ARM_MVFR0_DFLOAT_MASK 0x00000f00 124 #define ARM_MVFR0_SFLOAT_MASK 0x000000f0 125 #define ARM_MVFR0_ASIMD_MASK 0x0000000f 126 #define ARM_MVFR1_ASIMD_FMACS_MASK 0xf0000000 127 #define ARM_MVFR1_VFP_HPFP_MASK 0x0f000000 128 #define ARM_MVFR1_ASIMD_HPFP_MASK 0x00f00000 129 #define ARM_MVFR1_ASIMD_SPFP_MASK 0x000f0000 130 #define ARM_MVFR1_ASIMD_INT_MASK 0x0000f000 131 #define ARM_MVFR1_ASIMD_LDST_MASK 0x00000f00 132 #define ARM_MVFR1_D_NAN_MASK 0x000000f0 133 #define ARM_MVFR1_FTZ_MASK 0x0000000f 134 135 /* ARM3-specific coprocessor 15 registers */ 136 #define ARM3_CP15_FLUSH 1 137 #define ARM3_CP15_CONTROL 2 138 #define ARM3_CP15_CACHEABLE 3 139 #define ARM3_CP15_UPDATEABLE 4 140 #define ARM3_CP15_DISRUPTIVE 5 141 142 /* ARM3 Control register bits */ 143 #define ARM3_CTL_CACHE_ON 0x00000001 144 #define ARM3_CTL_SHARED 0x00000002 145 #define ARM3_CTL_MONITOR 0x00000004 146 147 /* 148 * Post-ARM3 CP15 registers: 149 * 150 * 1 Control register 151 * 152 * 2 Translation Table Base 153 * 154 * 3 Domain Access Control 155 * 156 * 4 Reserved 157 * 158 * 5 Fault Status 159 * 160 * 6 Fault Address 161 * 162 * 7 Cache/write-buffer Control 163 * 164 * 8 TLB Control 165 * 166 * 9 Cache Lockdown 167 * 168 * 10 TLB Lockdown 169 * 170 * 11 Reserved 171 * 172 * 12 Reserved 173 * 174 * 13 Process ID (for FCSE) 175 * 176 * 14 Reserved 177 * 178 * 15 Implementation Dependent 179 */ 180 181 /* Some of the definitions below need cleaning up for V3/V4 architectures */ 182 183 /* CPU control register (CP15 register 1) */ 184 #define CPU_CONTROL_MMU_ENABLE 0x00000001 /* M: MMU/Protection unit enable */ 185 #define CPU_CONTROL_AFLT_ENABLE 0x00000002 /* A: Alignment fault enable */ 186 #define CPU_CONTROL_DC_ENABLE 0x00000004 /* C: IDC/DC enable */ 187 #define CPU_CONTROL_WBUF_ENABLE 0x00000008 /* W: Write buffer enable */ 188 #define CPU_CONTROL_32BP_ENABLE 0x00000010 /* P: 32-bit exception handlers */ 189 #define CPU_CONTROL_32BD_ENABLE 0x00000020 /* D: 32-bit addressing */ 190 #define CPU_CONTROL_LABT_ENABLE 0x00000040 /* L: Late abort enable */ 191 #define CPU_CONTROL_BEND_ENABLE 0x00000080 /* B: Big-endian mode */ 192 #define CPU_CONTROL_SYST_ENABLE 0x00000100 /* S: System protection bit */ 193 #define CPU_CONTROL_ROM_ENABLE 0x00000200 /* R: ROM protection bit */ 194 #define CPU_CONTROL_CPCLK 0x00000400 /* F: Implementation defined */ 195 #define CPU_CONTROL_SWP_ENABLE 0x00000400 /* SW: SWP{B} perform normally. */ 196 #define CPU_CONTROL_BPRD_ENABLE 0x00000800 /* Z: Branch prediction enable */ 197 #define CPU_CONTROL_IC_ENABLE 0x00001000 /* I: IC enable */ 198 #define CPU_CONTROL_VECRELOC 0x00002000 /* V: Vector relocation */ 199 #define CPU_CONTROL_ROUNDROBIN 0x00004000 /* RR: Predictable replacement */ 200 #define CPU_CONTROL_V4COMPAT 0x00008000 /* L4: ARMv4 compat LDR R15 etc */ 201 #define CPU_CONTROL_HA_ENABLE 0x00020000 /* HA: Hardware Access flag enable */ 202 #define CPU_CONTROL_WXN_ENABLE 0x00080000 /* WXN: Write Execute Never */ 203 #define CPU_CONTROL_UWXN_ENABLE 0x00100000 /* UWXN: User Write eXecute Never */ 204 #define CPU_CONTROL_FI_ENABLE 0x00200000 /* FI: Low interrupt latency */ 205 #define CPU_CONTROL_UNAL_ENABLE 0x00400000 /* U: unaligned data access */ 206 #define CPU_CONTROL_XP_ENABLE 0x00800000 /* XP: extended page table */ 207 #define CPU_CONTROL_V_ENABLE 0x01000000 /* VE: Interrupt vectors enable */ 208 #define CPU_CONTROL_EX_BEND 0x02000000 /* EE: exception endianness */ 209 #define CPU_CONTROL_NMFI 0x08000000 /* NMFI: Non maskable FIQ */ 210 #define CPU_CONTROL_TR_ENABLE 0x10000000 /* TRE: */ 211 #define CPU_CONTROL_AF_ENABLE 0x20000000 /* AFE: Access flag enable */ 212 #define CPU_CONTROL_TE_ENABLE 0x40000000 /* TE: Thumb Exception enable */ 213 214 #define CPU_CONTROL_IDC_ENABLE CPU_CONTROL_DC_ENABLE 215 216 /* ARMv6/ARMv7 Co-Processor Access Control Register (CP15, 0, c1, c0, 2) */ 217 #define CPACR_V7_ASEDIS 0x80000000 /* Disable Advanced SIMD Ext. */ 218 #define CPACR_V7_D32DIS 0x40000000 /* Disable VFP regs 15-31 */ 219 #define CPACR_CPn(n) (3 << (2*n)) 220 #define CPACR_NOACCESS 0 /* reset value */ 221 #define CPACR_PRIVED 1 /* Privileged mode access */ 222 #define CPACR_RESERVED 2 223 #define CPACR_ALL 3 /* Privileged and User mode access */ 224 225 /* ARMv6/ARMv7 Non-Secure Access Control Register (CP15, 0, c1, c1, 2) */ 226 #define NSACR_SMP 0x00040000 /* ACTRL.SMP is writeable (!A8) */ 227 #define NSACR_L2ERR 0x00020000 /* L2ECTRL is writeable (!A8) */ 228 #define NSACR_ASEDIS 0x00008000 /* Deny Advanced SIMD Ext. */ 229 #define NSACR_D32DIS 0x00004000 /* Deny VFP regs 15-31 */ 230 #define NSACR_CPn(n) (1 << (n)) /* NonSecure access allowed */ 231 232 /* ARM11x6 Auxiliary Control Register (CP15 register 1, opcode2 1) */ 233 #define ARM11X6_AUXCTL_RS 0x00000001 /* return stack */ 234 #define ARM11X6_AUXCTL_DB 0x00000002 /* dynamic branch prediction */ 235 #define ARM11X6_AUXCTL_SB 0x00000004 /* static branch prediction */ 236 #define ARM11X6_AUXCTL_TR 0x00000008 /* MicroTLB replacement strat. */ 237 #define ARM11X6_AUXCTL_EX 0x00000010 /* exclusive L1/L2 cache */ 238 #define ARM11X6_AUXCTL_RA 0x00000020 /* clean entire cache disable */ 239 #define ARM11X6_AUXCTL_RV 0x00000040 /* block transfer cache disable */ 240 #define ARM11X6_AUXCTL_CZ 0x00000080 /* restrict cache size */ 241 242 /* ARM1136 Auxiliary Control Register (CP15 register 1, opcode2 1) */ 243 #define ARM1136_AUXCTL_PFI 0x80000000 /* PFI: partial FI mode. */ 244 /* This is an undocumented flag 245 * used to work around a cache bug 246 * in r0 steppings. See errata 247 * 364296. 248 */ 249 /* ARM1176 Auxiliary Control Register (CP15 register 1, opcode2 1) */ 250 #define ARM1176_AUXCTL_PHD 0x10000000 /* inst. prefetch halting disable */ 251 #define ARM1176_AUXCTL_BFD 0x20000000 /* branch folding disable */ 252 #define ARM1176_AUXCTL_FSD 0x40000000 /* force speculative ops disable */ 253 #define ARM1176_AUXCTL_FIO 0x80000000 /* low intr latency override */ 254 255 /* XScale Auxiliary Control Register (CP15 register 1, opcode2 1) */ 256 #define XSCALE_AUXCTL_K 0x00000001 /* dis. write buffer coalescing */ 257 #define XSCALE_AUXCTL_P 0x00000002 /* ECC protect page table access */ 258 #define XSCALE_AUXCTL_MD_WB_RA 0x00000000 /* mini-D$ wb, read-allocate */ 259 #define XSCALE_AUXCTL_MD_WB_RWA 0x00000010 /* mini-D$ wb, read/write-allocate */ 260 #define XSCALE_AUXCTL_MD_WT 0x00000020 /* mini-D$ wt, read-allocate */ 261 #define XSCALE_AUXCTL_MD_MASK 0x00000030 262 263 /* ARM11 MPCore Auxiliary Control Register (CP15 register 1, opcode2 1) */ 264 #define MPCORE_AUXCTL_RS 0x00000001 /* return stack */ 265 #define MPCORE_AUXCTL_DB 0x00000002 /* dynamic branch prediction */ 266 #define MPCORE_AUXCTL_SB 0x00000004 /* static branch prediction */ 267 #define MPCORE_AUXCTL_F 0x00000008 /* instruction folding enable */ 268 #define MPCORE_AUXCTL_EX 0x00000010 /* exclusive L1/L2 cache */ 269 #define MPCORE_AUXCTL_SA 0x00000020 /* SMP/AMP */ 270 271 /* Marvell PJ4B Auxillary Control Register (CP15.0.R1.c0.1) */ 272 #define PJ4B_AUXCTL_FW __BIT(0) /* Cache and TLB updates broadcast */ 273 #define PJ4B_AUXCTL_SMPNAMP __BIT(6) /* 0 = AMP, 1 = SMP */ 274 #define PJ4B_AUXCTL_L1PARITY __BIT(9) /* L1 parity checking */ 275 276 /* Marvell PJ4B Auxialiary Function Modes Control 0 (CP15.1.R15.c2.0) */ 277 #define PJ4B_AUXFMC0_L2EN __BIT(0) /* Tightly-Coupled L2 cache enable */ 278 #define PJ4B_AUXFMC0_SMPNAMP __BIT(1) /* 0 = AMP, 1 = SMP */ 279 #define PJ4B_AUXFMC0_L1PARITY __BIT(2) /* alias of PJ4B_AUXCTL_L1PARITY */ 280 #define PJ4B_AUXFMC0_DCSLFD __BIT(2) /* Disable DC Speculative linefill */ 281 #define PJ4B_AUXFMC0_FW __BIT(8) /* alias of PJ4B_AUXCTL_FW*/ 282 283 /* Cortex-A9 Auxiliary Control Register (CP15 register 1, opcode 1) */ 284 #define CORTEXA9_AUXCTL_FW 0x00000001 /* Cache and TLB updates broadcast */ 285 #define CORTEXA9_AUXCTL_L2PE 0x00000002 /* Prefetch hint enable */ 286 #define CORTEXA9_AUXCTL_L1PE 0x00000004 /* Data prefetch hint enable */ 287 #define CORTEXA9_AUXCTL_WR_ZERO 0x00000008 /* Ena. write full line of 0s mode */ 288 #define CORTEXA9_AUXCTL_SMP 0x00000040 /* Coherency is active */ 289 #define CORTEXA9_AUXCTL_EXCL 0x00000080 /* Exclusive cache bit */ 290 #define CORTEXA9_AUXCTL_ONEWAY 0x00000100 /* Allocate in on cache way only */ 291 #define CORTEXA9_AUXCTL_PARITY 0x00000200 /* Support parity checking */ 292 293 /* Cortex-A15 Auxiliary Control Register (CP15 register 1, opcode 1) */ 294 #define CORTEXA15_ACTLR_BTB __BIT(0) /* Cache and TLB updates broadcast */ 295 #define CORTEXA15_ACTLR_SMP __BIT(6) /* SMP */ 296 #define CORTEXA15_ACTLR_IOBEU __BIT(15) /* In order issue in Branch Exec Unit */ 297 298 /* Marvell Feroceon Extra Features Register (CP15 register 1, opcode2 0) */ 299 #define FC_DCACHE_REPL_LOCK 0x80000000 /* Replace DCache Lock */ 300 #define FC_DCACHE_STREAM_EN 0x20000000 /* DCache Streaming Switch */ 301 #define FC_WR_ALLOC_EN 0x10000000 /* Enable Write Allocate */ 302 #define FC_L2_PREF_DIS 0x01000000 /* L2 Cache Prefetch Disable */ 303 #define FC_L2_INV_EVICT_LINE 0x00800000 /* L2 Invalidates Uncorrectable Error Line Eviction */ 304 #define FC_L2CACHE_EN 0x00400000 /* L2 enable */ 305 #define FC_ICACHE_REPL_LOCK 0x00080000 /* Replace ICache Lock */ 306 #define FC_GLOB_HIST_REG_EN 0x00040000 /* Branch Global History Register Enable */ 307 #define FC_BRANCH_TARG_BUF_DIS 0x00020000 /* Branch Target Buffer Disable */ 308 #define FC_L1_PAR_ERR_EN 0x00010000 /* L1 Parity Error Enable */ 309 310 /* Cache type register definitions 0 */ 311 #define CPU_CT_FORMAT(x) (((x) >> 29) & 0x7) /* reg format */ 312 #define CPU_CT_ISIZE(x) ((x) & 0xfff) /* I$ info */ 313 #define CPU_CT_DSIZE(x) (((x) >> 12) & 0xfff) /* D$ info */ 314 #define CPU_CT_S (1U << 24) /* split cache */ 315 #define CPU_CT_CTYPE(x) (((x) >> 25) & 0xf) /* cache type */ 316 317 #define CPU_CT_CTYPE_WT 0 /* write-through */ 318 #define CPU_CT_CTYPE_WB1 1 /* write-back, clean w/ read */ 319 #define CPU_CT_CTYPE_WB2 2 /* w/b, clean w/ cp15,7 */ 320 #define CPU_CT_CTYPE_WB6 6 /* w/b, cp15,7, lockdown fmt A */ 321 #define CPU_CT_CTYPE_WB7 7 /* w/b, cp15,7, lockdown fmt B */ 322 #define CPU_CT_CTYPE_WB14 14 /* w/b, cp15,7, lockdown fmt C */ 323 324 #define CPU_CT_xSIZE_LEN(x) ((x) & 0x3) /* line size */ 325 #define CPU_CT_xSIZE_M (1U << 2) /* multiplier */ 326 #define CPU_CT_xSIZE_ASSOC(x) (((x) >> 3) & 0x7) /* associativity */ 327 #define CPU_CT_xSIZE_SIZE(x) (((x) >> 6) & 0x7) /* size */ 328 #define CPU_CT_xSIZE_P (1U << 11) /* need to page-color */ 329 330 /* format 4 definitions */ 331 #define CPU_CT4_ILINE(x) ((x) & 0xf) /* I$ line size */ 332 #define CPU_CT4_DLINE(x) (((x) >> 16) & 0xf) /* D$ line size */ 333 #define CPU_CT4_L1IPOLICY(x) (((x) >> 14) & 0x3) /* I$ policy */ 334 #define CPU_CT4_L1_AIVIVT 1 /* ASID tagged VIVT */ 335 #define CPU_CT4_L1_VIPT 2 /* VIPT */ 336 #define CPU_CT4_L1_PIPT 3 /* PIPT */ 337 #define CPU_CT4_ERG(x) (((x) >> 20) & 0xf) /* Cache WriteBack Granule */ 338 #define CPU_CT4_CWG(x) (((x) >> 24) & 0xf) /* Exclusive Resv. Granule */ 339 340 /* Cache size identifaction register definitions 1, Rd, c0, c0, 0 */ 341 #define CPU_CSID_CTYPE_WT 0x80000000 /* write-through avail */ 342 #define CPU_CSID_CTYPE_WB 0x40000000 /* write-back avail */ 343 #define CPU_CSID_CTYPE_RA 0x20000000 /* read-allocation avail */ 344 #define CPU_CSID_CTYPE_WA 0x10000000 /* write-allocation avail */ 345 #define CPU_CSID_NUMSETS(x) (((x) >> 13) & 0x7fff) 346 #define CPU_CSID_ASSOC(x) (((x) >> 3) & 0x1ff) 347 #define CPU_CSID_LEN(x) ((x) & 0x07) 348 349 /* Cache size selection register definitions 2, Rd, c0, c0, 0 */ 350 #define CPU_CSSR_L2 0x00000002 351 #define CPU_CSSR_L1 0x00000000 352 #define CPU_CSSR_InD 0x00000001 353 354 /* Fault status register definitions */ 355 356 #define FAULT_TYPE_MASK 0x0f 357 #define FAULT_USER 0x10 358 359 #define FAULT_WRTBUF_0 0x00 /* Vector Exception */ 360 #define FAULT_WRTBUF_1 0x02 /* Terminal Exception */ 361 #define FAULT_BUSERR_0 0x04 /* External Abort on Linefetch -- Section */ 362 #define FAULT_BUSERR_1 0x06 /* External Abort on Linefetch -- Page */ 363 #define FAULT_BUSERR_2 0x08 /* External Abort on Non-linefetch -- Section */ 364 #define FAULT_BUSERR_3 0x0a /* External Abort on Non-linefetch -- Page */ 365 #define FAULT_BUSTRNL1 0x0c /* External abort on Translation -- Level 1 */ 366 #define FAULT_BUSTRNL2 0x0e /* External abort on Translation -- Level 2 */ 367 #define FAULT_ALIGN_0 0x01 /* Alignment */ 368 #define FAULT_ALIGN_1 0x03 /* Alignment */ 369 #define FAULT_TRANS_S 0x05 /* Translation -- Section */ 370 #define FAULT_TRANS_P 0x07 /* Translation -- Page */ 371 #define FAULT_DOMAIN_S 0x09 /* Domain -- Section */ 372 #define FAULT_DOMAIN_P 0x0b /* Domain -- Page */ 373 #define FAULT_PERM_S 0x0d /* Permission -- Section */ 374 #define FAULT_PERM_P 0x0f /* Permission -- Page */ 375 376 #define FAULT_LPAE 0x0200 /* (SW) used long descriptors */ 377 #define FAULT_IMPRECISE 0x0400 /* Imprecise exception (XSCALE) */ 378 #define FAULT_WRITE 0x0800 /* fault was due to write (ARMv6+) */ 379 #define FAULT_EXT 0x1000 /* fault was due to external abort (ARMv6+) */ 380 #define FAULT_CM 0x2000 /* fault was due to cache maintenance (ARMv7+) */ 381 382 /* 383 * Address of the vector page, low and high versions. 384 */ 385 #define ARM_VECTORS_LOW 0x00000000U 386 #define ARM_VECTORS_HIGH 0xffff0000U 387 388 /* 389 * ARM Instructions 390 * 391 * 3 3 2 2 2 392 * 1 0 9 8 7 0 393 * +-------+-------------------------------------------------------+ 394 * | cond | instruction dependent | 395 * |c c c c| | 396 * +-------+-------------------------------------------------------+ 397 */ 398 399 #define INSN_SIZE 4 /* Always 4 bytes */ 400 #define INSN_COND_MASK 0xf0000000 /* Condition mask */ 401 #define INSN_COND_EQ 0 /* Z == 1 */ 402 #define INSN_COND_NE 1 /* Z == 0 */ 403 #define INSN_COND_CS 2 /* C == 1 */ 404 #define INSN_COND_CC 3 /* C == 0 */ 405 #define INSN_COND_MI 4 /* N == 1 */ 406 #define INSN_COND_PL 5 /* N == 0 */ 407 #define INSN_COND_VS 6 /* V == 1 */ 408 #define INSN_COND_VC 7 /* V == 0 */ 409 #define INSN_COND_HI 8 /* C == 1 && Z == 0 */ 410 #define INSN_COND_LS 9 /* C == 0 || Z == 1 */ 411 #define INSN_COND_GE 10 /* N == V */ 412 #define INSN_COND_LT 11 /* N != V */ 413 #define INSN_COND_GT 12 /* Z == 0 && N == V */ 414 #define INSN_COND_LE 13 /* Z == 1 || N != V */ 415 #define INSN_COND_AL 14 /* Always condition */ 416 417 #define THUMB_INSN_SIZE 2 /* Some are 4 bytes. */ 418 419 /* 420 * Defines and such for arm11 Performance Monitor Counters (p15, c15, c12, 0) 421 */ 422 #define ARM11_PMCCTL_E __BIT(0) /* enable all three counters */ 423 #define ARM11_PMCCTL_P __BIT(1) /* reset both Count Registers to zero */ 424 #define ARM11_PMCCTL_C __BIT(2) /* reset the Cycle Counter Register to zero */ 425 #define ARM11_PMCCTL_D __BIT(3) /* cycle count divide by 64 */ 426 #define ARM11_PMCCTL_EC0 __BIT(4) /* Enable Counter Register 0 interrupt */ 427 #define ARM11_PMCCTL_EC1 __BIT(5) /* Enable Counter Register 1 interrupt */ 428 #define ARM11_PMCCTL_ECC __BIT(6) /* Enable Cycle Counter interrupt */ 429 #define ARM11_PMCCTL_SBZa __BIT(7) /* UNP/SBZ */ 430 #define ARM11_PMCCTL_CR0 __BIT(8) /* Count Register 0 overflow flag */ 431 #define ARM11_PMCCTL_CR1 __BIT(9) /* Count Register 1 overflow flag */ 432 #define ARM11_PMCCTL_CCR __BIT(10) /* Cycle Count Register overflow flag */ 433 #define ARM11_PMCCTL_X __BIT(11) /* Enable Export of the events to the event bus */ 434 #define ARM11_PMCCTL_EVT1 __BITS(19,12) /* source of events for Count Register 1 */ 435 #define ARM11_PMCCTL_EVT0 __BITS(27,20) /* source of events for Count Register 0 */ 436 #define ARM11_PMCCTL_SBZb __BITS(31,28) /* UNP/SBZ */ 437 #define ARM11_PMCCTL_SBZ \ 438 (ARM11_PMCCTL_SBZa | ARM11_PMCCTL_SBZb) 439 440 #define ARM11_PMCEVT_ICACHE_MISS 0 /* Instruction Cache Miss */ 441 #define ARM11_PMCEVT_ISTREAM_STALL 1 /* Instruction Stream Stall */ 442 #define ARM11_PMCEVT_IUTLB_MISS 2 /* Instruction uTLB Miss */ 443 #define ARM11_PMCEVT_DUTLB_MISS 3 /* Data uTLB Miss */ 444 #define ARM11_PMCEVT_BRANCH 4 /* Branch Inst. Executed */ 445 #define ARM11_PMCEVT_BRANCH_MISS 6 /* Branch mispredicted */ 446 #define ARM11_PMCEVT_INST_EXEC 7 /* Instruction Executed */ 447 #define ARM11_PMCEVT_DCACHE_ACCESS0 9 /* Data Cache Access */ 448 #define ARM11_PMCEVT_DCACHE_ACCESS1 10 /* Data Cache Access */ 449 #define ARM11_PMCEVT_DCACHE_MISS 11 /* Data Cache Miss */ 450 #define ARM11_PMCEVT_DCACHE_WRITEBACK 12 /* Data Cache Writeback */ 451 #define ARM11_PMCEVT_PC_CHANGE 13 /* Software PC change */ 452 #define ARM11_PMCEVT_TLB_MISS 15 /* Main TLB Miss */ 453 #define ARM11_PMCEVT_DATA_ACCESS 16 /* non-cached data access */ 454 #define ARM11_PMCEVT_LSU_STALL 17 /* Load/Store Unit stall */ 455 #define ARM11_PMCEVT_WBUF_DRAIN 18 /* Write buffer drained */ 456 #define ARM11_PMCEVT_ETMEXTOUT0 32 /* ETMEXTOUT[0] asserted */ 457 #define ARM11_PMCEVT_ETMEXTOUT1 33 /* ETMEXTOUT[1] asserted */ 458 #define ARM11_PMCEVT_ETMEXTOUT 34 /* ETMEXTOUT[0 & 1] */ 459 #define ARM11_PMCEVT_CALL_EXEC 35 /* Procedure call executed */ 460 #define ARM11_PMCEVT_RETURN_EXEC 36 /* Return executed */ 461 #define ARM11_PMCEVT_RETURN_HIT 37 /* return address predicted */ 462 #define ARM11_PMCEVT_RETURN_MISS 38 /* return addr. mispredicted */ 463 #define ARM11_PMCEVT_CYCLE 255 /* Increment each cycle */ 464 465 /* Defines for ARM CORTEX performance counters */ 466 #define CORTEX_CNTENS_C __BIT(31) /* Enables the cycle counter */ 467 #define CORTEX_CNTENC_C __BIT(31) /* Disables the cycle counter */ 468 #define CORTEX_CNTOFL_C __BIT(31) /* Cycle counter overflow flag */ 469 470 /* Defines for ARM Cortex A7/A15 L2CTRL */ 471 #define L2CTRL_NUMCPU __BITS(25,24) // numcpus - 1 472 #define L2CTRL_ICPRES __BIT(23) // Interrupt Controller is present 473 474 /* Translation Table Base Register */ 475 #define TTBR_C __BIT(0) /* without MPE */ 476 #define TTBR_S __BIT(1) 477 #define TTBR_IMP __BIT(2) 478 #define TTBR_RGN_MASK __BITS(4,3) 479 #define TTBR_RGN_NC __SHIFTIN(0, TTBR_RGN_MASK) 480 #define TTBR_RGN_WBWA __SHIFTIN(1, TTBR_RGN_MASK) 481 #define TTBR_RGN_WT __SHIFTIN(2, TTBR_RGN_MASK) 482 #define TTBR_RGN_WBNWA __SHIFTIN(3, TTBR_RGN_MASK) 483 #define TTBR_NOS __BIT(5) 484 #define TTBR_IRGN_MASK (__BIT(6) | __BIT(0)) 485 #define TTBR_IRGN_NC 0 486 #define TTBR_IRGN_WBWA __BIT(6) 487 #define TTBR_IRGN_WT __BIT(0) 488 #define TTBR_IRGN_WBNWA (__BIT(0) | __BIT(6)) 489 490 /* Translate Table Base Control Register */ 491 #define TTBCR_S_EAE __BIT(31) // Extended Address Extension 492 #define TTBCR_S_PD1 __BIT(5) // Don't use TTBR1 493 #define TTBCR_S_PD0 __BIT(4) // Don't use TTBR0 494 #define TTBCR_S_N __BITS(2,0) // Width of base address in TTB0 495 496 #define TTBCR_L_EAE __BIT(31) // Extended Address Extension 497 #define TTBCR_L_SH1 __BITS(29,28) // TTBR1 Shareability 498 #define TTBCR_L_ORGN1 __BITS(27,26) // TTBR1 Outer cacheability 499 #define TTBCR_L_IRGN1 __BITS(25,24) // TTBR1 inner cacheability 500 #define TTBCR_L_EPD1 __BIT(23) // Don't use TTBR1 501 #define TTBCR_L_A1 __BIT(22) // ASID is in TTBR1 502 #define TTBCR_L_T1SZ __BITS(18,16) // TTBR1 size offset 503 #define TTBCR_L_SH0 __BITS(13,12) // TTBR0 Shareability 504 #define TTBCR_L_ORGN0 __BITS(11,10) // TTBR0 Outer cacheability 505 #define TTBCR_L_IRGN0 __BITS(9,8) // TTBR0 inner cacheability 506 #define TTBCR_L_EPD0 __BIT(7) // Don't use TTBR0 507 #define TTBCR_L_T0SZ __BITS(2,0) // TTBR0 size offset 508 509 #define NRRR_ORn(n) __BITS(17+2*(n),16+2*(n)) // Outer Cacheable mappings 510 #define NRRR_IRn(n) __BITS(1+2*(n),0+2*(n)) // Inner Cacheable mappings 511 #define NRRR_NC 0 // non-cacheable 512 #define NRRR_WB_WA 1 // write-back write-allocate 513 #define NRRR_WT 2 // write-through 514 #define NRRR_WB 3 // write-back 515 #define PRRR_NOSn(n) __BITS(24+2*(n))// Memory region is Inner Shareable 516 #define PRRR_NS1 __BIT(19) // Normal Shareable S=1 is Shareable 517 #define PRRR_NS0 __BIT(18) // Normal Shareable S=0 is Shareable 518 #define PRRR_DS1 __BIT(17) // Device Shareable S=1 is Shareable 519 #define PRRR_DS0 __BIT(16) // Device Shareable S=0 is Shareable 520 #define PRRR_TRn(n) __BITS(1+2*(n),0+2*(n)) 521 #define PRRR_TR_STRONG 0 // Strongly Ordered 522 #define PRRR_TR_DEVICE 1 // Device 523 #define PRRR_TR_NORMAL 2 // Normal Memory 524 525 /* ARMv7 MPIDR, Multiprocessor Affinity Register generic format */ 526 #define MPIDR_MP __BIT(31) /* 1 = Have MP Extention */ 527 #define MPIDR_U __BIT(30) /* 1 = Uni-Processor System */ 528 #define MPIDR_MT __BIT(24) /* 1 = SMT(AFF0 is logical) */ 529 #define MPIDR_AFF2 __BITS(23,16) /* Affinity Level 2 */ 530 #define MPIDR_AFF1 __BITS(15,8) /* Affinity Level 1 */ 531 #define MPIDR_AFF0 __BITS(7,0) /* Affinity Level 0 */ 532 533 /* MPIDR implementation of ARM Cortex A9: SMT and AFF2 is not used */ 534 #define CORTEXA9_MPIDR_MP MPIDR_MP 535 #define CORTEXA9_MPIDR_U MPIDR_U 536 #define CORTEXA9_MPIDR_CLID __BITS(11,8) /* AFF1 = cluster id */ 537 #define CORTEXA9_MPIDR_CPUID __BITS(0,1) /* AFF0 = physical core id */ 538 539 /* MPIDR implementation of Marvell PJ4B-MP: AFF2 is not used */ 540 #define PJ4B_MPIDR_MP MPIDR_MP 541 #define PJ4B_MPIDR_U MPIDR_U 542 #define PJ4B_MPIDR_MT MPIDR_MT /* 1 = SMT(AFF0 is logical) */ 543 #define PJ4B_MPIDR_CLID __BITS(11,8) /* AFF1 = cluster id */ 544 #define PJ4B_MPIDR_CPUID __BITS(0,3) /* AFF0 = core id */ 545 546 /* Defines for ARM Generic Timer */ 547 #define ARM_CNTCTL_ISTATUS __BIT(2) // Interrupt is pending 548 #define ARM_CNTCTL_IMASK __BIT(1) // Mask Interrupt 549 #define ARM_CNTCTL_ENABLE __BIT(0) // Timer Enabled 550 551 #define ARM_CNTKCTL_PL0PTEN __BIT(9) /* PL0 Physical Timer Enable */ 552 #define ARM_CNTKCTL_PL0VTEN __BIT(8) /* PL0 Virtual Timer Enable */ 553 #define ARM_CNTKCTL_EVNTI __BITS(7,4) /* CNTVCT Event Bit Select */ 554 #define ARM_CNTKCTL_EVNTDIR __BIT(3) /* CNTVCT Event Dir (1->0) */ 555 #define ARM_CNTKCTL_EVNTEN __BIT(2) /* CNTVCT Event Enable */ 556 #define ARM_CNTKCTL_PL0VCTEN __BIT(1) /* PL0 Virtual Counter Enable */ 557 #define ARM_CNTKCTL_PL0PCTEN __BIT(0) /* PL0 Physical Counter Enable */ 558 559 /* CNCHCTL, Timer PL2 Control register, Virtualization Extensions */ 560 #define ARM_CNTHCTL_EVNTI __BITS(7,4) 561 #define ARM_CNTHCTL_EVNTDIR __BIT(3) 562 #define ARM_CNTHCTL_EVNTEN __BIT(2) 563 #define ARM_CNTHCTL_PL1PCEN __BIT(1) 564 #define ARM_CNTHCTL_PL1PCTEN __BIT(0) 565 566 #define ARM_A5_TLBDATA_DOM __BITS(62,59) 567 #define ARM_A5_TLBDATA_AP __BITS(58,56) 568 #define ARM_A5_TLBDATA_NS_WALK __BIT(55) 569 #define ARM_A5_TLBDATA_NS_PAGE __BIT(54) 570 #define ARM_A5_TLBDATA_XN __BIT(53) 571 #define ARM_A5_TLBDATA_TEX __BITS(52,50) 572 #define ARM_A5_TLBDATA_B __BIT(49) 573 #define ARM_A5_TLBDATA_C __BIT(48) 574 #define ARM_A5_TLBDATA_S __BIT(47) 575 #define ARM_A5_TLBDATA_ASID __BITS(46,39) 576 #define ARM_A5_TLBDATA_SIZE __BITS(38,37) 577 #define ARM_A5_TLBDATA_SIZE_4KB 0 578 #define ARM_A5_TLBDATA_SIZE_16KB 1 579 #define ARM_A5_TLBDATA_SIZE_1MB 2 580 #define ARM_A5_TLBDATA_SIZE_16MB 3 581 #define ARM_A5_TLBDATA_VA __BITS(36,22) 582 #define ARM_A5_TLBDATA_PA __BITS(21,2) 583 #define ARM_A5_TLBDATA_nG __BIT(1) 584 #define ARM_A5_TLBDATA_VALID __BIT(0) 585 586 #define ARM_A7_TLBDATA2_S2_LEVEL __BITS(85-64,84-64) 587 #define ARM_A7_TLBDATA2_S1_SIZE __BITS(83-64,82-64) 588 #define ARM_A7_TLBDATA2_S1_SIZE_4KB 0 589 #define ARM_A7_TLBDATA2_S1_SIZE_64KB 1 590 #define ARM_A7_TLBDATA2_S1_SIZE_1MB 2 591 #define ARM_A7_TLBDATA2_S1_SIZE_16MB 3 592 #define ARM_A7_TLBDATA2_DOM __BITS(81-64,78-64) 593 #define ARM_A7_TLBDATA2_IS __BITS(77-64,76-64) 594 #define ARM_A7_TLBDATA2_IS_NC 0 595 #define ARM_A7_TLBDATA2_IS_WB_WA 1 596 #define ARM_A7_TLBDATA2_IS_WT 2 597 #define ARM_A7_TLBDATA2_IS_DSO 3 598 #define ARM_A7_TLBDATA2_S2OVR __BIT(75-64) 599 #define ARM_A7_TLBDATA2_SDO_MT __BITS(74-64,72-64) 600 #define ARM_A7_TLBDATA2_SDO_MT_D 2 601 #define ARM_A7_TLBDATA2_SDO_MT_SO 6 602 #define ARM_A7_TLBDATA2_OS __BITS(75-64,74-64) 603 #define ARM_A7_TLBDATA2_OS_NC 0 604 #define ARM_A7_TLBDATA2_OS_WB_WA 1 605 #define ARM_A7_TLBDATA2_OS_WT 2 606 #define ARM_A7_TLBDATA2_OS_WB 3 607 #define ARM_A7_TLBDATA2_SH __BITS(73-64,72-64) 608 #define ARM_A7_TLBDATA2_SH_NONE 0 609 #define ARM_A7_TLBDATA2_SH_UNUSED 1 610 #define ARM_A7_TLBDATA2_SH_OS 2 611 #define ARM_A7_TLBDATA2_SH_IS 3 612 #define ARM_A7_TLBDATA2_XN2 __BIT(71-64) 613 #define ARM_A7_TLBDATA2_XN1 __BIT(70-64) 614 #define ARM_A7_TLBDATA2_PXN __BIT(69-64) 615 616 #define ARM_A7_TLBDATA12_PA __BITS(68-32,41-32) 617 618 #define ARM_A7_TLBDATA1_NS __BIT(40-32) 619 #define ARM_A7_TLBDATA1_HAP __BITS(39-32,38-32) 620 #define ARM_A7_TLBDATA1_AP __BITS(37-32,35-32) 621 #define ARM_A7_TLBDATA1_nG __BIT(34-32) 622 623 #define ARM_A7_TLBDATA01_ASID __BITS(33,26) 624 625 #define ARM_A7_TLBDATA0_VMID __BITS(25,18) 626 #define ARM_A7_TLBDATA0_VA __BITS(17,5) 627 #define ARM_A7_TLBDATA0_NS_WALK __BIT(4) 628 #define ARM_A7_TLBDATA0_SIZE __BITS(3,1) 629 #define ARM_A7_TLBDATA0_SIZE_V7_4KB 0 630 #define ARM_A7_TLBDATA0_SIZE_LPAE_4KB 1 631 #define ARM_A7_TLBDATA0_SIZE_V7_64KB 2 632 #define ARM_A7_TLBDATA0_SIZE_LPAE_64KB 3 633 #define ARM_A7_TLBDATA0_SIZE_V7_1MB 4 634 #define ARM_A7_TLBDATA0_SIZE_LPAE_2MB 5 635 #define ARM_A7_TLBDATA0_SIZE_V7_16MB 6 636 #define ARM_A7_TLBDATA0_SIZE_LPAE_1GB 7 637 638 #define ARM_TLBDATA_VALID __BIT(0) 639 640 #define ARM_TLBDATAOP_WAY __BIT(31) 641 #define ARM_A5_TLBDATAOP_INDEX __BITS(5,0) 642 #define ARM_A7_TLBDATAOP_INDEX __BITS(6,0) 643 644 #if !defined(__ASSEMBLER__) && defined(_KERNEL) 645 static inline bool 646 arm_cond_ok_p(uint32_t insn, uint32_t psr) 647 { 648 const uint32_t __cond = __SHIFTOUT(insn, INSN_COND_MASK); 649 650 bool __ok; 651 const bool __z = (psr & PSR_Z_bit); 652 const bool __n = (psr & PSR_N_bit); 653 const bool __c = (psr & PSR_C_bit); 654 const bool __v = (psr & PSR_V_bit); 655 switch (__cond & ~1) { 656 case INSN_COND_EQ: // Z == 1 657 __ok = __z; 658 break; 659 case INSN_COND_CS: // C == 1 660 __ok = __c; 661 break; 662 case INSN_COND_MI: // N == 1 663 __ok = __n; 664 break; 665 case INSN_COND_VS: // V == 1 666 __ok = __v; 667 break; 668 case INSN_COND_HI: // C == 1 && Z == 0 669 __ok = __c && !__z; 670 break; 671 case INSN_COND_GE: // N == V 672 __ok = __n == __v; 673 break; 674 case INSN_COND_GT: // N == V && Z == 0 675 __ok = __n == __v && !__z; 676 break; 677 default: /* INSN_COND_AL or unconditional */ 678 return true; 679 } 680 681 return (__cond & 1) ? !__ok : __ok; 682 } 683 #endif /* !__ASSEMBLER && _KERNEL */ 684 685 #if !defined(__ASSEMBLER__) && !defined(_RUMPKERNEL) 686 #define ARMREG_READ_INLINE(name, __insnstring) \ 687 static inline uint32_t armreg_##name##_read(void) \ 688 { \ 689 uint32_t __rv; \ 690 __asm __volatile("mrc " __insnstring : "=r"(__rv)); \ 691 return __rv; \ 692 } 693 694 #define ARMREG_WRITE_INLINE(name, __insnstring) \ 695 static inline void armreg_##name##_write(uint32_t __val) \ 696 { \ 697 __asm __volatile("mcr " __insnstring :: "r"(__val)); \ 698 } 699 700 #define ARMREG_READ_INLINE2(name, __insnstring) \ 701 static inline uint32_t armreg_##name##_read(void) \ 702 { \ 703 uint32_t __rv; \ 704 __asm __volatile(".fpu vfp"); \ 705 __asm __volatile(__insnstring : "=r"(__rv)); \ 706 return __rv; \ 707 } 708 709 #define ARMREG_WRITE_INLINE2(name, __insnstring) \ 710 static inline void armreg_##name##_write(uint32_t __val) \ 711 { \ 712 __asm __volatile(".fpu vfp"); \ 713 __asm __volatile(__insnstring :: "r"(__val)); \ 714 } 715 716 #define ARMREG_READ64_INLINE(name, __insnstring) \ 717 static inline uint64_t armreg_##name##_read(void) \ 718 { \ 719 uint64_t __rv; \ 720 __asm __volatile("mrrc " __insnstring : "=r"(__rv)); \ 721 return __rv; \ 722 } 723 724 #define ARMREG_WRITE64_INLINE(name, __insnstring) \ 725 static inline void armreg_##name##_write(uint64_t __val) \ 726 { \ 727 __asm __volatile("mcrr " __insnstring :: "r"(__val)); \ 728 } 729 730 /* cp10 registers */ 731 ARMREG_READ_INLINE2(fpsid, "vmrs\t%0, fpsid") /* VFP System ID */ 732 ARMREG_READ_INLINE2(fpscr, "vmrs\t%0, fpscr") /* VFP Status/Control Register */ 733 ARMREG_WRITE_INLINE2(fpscr, "vmsr\tfpscr, %0") /* VFP Status/Control Register */ 734 ARMREG_READ_INLINE2(mvfr1, "vmrs\t%0, mvfr1") /* Media and VFP Feature Register 1 */ 735 ARMREG_READ_INLINE2(mvfr0, "vmrs\t%0, mvfr0") /* Media and VFP Feature Register 0 */ 736 ARMREG_READ_INLINE2(fpexc, "vmrs\t%0, fpexc") /* VFP Exception Register */ 737 ARMREG_WRITE_INLINE2(fpexc, "vmsr\tfpexc, %0") /* VFP Exception Register */ 738 ARMREG_READ_INLINE2(fpinst, "fmrx\t%0, fpinst") /* VFP Exception Instruction */ 739 ARMREG_WRITE_INLINE2(fpinst, "fmxr\tfpinst, %0") /* VFP Exception Instruction */ 740 ARMREG_READ_INLINE2(fpinst2, "fmrx\t%0, fpinst2") /* VFP Exception Instruction 2 */ 741 ARMREG_WRITE_INLINE2(fpinst2, "fmxr\tfpinst2, %0") /* VFP Exception Instruction 2 */ 742 743 /* cp15 c0 registers */ 744 ARMREG_READ_INLINE(midr, "p15,0,%0,c0,c0,0") /* Main ID Register */ 745 ARMREG_READ_INLINE(ctr, "p15,0,%0,c0,c0,1") /* Cache Type Register */ 746 ARMREG_READ_INLINE(tlbtr, "p15,0,%0,c0,c0,3") /* TLB Type Register */ 747 ARMREG_READ_INLINE(mpidr, "p15,0,%0,c0,c0,5") /* Multiprocess Affinity Register */ 748 ARMREG_READ_INLINE(revidr, "p15,0,%0,c0,c0,6") /* Revision ID Register */ 749 ARMREG_READ_INLINE(pfr0, "p15,0,%0,c0,c1,0") /* Processor Feature Register 0 */ 750 ARMREG_READ_INLINE(pfr1, "p15,0,%0,c0,c1,1") /* Processor Feature Register 1 */ 751 ARMREG_READ_INLINE(mmfr0, "p15,0,%0,c0,c1,4") /* Memory Model Feature Register 0 */ 752 ARMREG_READ_INLINE(mmfr1, "p15,0,%0,c0,c1,5") /* Memory Model Feature Register 1 */ 753 ARMREG_READ_INLINE(mmfr2, "p15,0,%0,c0,c1,6") /* Memory Model Feature Register 2 */ 754 ARMREG_READ_INLINE(mmfr3, "p15,0,%0,c0,c1,7") /* Memory Model Feature Register 3 */ 755 ARMREG_READ_INLINE(isar0, "p15,0,%0,c0,c2,0") /* Instruction Set Attribute Register 0 */ 756 ARMREG_READ_INLINE(isar1, "p15,0,%0,c0,c2,1") /* Instruction Set Attribute Register 1 */ 757 ARMREG_READ_INLINE(isar2, "p15,0,%0,c0,c2,2") /* Instruction Set Attribute Register 2 */ 758 ARMREG_READ_INLINE(isar3, "p15,0,%0,c0,c2,3") /* Instruction Set Attribute Register 3 */ 759 ARMREG_READ_INLINE(isar4, "p15,0,%0,c0,c2,4") /* Instruction Set Attribute Register 4 */ 760 ARMREG_READ_INLINE(isar5, "p15,0,%0,c0,c2,5") /* Instruction Set Attribute Register 5 */ 761 ARMREG_READ_INLINE(ccsidr, "p15,1,%0,c0,c0,0") /* Cache Size ID Register */ 762 ARMREG_READ_INLINE(clidr, "p15,1,%0,c0,c0,1") /* Cache Level ID Register */ 763 ARMREG_READ_INLINE(csselr, "p15,2,%0,c0,c0,0") /* Cache Size Selection Register */ 764 ARMREG_WRITE_INLINE(csselr, "p15,2,%0,c0,c0,0") /* Cache Size Selection Register */ 765 /* cp15 c1 registers */ 766 ARMREG_READ_INLINE(sctlr, "p15,0,%0,c1,c0,0") /* System Control Register */ 767 ARMREG_WRITE_INLINE(sctlr, "p15,0,%0,c1,c0,0") /* System Control Register */ 768 ARMREG_READ_INLINE(auxctl, "p15,0,%0,c1,c0,1") /* Auxiliary Control Register */ 769 ARMREG_WRITE_INLINE(auxctl, "p15,0,%0,c1,c0,1") /* Auxiliary Control Register */ 770 ARMREG_READ_INLINE(cpacr, "p15,0,%0,c1,c0,2") /* Co-Processor Access Control Register */ 771 ARMREG_WRITE_INLINE(cpacr, "p15,0,%0,c1,c0,2") /* Co-Processor Access Control Register */ 772 ARMREG_READ_INLINE(scr, "p15,0,%0,c1,c1,0") /* Secure Configuration Register */ 773 ARMREG_READ_INLINE(nsacr, "p15,0,%0,c1,c1,2") /* Non-Secure Access Control Register */ 774 /* cp15 c2 registers */ 775 ARMREG_READ_INLINE(ttbr, "p15,0,%0,c2,c0,0") /* Translation Table Base Register 0 */ 776 ARMREG_WRITE_INLINE(ttbr, "p15,0,%0,c2,c0,0") /* Translation Table Base Register 0 */ 777 ARMREG_READ_INLINE(ttbr1, "p15,0,%0,c2,c0,1") /* Translation Table Base Register 1 */ 778 ARMREG_WRITE_INLINE(ttbr1, "p15,0,%0,c2,c0,1") /* Translation Table Base Register 1 */ 779 ARMREG_READ_INLINE(ttbcr, "p15,0,%0,c2,c0,2") /* Translation Table Base Register */ 780 ARMREG_WRITE_INLINE(ttbcr, "p15,0,%0,c2,c0,2") /* Translation Table Base Register */ 781 /* cp15 c3 registers */ 782 ARMREG_READ_INLINE(dacr, "p15,0,%0,c3,c0,0") /* Domain Access Control Register */ 783 ARMREG_WRITE_INLINE(dacr, "p15,0,%0,c3,c0,0") /* Domain Access Control Register */ 784 /* cp15 c5 registers */ 785 ARMREG_READ_INLINE(dfsr, "p15,0,%0,c5,c0,0") /* Data Fault Status Register */ 786 ARMREG_READ_INLINE(ifsr, "p15,0,%0,c5,c0,1") /* Instruction Fault Status Register */ 787 /* cp15 c6 registers */ 788 ARMREG_READ_INLINE(dfar, "p15,0,%0,c6,c0,0") /* Data Fault Address Register */ 789 ARMREG_READ_INLINE(ifar, "p15,0,%0,c6,c0,2") /* Instruction Fault Address Register */ 790 /* cp15 c7 registers */ 791 ARMREG_WRITE_INLINE(icialluis, "p15,0,%0,c7,c1,0") /* Instruction Inv All (IS) */ 792 ARMREG_WRITE_INLINE(bpiallis, "p15,0,%0,c7,c1,6") /* Branch Predictor Invalidate All (IS) */ 793 ARMREG_READ_INLINE(par, "p15,0,%0,c7,c4,0") /* Physical Address Register */ 794 ARMREG_WRITE_INLINE(iciallu, "p15,0,%0,c7,c5,0") /* Instruction Invalidate All */ 795 ARMREG_WRITE_INLINE(icimvau, "p15,0,%0,c7,c5,1") /* Instruction Invalidate MVA */ 796 ARMREG_WRITE_INLINE(isb, "p15,0,%0,c7,c5,4") /* Instruction Synchronization Barrier */ 797 ARMREG_WRITE_INLINE(bpiall, "p15,0,%0,c7,c5,6") /* Branch Predictor Invalidate All */ 798 ARMREG_WRITE_INLINE(bpimva, "p15,0,%0,c7,c5,7") /* Branch Predictor invalidate by MVA */ 799 ARMREG_WRITE_INLINE(dcimvac, "p15,0,%0,c7,c6,1") /* Data Invalidate MVA to PoC */ 800 ARMREG_WRITE_INLINE(dcisw, "p15,0,%0,c7,c6,2") /* Data Invalidate Set/Way */ 801 ARMREG_WRITE_INLINE(ats1cpr, "p15,0,%0,c7,c8,0") /* AddrTrans CurState PL1 Read */ 802 ARMREG_WRITE_INLINE(ats1cpw, "p15,0,%0,c7,c8,1") /* AddrTrans CurState PL1 Write */ 803 ARMREG_WRITE_INLINE(ats1cur, "p15,0,%0,c7,c8,2") /* AddrTrans CurState PL0 Read */ 804 ARMREG_WRITE_INLINE(ats1cuw, "p15,0,%0,c7,c8,3") /* AddrTrans CurState PL0 Write */ 805 ARMREG_WRITE_INLINE(dccmvac, "p15,0,%0,c7,c10,1") /* Data Clean MVA to PoC */ 806 ARMREG_WRITE_INLINE(dccsw, "p15,0,%0,c7,c10,2") /* Data Clean Set/Way */ 807 ARMREG_WRITE_INLINE(dsb, "p15,0,%0,c7,c10,4") /* Data Synchronization Barrier */ 808 ARMREG_WRITE_INLINE(dmb, "p15,0,%0,c7,c10,5") /* Data Memory Barrier */ 809 ARMREG_WRITE_INLINE(dccmvau, "p15,0,%0,c7,c11,1") /* Data Clean MVA to PoU */ 810 ARMREG_WRITE_INLINE(dccimvac, "p15,0,%0,c7,c14,1") /* Data Clean&Inv MVA to PoC */ 811 ARMREG_WRITE_INLINE(dccisw, "p15,0,%0,c7,c14,2") /* Data Clean&Inv Set/Way */ 812 /* cp15 c8 registers */ 813 ARMREG_WRITE_INLINE(tlbiallis, "p15,0,%0,c8,c3,0") /* Invalidate entire unified TLB, inner shareable */ 814 ARMREG_WRITE_INLINE(tlbimvais, "p15,0,%0,c8,c3,1") /* Invalidate unified TLB by MVA, inner shareable */ 815 ARMREG_WRITE_INLINE(tlbiasidis, "p15,0,%0,c8,c3,2") /* Invalidate unified TLB by ASID, inner shareable */ 816 ARMREG_WRITE_INLINE(tlbimvaais, "p15,0,%0,c8,c3,3") /* Invalidate unified TLB by MVA, all ASID, inner shareable */ 817 ARMREG_WRITE_INLINE(itlbiall, "p15,0,%0,c8,c5,0") /* Invalidate entire instruction TLB */ 818 ARMREG_WRITE_INLINE(itlbimva, "p15,0,%0,c8,c5,1") /* Invalidate instruction TLB by MVA */ 819 ARMREG_WRITE_INLINE(itlbiasid, "p15,0,%0,c8,c5,2") /* Invalidate instruction TLB by ASID */ 820 ARMREG_WRITE_INLINE(dtlbiall, "p15,0,%0,c8,c6,0") /* Invalidate entire data TLB */ 821 ARMREG_WRITE_INLINE(dtlbimva, "p15,0,%0,c8,c6,1") /* Invalidate data TLB by MVA */ 822 ARMREG_WRITE_INLINE(dtlbiasid, "p15,0,%0,c8,c6,2") /* Invalidate data TLB by ASID */ 823 ARMREG_WRITE_INLINE(tlbiall, "p15,0,%0,c8,c7,0") /* Invalidate entire unified TLB */ 824 ARMREG_WRITE_INLINE(tlbimva, "p15,0,%0,c8,c7,1") /* Invalidate unified TLB by MVA */ 825 ARMREG_WRITE_INLINE(tlbiasid, "p15,0,%0,c8,c7,2") /* Invalidate unified TLB by ASID */ 826 ARMREG_WRITE_INLINE(tlbimvaa, "p15,0,%0,c8,c7,3") /* Invalidate unified TLB by MVA, all ASID */ 827 /* cp15 c9 registers */ 828 ARMREG_READ_INLINE(pmcr, "p15,0,%0,c9,c12,0") /* PMC Control Register */ 829 ARMREG_WRITE_INLINE(pmcr, "p15,0,%0,c9,c12,0") /* PMC Control Register */ 830 ARMREG_READ_INLINE(pmcntenset, "p15,0,%0,c9,c12,1") /* PMC Count Enable Set */ 831 ARMREG_WRITE_INLINE(pmcntenset, "p15,0,%0,c9,c12,1") /* PMC Count Enable Set */ 832 ARMREG_READ_INLINE(pmcntenclr, "p15,0,%0,c9,c12,2") /* PMC Count Enable Clear */ 833 ARMREG_WRITE_INLINE(pmcntenclr, "p15,0,%0,c9,c12,2") /* PMC Count Enable Clear */ 834 ARMREG_READ_INLINE(pmovsr, "p15,0,%0,c9,c12,3") /* PMC Overflow Flag Status */ 835 ARMREG_WRITE_INLINE(pmovsr, "p15,0,%0,c9,c12,3") /* PMC Overflow Flag Status */ 836 ARMREG_READ_INLINE(pmccntr, "p15,0,%0,c9,c13,0") /* PMC Cycle Counter */ 837 ARMREG_WRITE_INLINE(pmccntr, "p15,0,%0,c9,c13,0") /* PMC Cycle Counter */ 838 ARMREG_READ_INLINE(pmuserenr, "p15,0,%0,c9,c14,0") /* PMC User Enable */ 839 ARMREG_WRITE_INLINE(pmuserenr, "p15,0,%0,c9,c14,0") /* PMC User Enable */ 840 ARMREG_READ_INLINE(pmintenset, "p15,0,%0,c9,c14,1") /* PMC Interrupt Enable Set */ 841 ARMREG_WRITE_INLINE(pmintenset, "p15,0,%0,c9,c14,1") /* PMC Interrupt Enable Set */ 842 ARMREG_READ_INLINE(pmintenclr, "p15,0,%0,c9,c14,2") /* PMC Interrupt Enable Clear */ 843 ARMREG_WRITE_INLINE(pmintenclr, "p15,0,%0,c9,c14,2") /* PMC Interrupt Enable Clear */ 844 ARMREG_READ_INLINE(l2ctrl, "p15,1,%0,c9,c0,2") /* A7/A15 L2 Control Register */ 845 /* cp10 c10 registers */ 846 ARMREG_READ_INLINE(prrr, "p15,0,%0,c10,c2,0") /* Primary Region Remap Register */ 847 ARMREG_WRITE_INLINE(prrr, "p15,0,%0,c10,c2,0") /* Primary Region Remap Register */ 848 ARMREG_READ_INLINE(nrrr, "p15,0,%0,c10,c2,1") /* Normal Region Remap Register */ 849 ARMREG_WRITE_INLINE(nrrr, "p15,0,%0,c10,c2,1") /* Normal Region Remap Register */ 850 /* cp15 c13 registers */ 851 ARMREG_READ_INLINE(contextidr, "p15,0,%0,c13,c0,1") /* Context ID Register */ 852 ARMREG_WRITE_INLINE(contextidr, "p15,0,%0,c13,c0,1") /* Context ID Register */ 853 ARMREG_READ_INLINE(tpidrurw, "p15,0,%0,c13,c0,2") /* User read-write Thread ID Register */ 854 ARMREG_WRITE_INLINE(tpidrurw, "p15,0,%0,c13,c0,2") /* User read-write Thread ID Register */ 855 ARMREG_READ_INLINE(tpidruro, "p15,0,%0,c13,c0,3") /* User read-only Thread ID Register */ 856 ARMREG_WRITE_INLINE(tpidruro, "p15,0,%0,c13,c0,3") /* User read-only Thread ID Register */ 857 ARMREG_READ_INLINE(tpidrprw, "p15,0,%0,c13,c0,4") /* PL1 only Thread ID Register */ 858 ARMREG_WRITE_INLINE(tpidrprw, "p15,0,%0,c13,c0,4") /* PL1 only Thread ID Register */ 859 /* cp14 c12 registers */ 860 ARMREG_READ_INLINE(vbar, "p15,0,%0,c12,c0,0") /* Vector Base Address Register */ 861 ARMREG_WRITE_INLINE(vbar, "p15,0,%0,c12,c0,0") /* Vector Base Address Register */ 862 /* cp15 c14 registers */ 863 /* cp15 Global Timer Registers */ 864 ARMREG_READ_INLINE(cnt_frq, "p15,0,%0,c14,c0,0") /* Counter Frequency Register */ 865 ARMREG_WRITE_INLINE(cnt_frq, "p15,0,%0,c14,c0,0") /* Counter Frequency Register */ 866 ARMREG_READ_INLINE(cntk_ctl, "p15,0,%0,c14,c1,0") /* Timer PL1 Control Register */ 867 ARMREG_WRITE_INLINE(cntk_ctl, "p15,0,%0,c14,c1,0") /* Timer PL1 Control Register */ 868 ARMREG_READ_INLINE(cntp_tval, "p15,0,%0,c14,c2,0") /* PL1 Physical TimerValue Register */ 869 ARMREG_WRITE_INLINE(cntp_tval, "p15,0,%0,c14,c2,0") /* PL1 Physical TimerValue Register */ 870 ARMREG_READ_INLINE(cntp_ctl, "p15,0,%0,c14,c2,1") /* PL1 Physical Timer Control Register */ 871 ARMREG_WRITE_INLINE(cntp_ctl, "p15,0,%0,c14,c2,1") /* PL1 Physical Timer Control Register */ 872 ARMREG_READ_INLINE(cntv_tval, "p15,0,%0,c14,c3,0") /* Virtual TimerValue Register */ 873 ARMREG_WRITE_INLINE(cntv_tval, "p15,0,%0,c14,c3,0") /* Virtual TimerValue Register */ 874 ARMREG_READ_INLINE(cntv_ctl, "p15,0,%0,c14,c3,1") /* Virtual Timer Control Register */ 875 ARMREG_WRITE_INLINE(cntv_ctl, "p15,0,%0,c14,c3,1") /* Virtual Timer Control Register */ 876 ARMREG_READ64_INLINE(cntp_ct, "p15,0,%Q0,%R0,c14") /* Physical Count Register */ 877 ARMREG_WRITE64_INLINE(cntp_ct, "p15,0,%Q0,%R0,c14") /* Physical Count Register */ 878 ARMREG_READ64_INLINE(cntv_ct, "p15,1,%Q0,%R0,c14") /* Virtual Count Register */ 879 ARMREG_WRITE64_INLINE(cntv_ct, "p15,1,%Q0,%R0,c14") /* Virtual Count Register */ 880 ARMREG_READ64_INLINE(cntp_cval, "p15,2,%Q0,%R0,c14") /* PL1 Physical Timer CompareValue Register */ 881 ARMREG_WRITE64_INLINE(cntp_cval, "p15,2,%Q0,%R0,c14") /* PL1 Physical Timer CompareValue Register */ 882 ARMREG_READ64_INLINE(cntv_cval, "p15,3,%Q0,%R0,c14") /* PL1 Virtual Timer CompareValue Register */ 883 ARMREG_WRITE64_INLINE(cntv_cval, "p15,3,%Q0,%R0,c14") /* PL1 Virtual Timer CompareValue Register */ 884 ARMREG_READ64_INLINE(cntvoff, "p15,4,%Q0,%R0,c14") /* Virtual Offset Register */ 885 ARMREG_WRITE64_INLINE(cntvoff, "p15,4,%Q0,%R0,c14") /* Virtual Offset Register */ 886 /* cp15 c15 registers */ 887 ARMREG_READ_INLINE(cbar, "p15,4,%0,c15,c0,0") /* Configuration Base Address Register */ 888 ARMREG_READ_INLINE(pmcrv6, "p15,0,%0,c15,c12,0") /* PMC Control Register (armv6) */ 889 ARMREG_WRITE_INLINE(pmcrv6, "p15,0,%0,c15,c12,0") /* PMC Control Register (armv6) */ 890 ARMREG_READ_INLINE(pmccntrv6, "p15,0,%0,c15,c12,1") /* PMC Cycle Counter (armv6) */ 891 ARMREG_WRITE_INLINE(pmccntrv6, "p15,0,%0,c15,c12,1") /* PMC Cycle Counter (armv6) */ 892 893 ARMREG_READ_INLINE(tlbdata0, "p15,3,%0,c15,c0,0") /* TLB Data Register 0 (cortex) */ 894 ARMREG_READ_INLINE(tlbdata1, "p15,3,%0,c15,c0,1") /* TLB Data Register 1 (cortex) */ 895 ARMREG_READ_INLINE(tlbdata2, "p15,3,%0,c15,c0,2") /* TLB Data Register 2 (cortex) */ 896 ARMREG_WRITE_INLINE(tlbdataop, "p15,3,%0,c15,c4,2") /* TLB Data Read Operation (cortex) */ 897 898 ARMREG_READ_INLINE(sheeva_xctrl, "p15,1,%0,c15,c1,0") /* Sheeva eXtra Control register */ 899 ARMREG_WRITE_INLINE(sheeva_xctrl, "p15,1,%0,c15,c1,0") /* Sheeva eXtra Control register */ 900 901 #endif /* !__ASSEMBLER__ */ 902 903 #endif /* _ARM_ARMREG_H */ 904
Indexes created Mon Sep 29 18:09:42 GMT 2025