armreg.h revision 1.27
1 /* $NetBSD: armreg.h,v 1.27 2003/09/06 08:43:02 rearnsha Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2001 Ben Harris 5 * Copyright (c) 1994-1996 Mark Brinicombe. 6 * Copyright (c) 1994 Brini. 7 * All rights reserved. 8 * 9 * This code is derived from software written for Brini by Mark Brinicombe 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by Brini. 22 * 4. The name of the company nor the name of the author may be used to 23 * endorse or promote products derived from this software without specific 24 * prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 27 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 28 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 29 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 30 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 31 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 32 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 */ 38 39 #ifndef _ARM_ARMREG_H 40 #define _ARM_ARMREG_H 41 42 /* 43 * ARM Process Status Register 44 * 45 * The picture in the ARM manuals looks like this: 46 * 3 3 2 2 2 2 47 * 1 0 9 8 7 6 8 7 6 5 4 0 48 * +-+-+-+-+-+-------------------------------------+-+-+-+---------+ 49 * |N|Z|C|V|Q| reserved |I|F|T|M M M M M| 50 * | | | | | | | | | |4 3 2 1 0| 51 * +-+-+-+-+-+-------------------------------------+-+-+-+---------+ 52 */ 53 54 #define PSR_FLAGS 0xf0000000 /* flags */ 55 #define PSR_N_bit (1 << 31) /* negative */ 56 #define PSR_Z_bit (1 << 30) /* zero */ 57 #define PSR_C_bit (1 << 29) /* carry */ 58 #define PSR_V_bit (1 << 28) /* overflow */ 59 60 #define PSR_Q_bit (1 << 27) /* saturation */ 61 62 #define I32_bit (1 << 7) /* IRQ disable */ 63 #define F32_bit (1 << 6) /* FIQ disable */ 64 65 #define PSR_T_bit (1 << 5) /* Thumb state */ 66 #define PSR_J_bit (1 << 24) /* Java mode */ 67 68 #define PSR_MODE 0x0000001f /* mode mask */ 69 #define PSR_USR26_MODE 0x00000000 70 #define PSR_FIQ26_MODE 0x00000001 71 #define PSR_IRQ26_MODE 0x00000002 72 #define PSR_SVC26_MODE 0x00000003 73 #define PSR_USR32_MODE 0x00000010 74 #define PSR_FIQ32_MODE 0x00000011 75 #define PSR_IRQ32_MODE 0x00000012 76 #define PSR_SVC32_MODE 0x00000013 77 #define PSR_ABT32_MODE 0x00000017 78 #define PSR_UND32_MODE 0x0000001b 79 #define PSR_SYS32_MODE 0x0000001f 80 #define PSR_32_MODE 0x00000010 81 82 #define PSR_IN_USR_MODE(psr) (!((psr) & 3)) /* XXX */ 83 #define PSR_IN_32_MODE(psr) ((psr) & PSR_32_MODE) 84 85 /* In 26-bit modes, the PSR is stuffed into R15 along with the PC. */ 86 87 #define R15_MODE 0x00000003 88 #define R15_MODE_USR 0x00000000 89 #define R15_MODE_FIQ 0x00000001 90 #define R15_MODE_IRQ 0x00000002 91 #define R15_MODE_SVC 0x00000003 92 93 #define R15_PC 0x03fffffc 94 95 #define R15_FIQ_DISABLE 0x04000000 96 #define R15_IRQ_DISABLE 0x08000000 97 98 #define R15_FLAGS 0xf0000000 99 #define R15_FLAG_N 0x80000000 100 #define R15_FLAG_Z 0x40000000 101 #define R15_FLAG_C 0x20000000 102 #define R15_FLAG_V 0x10000000 103 104 /* 105 * Co-processor 15: The system control co-processor. 106 */ 107 108 #define ARM_CP15_CPU_ID 0 109 110 /* 111 * The CPU ID register is theoretically structured, but the definitions of 112 * the fields keep changing. 113 */ 114 115 /* The high-order byte is always the implementor */ 116 #define CPU_ID_IMPLEMENTOR_MASK 0xff000000 117 #define CPU_ID_ARM_LTD 0x41000000 /* 'A' */ 118 #define CPU_ID_DEC 0x44000000 /* 'D' */ 119 #define CPU_ID_INTEL 0x69000000 /* 'i' */ 120 #define CPU_ID_TI 0x54000000 /* 'T' */ 121 122 /* How to decide what format the CPUID is in. */ 123 #define CPU_ID_ISOLD(x) (((x) & 0x0000f000) == 0x00000000) 124 #define CPU_ID_IS7(x) (((x) & 0x0000f000) == 0x00007000) 125 #define CPU_ID_ISNEW(x) (!CPU_ID_ISOLD(x) && !CPU_ID_IS7(x)) 126 127 /* On ARM3 and ARM6, this byte holds the foundry ID. */ 128 #define CPU_ID_FOUNDRY_MASK 0x00ff0000 129 #define CPU_ID_FOUNDRY_VLSI 0x00560000 130 131 /* On ARM7 it holds the architecture and variant (sub-model) */ 132 #define CPU_ID_7ARCH_MASK 0x00800000 133 #define CPU_ID_7ARCH_V3 0x00000000 134 #define CPU_ID_7ARCH_V4T 0x00800000 135 #define CPU_ID_7VARIANT_MASK 0x007f0000 136 137 /* On more recent ARMs, it does the same, but in a different format */ 138 #define CPU_ID_ARCH_MASK 0x000f0000 139 #define CPU_ID_ARCH_V3 0x00000000 140 #define CPU_ID_ARCH_V4 0x00010000 141 #define CPU_ID_ARCH_V4T 0x00020000 142 #define CPU_ID_ARCH_V5 0x00030000 143 #define CPU_ID_ARCH_V5T 0x00040000 144 #define CPU_ID_ARCH_V5TE 0x00050000 145 #define CPU_ID_VARIANT_MASK 0x00f00000 146 147 /* Next three nybbles are part number */ 148 #define CPU_ID_PARTNO_MASK 0x0000fff0 149 150 /* Intel XScale has sub fields in part number */ 151 #define CPU_ID_XSCALE_COREGEN_MASK 0x0000e000 /* core generation */ 152 #define CPU_ID_XSCALE_COREREV_MASK 0x00001c00 /* core revision */ 153 #define CPU_ID_XSCALE_PRODUCT_MASK 0x000003f0 /* product number */ 154 155 /* And finally, the revision number. */ 156 #define CPU_ID_REVISION_MASK 0x0000000f 157 158 /* Individual CPUs are probably best IDed by everything but the revision. */ 159 #define CPU_ID_CPU_MASK 0xfffffff0 160 161 /* Fake CPU IDs for ARMs without CP15 */ 162 #define CPU_ID_ARM2 0x41560200 163 #define CPU_ID_ARM250 0x41560250 164 165 /* Pre-ARM7 CPUs -- [15:12] == 0 */ 166 #define CPU_ID_ARM3 0x41560300 167 #define CPU_ID_ARM600 0x41560600 168 #define CPU_ID_ARM610 0x41560610 169 #define CPU_ID_ARM620 0x41560620 170 171 /* ARM7 CPUs -- [15:12] == 7 */ 172 #define CPU_ID_ARM700 0x41007000 /* XXX This is a guess. */ 173 #define CPU_ID_ARM710 0x41007100 174 #define CPU_ID_ARM7500 0x41027100 /* XXX This is a guess. */ 175 #define CPU_ID_ARM710A 0x41047100 /* inc ARM7100 */ 176 #define CPU_ID_ARM7500FE 0x41077100 177 #define CPU_ID_ARM710T 0x41807100 178 #define CPU_ID_ARM720T 0x41807200 179 #define CPU_ID_ARM740T8K 0x41807400 /* XXX no MMU, 8KB cache */ 180 #define CPU_ID_ARM740T4K 0x41817400 /* XXX no MMU, 4KB cache */ 181 182 /* Post-ARM7 CPUs */ 183 #define CPU_ID_ARM810 0x41018100 184 #define CPU_ID_ARM920T 0x41129200 185 #define CPU_ID_ARM922T 0x41029220 186 #define CPU_ID_ARM940T 0x41029400 /* XXX no MMU */ 187 #define CPU_ID_ARM946ES 0x41049460 /* XXX no MMU */ 188 #define CPU_ID_ARM966ES 0x41049660 /* XXX no MMU */ 189 #define CPU_ID_ARM966ESR1 0x41059660 /* XXX no MMU */ 190 #define CPU_ID_ARM1020E 0x4115a200 /* (AKA arm10 rev 1) */ 191 #define CPU_ID_ARM1022ES 0x4105a220 192 #define CPU_ID_SA110 0x4401a100 193 #define CPU_ID_SA1100 0x4401a110 194 #define CPU_ID_TI925T 0x54029250 195 #define CPU_ID_SA1110 0x6901b110 196 #define CPU_ID_IXP1200 0x6901c120 197 #define CPU_ID_80200 0x69052000 198 #define CPU_ID_PXA250 0x69052100 /* sans core revision */ 199 #define CPU_ID_PXA210 0x69052120 200 #define CPU_ID_PXA250A 0x69052100 /* 1st version Core */ 201 #define CPU_ID_PXA210A 0x69052120 /* 1st version Core */ 202 #define CPU_ID_PXA250B 0x69052900 /* 3rd version Core */ 203 #define CPU_ID_PXA210B 0x69052920 /* 3rd version Core */ 204 #define CPU_ID_PXA250C 0x69052d00 /* 4th version Core */ 205 #define CPU_ID_PXA210C 0x69052d20 /* 4th version Core */ 206 #define CPU_ID_80321_400 0x69052420 207 #define CPU_ID_80321_600 0x69052430 208 #define CPU_ID_80321_400_B0 0x69052c20 209 #define CPU_ID_80321_600_B0 0x69052c30 210 #define CPU_ID_IXP425_533 0x690541c0 211 #define CPU_ID_IXP425_400 0x690541d0 212 #define CPU_ID_IXP425_266 0x690541f0 213 214 /* ARM3-specific coprocessor 15 registers */ 215 #define ARM3_CP15_FLUSH 1 216 #define ARM3_CP15_CONTROL 2 217 #define ARM3_CP15_CACHEABLE 3 218 #define ARM3_CP15_UPDATEABLE 4 219 #define ARM3_CP15_DISRUPTIVE 5 220 221 /* ARM3 Control register bits */ 222 #define ARM3_CTL_CACHE_ON 0x00000001 223 #define ARM3_CTL_SHARED 0x00000002 224 #define ARM3_CTL_MONITOR 0x00000004 225 226 /* 227 * Post-ARM3 CP15 registers: 228 * 229 * 1 Control register 230 * 231 * 2 Translation Table Base 232 * 233 * 3 Domain Access Control 234 * 235 * 4 Reserved 236 * 237 * 5 Fault Status 238 * 239 * 6 Fault Address 240 * 241 * 7 Cache/write-buffer Control 242 * 243 * 8 TLB Control 244 * 245 * 9 Cache Lockdown 246 * 247 * 10 TLB Lockdown 248 * 249 * 11 Reserved 250 * 251 * 12 Reserved 252 * 253 * 13 Process ID (for FCSE) 254 * 255 * 14 Reserved 256 * 257 * 15 Implementation Dependent 258 */ 259 260 /* Some of the definitions below need cleaning up for V3/V4 architectures */ 261 262 /* CPU control register (CP15 register 1) */ 263 #define CPU_CONTROL_MMU_ENABLE 0x00000001 /* M: MMU/Protection unit enable */ 264 #define CPU_CONTROL_AFLT_ENABLE 0x00000002 /* A: Alignment fault enable */ 265 #define CPU_CONTROL_DC_ENABLE 0x00000004 /* C: IDC/DC enable */ 266 #define CPU_CONTROL_WBUF_ENABLE 0x00000008 /* W: Write buffer enable */ 267 #define CPU_CONTROL_32BP_ENABLE 0x00000010 /* P: 32-bit exception handlers */ 268 #define CPU_CONTROL_32BD_ENABLE 0x00000020 /* D: 32-bit addressing */ 269 #define CPU_CONTROL_LABT_ENABLE 0x00000040 /* L: Late abort enable */ 270 #define CPU_CONTROL_BEND_ENABLE 0x00000080 /* B: Big-endian mode */ 271 #define CPU_CONTROL_SYST_ENABLE 0x00000100 /* S: System protection bit */ 272 #define CPU_CONTROL_ROM_ENABLE 0x00000200 /* R: ROM protection bit */ 273 #define CPU_CONTROL_CPCLK 0x00000400 /* F: Implementation defined */ 274 #define CPU_CONTROL_BPRD_ENABLE 0x00000800 /* Z: Branch prediction enable */ 275 #define CPU_CONTROL_IC_ENABLE 0x00001000 /* I: IC enable */ 276 #define CPU_CONTROL_VECRELOC 0x00002000 /* V: Vector relocation */ 277 #define CPU_CONTROL_ROUNDROBIN 0x00004000 /* RR: Predictable replacement */ 278 #define CPU_CONTROL_V4COMPAT 0x00008000 /* L4: ARMv4 compat LDR R15 etc */ 279 280 #define CPU_CONTROL_IDC_ENABLE CPU_CONTROL_DC_ENABLE 281 282 /* XScale Auxillary Control Register (CP15 register 1, opcode2 1) */ 283 #define XSCALE_AUXCTL_K 0x00000001 /* dis. write buffer coalescing */ 284 #define XSCALE_AUXCTL_P 0x00000002 /* ECC protect page table access */ 285 #define XSCALE_AUXCTL_MD_WB_RA 0x00000000 /* mini-D$ wb, read-allocate */ 286 #define XSCALE_AUXCTL_MD_WB_RWA 0x00000010 /* mini-D$ wb, read/write-allocate */ 287 #define XSCALE_AUXCTL_MD_WT 0x00000020 /* mini-D$ wt, read-allocate */ 288 #define XSCALE_AUXCTL_MD_MASK 0x00000030 289 290 /* Cache type register definitions */ 291 #define CPU_CT_ISIZE(x) ((x) & 0xfff) /* I$ info */ 292 #define CPU_CT_DSIZE(x) (((x) >> 12) & 0xfff) /* D$ info */ 293 #define CPU_CT_S (1U << 24) /* split cache */ 294 #define CPU_CT_CTYPE(x) (((x) >> 25) & 0xf) /* cache type */ 295 296 #define CPU_CT_CTYPE_WT 0 /* write-through */ 297 #define CPU_CT_CTYPE_WB1 1 /* write-back, clean w/ read */ 298 #define CPU_CT_CTYPE_WB2 2 /* w/b, clean w/ cp15,7 */ 299 #define CPU_CT_CTYPE_WB6 6 /* w/b, cp15,7, lockdown fmt A */ 300 #define CPU_CT_CTYPE_WB7 7 /* w/b, cp15,7, lockdown fmt B */ 301 302 #define CPU_CT_xSIZE_LEN(x) ((x) & 0x3) /* line size */ 303 #define CPU_CT_xSIZE_M (1U << 2) /* multiplier */ 304 #define CPU_CT_xSIZE_ASSOC(x) (((x) >> 3) & 0x7) /* associativity */ 305 #define CPU_CT_xSIZE_SIZE(x) (((x) >> 6) & 0x7) /* size */ 306 307 /* Fault status register definitions */ 308 309 #define FAULT_TYPE_MASK 0x0f 310 #define FAULT_USER 0x10 311 312 #define FAULT_WRTBUF_0 0x00 /* Vector Exception */ 313 #define FAULT_WRTBUF_1 0x02 /* Terminal Exception */ 314 #define FAULT_BUSERR_0 0x04 /* External Abort on Linefetch -- Section */ 315 #define FAULT_BUSERR_1 0x06 /* External Abort on Linefetch -- Page */ 316 #define FAULT_BUSERR_2 0x08 /* External Abort on Non-linefetch -- Section */ 317 #define FAULT_BUSERR_3 0x0a /* External Abort on Non-linefetch -- Page */ 318 #define FAULT_BUSTRNL1 0x0c /* External abort on Translation -- Level 1 */ 319 #define FAULT_BUSTRNL2 0x0e /* External abort on Translation -- Level 2 */ 320 #define FAULT_ALIGN_0 0x01 /* Alignment */ 321 #define FAULT_ALIGN_1 0x03 /* Alignment */ 322 #define FAULT_TRANS_S 0x05 /* Translation -- Section */ 323 #define FAULT_TRANS_P 0x07 /* Translation -- Page */ 324 #define FAULT_DOMAIN_S 0x09 /* Domain -- Section */ 325 #define FAULT_DOMAIN_P 0x0b /* Domain -- Page */ 326 #define FAULT_PERM_S 0x0d /* Permission -- Section */ 327 #define FAULT_PERM_P 0x0f /* Permission -- Page */ 328 329 /* 330 * Address of the vector page, low and high versions. 331 */ 332 #define ARM_VECTORS_LOW 0x00000000U 333 #define ARM_VECTORS_HIGH 0xffff0000U 334 335 /* 336 * ARM Instructions 337 * 338 * 3 3 2 2 2 339 * 1 0 9 8 7 0 340 * +-------+-------------------------------------------------------+ 341 * | cond | instruction dependant | 342 * |c c c c| | 343 * +-------+-------------------------------------------------------+ 344 */ 345 346 #define INSN_SIZE 4 /* Always 4 bytes */ 347 #define INSN_COND_MASK 0xf0000000 /* Condition mask */ 348 #define INSN_COND_AL 0xe0000000 /* Always condition */ 349 350 #endif 351
Indexes created Fri Sep 26 20:09:58 GMT 2025