armreg.h revision 1.7
1 /* $NetBSD: armreg.h,v 1.7 2001/03/10 16:19:59 bjh21 Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2001 Ben Harris 5 * Copyright (c) 1994-1996 Mark Brinicombe. 6 * Copyright (c) 1994 Brini. 7 * All rights reserved. 8 * 9 * This code is derived from software written for Brini by Mark Brinicombe 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by Brini. 22 * 4. The name of the company nor the name of the author may be used to 23 * endorse or promote products derived from this software without specific 24 * prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 27 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 28 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 29 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 30 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 31 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 32 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 */ 38 39 #ifndef _ARM_ARMREG_H 40 #define _ARM_ARMREG_H 41 42 /* 43 * ARM Process Status Register 44 * 45 * The picture in the ARM manuals looks like this: 46 * 3 3 2 2 2 2 47 * 1 0 9 8 7 6 8 7 6 5 4 0 48 * +-+-+-+-+-+-------------------------------------+-+-+-+---------+ 49 * |N|Z|C|V|Q| reserved |I|F|T|M M M M M| 50 * | | | | | | | | | |4 3 2 1 0| 51 * +-+-+-+-+-+-------------------------------------+-+-+-+---------+ 52 */ 53 54 #define PSR_FLAGS 0xf0000000 /* flags */ 55 #define PSR_N_bit (1 << 31) /* negative */ 56 #define PSR_Z_bit (1 << 30) /* zero */ 57 #define PSR_C_bit (1 << 29) /* carry */ 58 #define PSR_V_bit (1 << 28) /* overflow */ 59 60 #define PSR_Q_bit (1 << 27) /* saturation */ 61 62 #define I32_bit (1 << 7) /* IRQ disable */ 63 #define F32_bit (1 << 6) /* FIQ disable */ 64 65 #define PSR_T_bit (1 << 5) /* Thumb state */ 66 67 #define PSR_MODE 0x0000001f /* mode mask */ 68 #define PSR_USR26_MODE 0x00000000 69 #define PSR_FIQ26_MODE 0x00000001 70 #define PSR_IRQ26_MODE 0x00000002 71 #define PSR_SVC26_MODE 0x00000003 72 #define PSR_USR32_MODE 0x00000010 73 #define PSR_FIQ32_MODE 0x00000011 74 #define PSR_IRQ32_MODE 0x00000012 75 #define PSR_SVC32_MODE 0x00000013 76 #define PSR_ABT32_MODE 0x00000017 77 #define PSR_UND32_MODE 0x0000001b 78 #define PSR_SYS32_MODE 0x0000001f 79 #define PSR_32_MODE 0x00000010 80 81 #define PSR_IN_USR_MODE(psr) (!((psr) & 3)) /* XXX */ 82 #define PSR_IN_32_MODE(psr) ((psr) & PSR_32_MODE) 83 84 /* In 26-bit modes, the PSR is stuffed into R15 along with the PC. */ 85 86 #define R15_MODE 0x00000003 87 #define R15_MODE_USR 0x00000000 88 #define R15_MODE_FIQ 0x00000001 89 #define R15_MODE_IRQ 0x00000002 90 #define R15_MODE_SVC 0x00000003 91 92 #define R15_PC 0x03fffffc 93 94 #define R15_FIQ_DISABLE 0x04000000 95 #define R15_IRQ_DISABLE 0x08000000 96 97 #define R15_FLAGS 0xf0000000 98 #define R15_FLAG_N 0x80000000 99 #define R15_FLAG_Z 0x40000000 100 #define R15_FLAG_C 0x20000000 101 #define R15_FLAG_V 0x10000000 102 103 /* 104 * Co-processor 15: The system control co-processor. 105 */ 106 107 #define ARM_CP15_CPU_ID 0 108 109 /* 110 * The CPU ID register is theoretically structured, but the definitions of 111 * the fields keep changing. 112 */ 113 114 /* The high-order byte is always the implementor */ 115 #define CPU_ID_IMPLEMENTOR_MASK 0xff000000 116 #define CPU_ID_ARM_LTD 0x41000000 /* 'A' */ 117 #define CPU_ID_DEC 0x44000000 /* 'D' */ 118 #define CPU_ID_INTEL 0x69000000 /* 'i' */ 119 120 /* How to decide what format the CPUID is in. */ 121 #define CPU_ID_ISOLD(x) (((x) & 0x0000f000) == 0x00000000) 122 #define CPU_ID_IS7(x) (((x) & 0x0000f000) == 0x00007000) 123 #define CPU_ID_ISNEW(x) (!CPU_ID_ISOLD(x) && !CPU_ID_IS7(x)) 124 125 /* On ARM3 and ARM6, this byte holds the foundry ID. */ 126 #define CPU_ID_FOUNDRY_MASK 0x00ff0000 127 #define CPU_ID_FOUNDRY_VLSI 0x00560000 128 129 /* On ARM7 it holds the architecture and variant (sub-model) */ 130 #define CPU_ID_7ARCH_MASK 0x00800000 131 #define CPU_ID_7ARCH_V3 0x00000000 132 #define CPU_ID_7ARCH_V4T 0x00800000 133 #define CPU_ID_7VARIANT_MASK 0x007f0000 134 135 /* On more recent ARMs, it does the same, but in a different format */ 136 #define CPU_ID_ARCH_MASK 0x000f0000 137 #define CPU_ID_ARCH_V3 0x00000000 138 #define CPU_ID_ARCH_V4 0x00010000 139 #define CPU_ID_ARCH_V4T 0x00020000 140 #define CPU_ID_ARCH_V5 0x00030000 141 #define CPU_ID_ARCH_V5T 0x00040000 142 #define CPU_ID_ARCH_V5TE 0x00050000 143 #define CPU_ID_VARIANT_MASK 0x00f00000 144 145 /* Next three nybbles are part number */ 146 #define CPU_ID_PARTNO_MASK 0x0000fff0 147 148 /* And finally, the revision number. */ 149 #define CPU_ID_REVISION_MASK 0x0000000f 150 151 /* Individual CPUs are probably best IDed by everything but the revision. */ 152 #define CPU_ID_CPU_MASK 0xfffffff0 153 154 /* Fake CPU IDs for ARMs without CP15 */ 155 #define CPU_ID_ARM2 0x41560200 156 #define CPU_ID_ARM250 0x41560250 157 158 /* Pre-ARM7 CPUs -- [15:12] == 0 */ 159 #define CPU_ID_ARM3 0x41560300 160 #define CPU_ID_ARM600 0x41560600 161 #define CPU_ID_ARM610 0x41560610 162 #define CPU_ID_ARM620 0x41560620 163 164 /* ARM7 CPUs -- [15:12] == 7 */ 165 #define CPU_ID_ARM700 0x41007000 /* XXX This is a guess. */ 166 #define CPU_ID_ARM710 0x41007100 167 #define CPU_ID_ARM7500 0x41027100 /* XXX This is a guess. */ 168 #define CPU_ID_ARM710A 0x41047100 /* inc ARM7100 */ 169 #define CPU_ID_ARM7500FE 0x41077100 170 #define CPU_ID_ARM710T 0x41807100 171 #define CPU_ID_ARM720T 0x41807200 172 #define CPU_ID_ARM740T8K 0x41807400 /* XXX no MMU, 8KB cache */ 173 #define CPU_ID_ARM740T4K 0x41817400 /* XXX no MMU, 4KB cache */ 174 175 /* Post-ARM7 CPUs */ 176 #define CPU_ID_ARM810 0x41018100 177 #define CPU_ID_ARM920T 0x41129200 178 #define CPU_ID_ARM922T 0x41029220 179 #define CPU_ID_ARM940T 0x41029400 /* XXX no MMU */ 180 #define CPU_ID_ARM946ES 0x41049460 /* XXX no MMU */ 181 #define CPU_ID_ARM966ES 0x41049660 /* XXX no MMU */ 182 #define CPU_ID_ARM966ESR1 0x41059660 /* XXX no MMU */ 183 #define CPU_ID_SA110 0x4401a100 184 #define CPU_ID_SA1100 0x4401a110 185 #define CPU_ID_SA1110 0x6901b110 186 #define CPU_ID_I80200 0x69052000 /* XScale core */ 187 188 /* ARM3-specific coprocessor 15 registers */ 189 #define ARM3_CP15_FLUSH 1 190 #define ARM3_CP15_CONTROL 2 191 #define ARM3_CP15_CACHEABLE 3 192 #define ARM3_CP15_UPDATEABLE 4 193 #define ARM3_CP15_DISRUPTIVE 5 194 195 /* ARM3 Control register bits */ 196 #define ARM3_CTL_CACHE_ON 0x00000001 197 #define ARM3_CTL_SHARED 0x00000002 198 #define ARM3_CTL_MONITOR 0x00000004 199 200 /* 201 * Post-ARM3 CP15 registers: 202 */ 203 /* Some of the definitions below need cleaning up for V3/V4 architectures */ 204 205 /* CPU control register (CP15 register 1) */ 206 #define CPU_CONTROL_MMU_ENABLE 0x00000001 /* M: MMU/Protection unit enable */ 207 #define CPU_CONTROL_AFLT_ENABLE 0x00000002 /* A: Alignment fault enable */ 208 #define CPU_CONTROL_DC_ENABLE 0x00000004 /* C: IDC/DC enable */ 209 #define CPU_CONTROL_WBUF_ENABLE 0x00000008 /* W: Write buffer enable */ 210 #define CPU_CONTROL_32BP_ENABLE 0x00000010 /* P: 32-bit exception handlers */ 211 #define CPU_CONTROL_32BD_ENABLE 0x00000020 /* D: 32-bit addressing */ 212 #define CPU_CONTROL_LABT_ENABLE 0x00000040 /* L: Late abort enable */ 213 #define CPU_CONTROL_BEND_ENABLE 0x00000080 /* B: Big-endian mode */ 214 #define CPU_CONTROL_SYST_ENABLE 0x00000100 /* S: System protection bit */ 215 #define CPU_CONTROL_ROM_ENABLE 0x00000200 /* R: ROM protection bit */ 216 #define CPU_CONTROL_CPCLK 0x00000400 /* F: Implementation defined */ 217 #define CPU_CONTROL_BPRD_ENABLE 0x00000800 /* Z: Branch prediction enable */ 218 #define CPU_CONTROL_IC_ENABLE 0x00001000 /* I: IC enable */ 219 #define CPU_CONTROL_VECRELOC 0x00002000 /* V: Vector relocation */ 220 #define CPU_CONTROL_ROUNDROBIN 0x00004000 /* RR: Predictable replacement */ 221 #define CPU_CONTROL_V4COMPAT 0x00008000 /* L4: ARMv4 compat LDR R15 etc */ 222 223 #define CPU_CONTROL_IDC_ENABLE CPU_CONTROL_DC_ENABLE 224 225 /* Cache type register definitions */ 226 #define CPU_CT_IINFO_MASK 0x00000fff 227 #define CPU_CT_IINFO_SHIFT 0 228 #define CPU_CT_DINFO_MASK 0x00fff000 229 #define CPU_CT_DINFO_SHIFT 12 230 #define CPU_CT_HARVARD 0x01000000 231 #define CPU_CT_TYPE_MASK 0x1e000000 232 /* "Info" subfields -- see ARM ARM for meanings. */ 233 #define CPU_CT_LINE_MASK 0x00000003 234 #define CPU_CT_M_BIT 0x00000004 235 #define CPU_CT_ASSOC_MASK 0x00000038 236 #define CPU_CT_SIZE_MASK 0x000001c0 237 238 /* Fault status register definitions */ 239 240 #define FAULT_TYPE_MASK 0x0f 241 #define FAULT_USER 0x10 242 243 #define FAULT_WRTBUF_0 0x00 /* Vector Exception */ 244 #define FAULT_WRTBUF_1 0x02 /* Terminal Exception */ 245 #define FAULT_BUSERR_0 0x04 /* External Abort on Linefetch -- Section */ 246 #define FAULT_BUSERR_1 0x06 /* External Abort on Linefetch -- Page */ 247 #define FAULT_BUSERR_2 0x08 /* External Abort on Non-linefetch -- Section */ 248 #define FAULT_BUSERR_3 0x0a /* External Abort on Non-linefetch -- Page */ 249 #define FAULT_BUSTRNL1 0x0c /* External abort on Translation -- Level 1 */ 250 #define FAULT_BUSTRNL2 0x0e /* External abort on Translation -- Level 2 */ 251 #define FAULT_ALIGN_0 0x01 /* Alignment */ 252 #define FAULT_ALIGN_1 0x03 /* Alignment */ 253 #define FAULT_TRANS_S 0x05 /* Translation -- Section */ 254 #define FAULT_TRANS_P 0x07 /* Translation -- Page */ 255 #define FAULT_DOMAIN_S 0x09 /* Domain -- Section */ 256 #define FAULT_DOMAIN_P 0x0b /* Domain -- Page */ 257 #define FAULT_PERM_S 0x0d /* Permission -- Section */ 258 #define FAULT_PERM_P 0x0f /* Permission -- Page */ 259 260 /* 261 * ARM Instructions 262 * 263 * 3 3 2 2 2 264 * 1 0 9 8 7 0 265 * +-------+-------------------------------------------------------+ 266 * | cond | instruction dependant | 267 * |c c c c| | 268 * +-------+-------------------------------------------------------+ 269 */ 270 271 #define INSN_SIZE 4 /* Always 4 bytes */ 272 #define INSN_COND_MASK 0xf0000000 /* Condition mask */ 273 #define INSN_COND_AL 0xe0000000 /* Always condition */ 274 275 #endif 276
Indexes created Wed Sep 24 22:09:59 GMT 2025