armreg.h revision 1.70
1 /* $NetBSD: armreg.h,v 1.70 2012/11/29 18:15:33 matt Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2001 Ben Harris 5 * Copyright (c) 1994-1996 Mark Brinicombe. 6 * Copyright (c) 1994 Brini. 7 * All rights reserved. 8 * 9 * This code is derived from software written for Brini by Mark Brinicombe 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by Brini. 22 * 4. The name of the company nor the name of the author may be used to 23 * endorse or promote products derived from this software without specific 24 * prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 27 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 28 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 29 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 30 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 31 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 32 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 */ 38 39 #ifndef _ARM_ARMREG_H 40 #define _ARM_ARMREG_H 41 42 /* 43 * ARM Process Status Register 44 * 45 * The picture in the ARM manuals looks like this: 46 * 3 3 2 2 2 2 47 * 1 0 9 8 7 6 8 7 6 5 4 0 48 * +-+-+-+-+-+-------------------------------------+-+-+-+---------+ 49 * |N|Z|C|V|Q| reserved |I|F|T|M M M M M| 50 * | | | | | | | | | |4 3 2 1 0| 51 * +-+-+-+-+-+-------------------------------------+-+-+-+---------+ 52 */ 53 54 #define PSR_FLAGS 0xf0000000 /* flags */ 55 #define PSR_N_bit (1 << 31) /* negative */ 56 #define PSR_Z_bit (1 << 30) /* zero */ 57 #define PSR_C_bit (1 << 29) /* carry */ 58 #define PSR_V_bit (1 << 28) /* overflow */ 59 60 #define PSR_Q_bit (1 << 27) /* saturation */ 61 62 #define I32_bit (1 << 7) /* IRQ disable */ 63 #define F32_bit (1 << 6) /* FIQ disable */ 64 #define IF32_bits (3 << 6) /* IRQ/FIQ disable */ 65 66 #define PSR_T_bit (1 << 5) /* Thumb state */ 67 #define PSR_J_bit (1 << 24) /* Java mode */ 68 69 #define PSR_MODE 0x0000001f /* mode mask */ 70 #define PSR_USR26_MODE 0x00000000 71 #define PSR_FIQ26_MODE 0x00000001 72 #define PSR_IRQ26_MODE 0x00000002 73 #define PSR_SVC26_MODE 0x00000003 74 #define PSR_USR32_MODE 0x00000010 75 #define PSR_FIQ32_MODE 0x00000011 76 #define PSR_IRQ32_MODE 0x00000012 77 #define PSR_SVC32_MODE 0x00000013 78 #define PSR_MON32_MODE 0x00000016 79 #define PSR_ABT32_MODE 0x00000017 80 #define PSR_HYP32_MODE 0x0000001a 81 #define PSR_UND32_MODE 0x0000001b 82 #define PSR_SYS32_MODE 0x0000001f 83 #define PSR_32_MODE 0x00000010 84 85 #define PSR_IN_USR_MODE(psr) (!((psr) & 3)) /* XXX */ 86 #define PSR_IN_32_MODE(psr) ((psr) & PSR_32_MODE) 87 88 /* In 26-bit modes, the PSR is stuffed into R15 along with the PC. */ 89 90 #define R15_MODE 0x00000003 91 #define R15_MODE_USR 0x00000000 92 #define R15_MODE_FIQ 0x00000001 93 #define R15_MODE_IRQ 0x00000002 94 #define R15_MODE_SVC 0x00000003 95 96 #define R15_PC 0x03fffffc 97 98 #define R15_FIQ_DISABLE 0x04000000 99 #define R15_IRQ_DISABLE 0x08000000 100 101 #define R15_FLAGS 0xf0000000 102 #define R15_FLAG_N 0x80000000 103 #define R15_FLAG_Z 0x40000000 104 #define R15_FLAG_C 0x20000000 105 #define R15_FLAG_V 0x10000000 106 107 /* 108 * Co-processor 15: The system control co-processor. 109 */ 110 111 #define ARM_CP15_CPU_ID 0 112 113 /* 114 * The CPU ID register is theoretically structured, but the definitions of 115 * the fields keep changing. 116 */ 117 118 /* The high-order byte is always the implementor */ 119 #define CPU_ID_IMPLEMENTOR_MASK 0xff000000 120 #define CPU_ID_ARM_LTD 0x41000000 /* 'A' */ 121 #define CPU_ID_DEC 0x44000000 /* 'D' */ 122 #define CPU_ID_INTEL 0x69000000 /* 'i' */ 123 #define CPU_ID_TI 0x54000000 /* 'T' */ 124 #define CPU_ID_MARVELL 0x56000000 /* 'V' */ 125 #define CPU_ID_FARADAY 0x66000000 /* 'f' */ 126 127 /* How to decide what format the CPUID is in. */ 128 #define CPU_ID_ISOLD(x) (((x) & 0x0000f000) == 0x00000000) 129 #define CPU_ID_IS7(x) (((x) & 0x0000f000) == 0x00007000) 130 #define CPU_ID_ISNEW(x) (!CPU_ID_ISOLD(x) && !CPU_ID_IS7(x)) 131 132 /* On ARM3 and ARM6, this byte holds the foundry ID. */ 133 #define CPU_ID_FOUNDRY_MASK 0x00ff0000 134 #define CPU_ID_FOUNDRY_VLSI 0x00560000 135 136 /* On ARM7 it holds the architecture and variant (sub-model) */ 137 #define CPU_ID_7ARCH_MASK 0x00800000 138 #define CPU_ID_7ARCH_V3 0x00000000 139 #define CPU_ID_7ARCH_V4T 0x00800000 140 #define CPU_ID_7VARIANT_MASK 0x007f0000 141 142 /* On more recent ARMs, it does the same, but in a different format */ 143 #define CPU_ID_ARCH_MASK 0x000f0000 144 #define CPU_ID_ARCH_V3 0x00000000 145 #define CPU_ID_ARCH_V4 0x00010000 146 #define CPU_ID_ARCH_V4T 0x00020000 147 #define CPU_ID_ARCH_V5 0x00030000 148 #define CPU_ID_ARCH_V5T 0x00040000 149 #define CPU_ID_ARCH_V5TE 0x00050000 150 #define CPU_ID_ARCH_V5TEJ 0x00060000 151 #define CPU_ID_ARCH_V6 0x00070000 152 #define CPU_ID_VARIANT_MASK 0x00f00000 153 154 /* Next three nybbles are part number */ 155 #define CPU_ID_PARTNO_MASK 0x0000fff0 156 157 /* Intel XScale has sub fields in part number */ 158 #define CPU_ID_XSCALE_COREGEN_MASK 0x0000e000 /* core generation */ 159 #define CPU_ID_XSCALE_COREREV_MASK 0x00001c00 /* core revision */ 160 #define CPU_ID_XSCALE_PRODUCT_MASK 0x000003f0 /* product number */ 161 162 /* And finally, the revision number. */ 163 #define CPU_ID_REVISION_MASK 0x0000000f 164 165 /* Individual CPUs are probably best IDed by everything but the revision. */ 166 #define CPU_ID_CPU_MASK 0xfffffff0 167 168 /* Fake CPU IDs for ARMs without CP15 */ 169 #define CPU_ID_ARM2 0x41560200 170 #define CPU_ID_ARM250 0x41560250 171 172 /* Pre-ARM7 CPUs -- [15:12] == 0 */ 173 #define CPU_ID_ARM3 0x41560300 174 #define CPU_ID_ARM600 0x41560600 175 #define CPU_ID_ARM610 0x41560610 176 #define CPU_ID_ARM620 0x41560620 177 178 /* ARM7 CPUs -- [15:12] == 7 */ 179 #define CPU_ID_ARM700 0x41007000 /* XXX This is a guess. */ 180 #define CPU_ID_ARM710 0x41007100 181 #define CPU_ID_ARM7500 0x41027100 182 #define CPU_ID_ARM710A 0x41047100 /* inc ARM7100 */ 183 #define CPU_ID_ARM7500FE 0x41077100 184 #define CPU_ID_ARM710T 0x41807100 185 #define CPU_ID_ARM720T 0x41807200 186 #define CPU_ID_ARM740T8K 0x41807400 /* XXX no MMU, 8KB cache */ 187 #define CPU_ID_ARM740T4K 0x41817400 /* XXX no MMU, 4KB cache */ 188 189 /* Post-ARM7 CPUs */ 190 #define CPU_ID_ARM810 0x41018100 191 #define CPU_ID_ARM920T 0x41129200 192 #define CPU_ID_ARM922T 0x41029220 193 #define CPU_ID_ARM926EJS 0x41069260 194 #define CPU_ID_ARM940T 0x41029400 /* XXX no MMU */ 195 #define CPU_ID_ARM946ES 0x41049460 /* XXX no MMU */ 196 #define CPU_ID_ARM966ES 0x41049660 /* XXX no MMU */ 197 #define CPU_ID_ARM966ESR1 0x41059660 /* XXX no MMU */ 198 #define CPU_ID_ARM1020E 0x4115a200 /* (AKA arm10 rev 1) */ 199 #define CPU_ID_ARM1022ES 0x4105a220 200 #define CPU_ID_ARM1026EJS 0x4106a260 201 #define CPU_ID_ARM11MPCORE 0x410fb020 202 #define CPU_ID_ARM1136JS 0x4107b360 203 #define CPU_ID_ARM1136JSR1 0x4117b360 204 #define CPU_ID_ARM1156T2S 0x4107b560 /* MPU only */ 205 #define CPU_ID_ARM1176JZS 0x410fb760 206 #define CPU_ID_ARM11_P(n) ((n & 0xff07f000) == 0x4107b000) 207 #define CPU_ID_CORTEXA5R0 0x410fc050 208 #define CPU_ID_CORTEXA8R1 0x411fc080 209 #define CPU_ID_CORTEXA8R2 0x412fc080 210 #define CPU_ID_CORTEXA8R3 0x413fc080 211 #define CPU_ID_CORTEXA9R2 0x411fc090 212 #define CPU_ID_CORTEXA9R3 0x412fc090 213 #define CPU_ID_CORTEXA9R4 0x413fc090 214 #define CPU_ID_CORTEXA15R2 0x412fc0f0 215 #define CPU_ID_CORTEXA15R3 0x413fc0f0 216 #define CPU_ID_CORTEX_P(n) ((n & 0xff0ff000) == 0x410fc000) 217 #define CPU_ID_CORTEX_A8_P(n) ((n & 0xff0ff0f0) == 0x410fc080) 218 #define CPU_ID_CORTEX_A9_P(n) ((n & 0xff0ff0f0) == 0x410fc090) 219 #define CPU_ID_SA110 0x4401a100 220 #define CPU_ID_SA1100 0x4401a110 221 #define CPU_ID_TI925T 0x54029250 222 #define CPU_ID_MV88FR571_VD 0x56155710 223 #define CPU_ID_MV88SV131 0x56251310 224 #define CPU_ID_FA526 0x66015260 225 #define CPU_ID_SA1110 0x6901b110 226 #define CPU_ID_IXP1200 0x6901c120 227 #define CPU_ID_80200 0x69052000 228 #define CPU_ID_PXA250 0x69052100 /* sans core revision */ 229 #define CPU_ID_PXA210 0x69052120 230 #define CPU_ID_PXA250A 0x69052100 /* 1st version Core */ 231 #define CPU_ID_PXA210A 0x69052120 /* 1st version Core */ 232 #define CPU_ID_PXA250B 0x69052900 /* 3rd version Core */ 233 #define CPU_ID_PXA210B 0x69052920 /* 3rd version Core */ 234 #define CPU_ID_PXA250C 0x69052d00 /* 4th version Core */ 235 #define CPU_ID_PXA210C 0x69052d20 /* 4th version Core */ 236 #define CPU_ID_PXA27X 0x69054110 237 #define CPU_ID_80321_400 0x69052420 238 #define CPU_ID_80321_600 0x69052430 239 #define CPU_ID_80321_400_B0 0x69052c20 240 #define CPU_ID_80321_600_B0 0x69052c30 241 #define CPU_ID_80219_400 0x69052e20 242 #define CPU_ID_80219_600 0x69052e30 243 #define CPU_ID_IXP425_533 0x690541c0 244 #define CPU_ID_IXP425_400 0x690541d0 245 #define CPU_ID_IXP425_266 0x690541f0 246 247 /* ARM3-specific coprocessor 15 registers */ 248 #define ARM3_CP15_FLUSH 1 249 #define ARM3_CP15_CONTROL 2 250 #define ARM3_CP15_CACHEABLE 3 251 #define ARM3_CP15_UPDATEABLE 4 252 #define ARM3_CP15_DISRUPTIVE 5 253 254 /* ARM3 Control register bits */ 255 #define ARM3_CTL_CACHE_ON 0x00000001 256 #define ARM3_CTL_SHARED 0x00000002 257 #define ARM3_CTL_MONITOR 0x00000004 258 259 /* 260 * Post-ARM3 CP15 registers: 261 * 262 * 1 Control register 263 * 264 * 2 Translation Table Base 265 * 266 * 3 Domain Access Control 267 * 268 * 4 Reserved 269 * 270 * 5 Fault Status 271 * 272 * 6 Fault Address 273 * 274 * 7 Cache/write-buffer Control 275 * 276 * 8 TLB Control 277 * 278 * 9 Cache Lockdown 279 * 280 * 10 TLB Lockdown 281 * 282 * 11 Reserved 283 * 284 * 12 Reserved 285 * 286 * 13 Process ID (for FCSE) 287 * 288 * 14 Reserved 289 * 290 * 15 Implementation Dependent 291 */ 292 293 /* Some of the definitions below need cleaning up for V3/V4 architectures */ 294 295 /* CPU control register (CP15 register 1) */ 296 #define CPU_CONTROL_MMU_ENABLE 0x00000001 /* M: MMU/Protection unit enable */ 297 #define CPU_CONTROL_AFLT_ENABLE 0x00000002 /* A: Alignment fault enable */ 298 #define CPU_CONTROL_DC_ENABLE 0x00000004 /* C: IDC/DC enable */ 299 #define CPU_CONTROL_WBUF_ENABLE 0x00000008 /* W: Write buffer enable */ 300 #define CPU_CONTROL_32BP_ENABLE 0x00000010 /* P: 32-bit exception handlers */ 301 #define CPU_CONTROL_32BD_ENABLE 0x00000020 /* D: 32-bit addressing */ 302 #define CPU_CONTROL_LABT_ENABLE 0x00000040 /* L: Late abort enable */ 303 #define CPU_CONTROL_BEND_ENABLE 0x00000080 /* B: Big-endian mode */ 304 #define CPU_CONTROL_SYST_ENABLE 0x00000100 /* S: System protection bit */ 305 #define CPU_CONTROL_ROM_ENABLE 0x00000200 /* R: ROM protection bit */ 306 #define CPU_CONTROL_CPCLK 0x00000400 /* F: Implementation defined */ 307 #define CPU_CONTROL_SWP_ENABLE 0x00000400 /* SW: SWP{B} perform normally. */ 308 #define CPU_CONTROL_BPRD_ENABLE 0x00000800 /* Z: Branch prediction enable */ 309 #define CPU_CONTROL_IC_ENABLE 0x00001000 /* I: IC enable */ 310 #define CPU_CONTROL_VECRELOC 0x00002000 /* V: Vector relocation */ 311 #define CPU_CONTROL_ROUNDROBIN 0x00004000 /* RR: Predictable replacement */ 312 #define CPU_CONTROL_V4COMPAT 0x00008000 /* L4: ARMv4 compat LDR R15 etc */ 313 #define CPU_CONTROL_FI_ENABLE 0x00200000 /* FI: Low interrupt latency */ 314 #define CPU_CONTROL_UNAL_ENABLE 0x00400000 /* U: unaligned data access */ 315 #define CPU_CONTROL_XP_ENABLE 0x00800000 /* XP: extended page table */ 316 #define CPU_CONTROL_V_ENABLE 0x01000000 /* VE: Interrupt vectors enable */ 317 #define CPU_CONTROL_EX_BEND 0x02000000 /* EE: exception endianness */ 318 #define CPU_CONTROL_NMFI 0x08000000 /* NMFI: Non maskable FIQ */ 319 #define CPU_CONTROL_TR_ENABLE 0x10000000 /* TRE: */ 320 #define CPU_CONTROL_AF_ENABLE 0x20000000 /* AFE: Access flag enable */ 321 #define CPU_CONTROL_TE_ENABLE 0x40000000 /* TE: Thumb Exception enable */ 322 323 #define CPU_CONTROL_IDC_ENABLE CPU_CONTROL_DC_ENABLE 324 325 /* ARMv6/ARMv7 Co-Processor Access Control Register (CP15, 0, c1, c0, 2) */ 326 #define CPACR_V7_ASEDIS 0x80000000 /* Disable Advanced SIMD Ext. */ 327 #define CPACR_V7_D32DIS 0x40000000 /* Disable VFP regs 15-31 */ 328 #define CPACR_CPn(n) (3 << (2*n)) 329 #define CPACR_NOACCESS 0 /* reset value */ 330 #define CPACR_PRIVED 1 /* Privileged mode access */ 331 #define CPACR_RESERVED 2 332 #define CPACR_ALL 3 /* Privileged and User mode access */ 333 334 /* ARM11x6 Auxiliary Control Register (CP15 register 1, opcode2 1) */ 335 #define ARM11X6_AUXCTL_RS 0x00000001 /* return stack */ 336 #define ARM11X6_AUXCTL_DB 0x00000002 /* dynamic branch prediction */ 337 #define ARM11X6_AUXCTL_SB 0x00000004 /* static branch prediction */ 338 #define ARM11X6_AUXCTL_TR 0x00000008 /* MicroTLB replacement strat. */ 339 #define ARM11X6_AUXCTL_EX 0x00000010 /* exclusive L1/L2 cache */ 340 #define ARM11X6_AUXCTL_RA 0x00000020 /* clean entire cache disable */ 341 #define ARM11X6_AUXCTL_RV 0x00000040 /* block transfer cache disable */ 342 #define ARM11X6_AUXCTL_CZ 0x00000080 /* restrict cache size */ 343 344 /* ARM1136 Auxiliary Control Register (CP15 register 1, opcode2 1) */ 345 #define ARM1136_AUXCTL_PFI 0x80000000 /* PFI: partial FI mode. */ 346 /* This is an undocumented flag 347 * used to work around a cache bug 348 * in r0 steppings. See errata 349 * 364296. 350 */ 351 /* ARM1176 Auxiliary Control Register (CP15 register 1, opcode2 1) */ 352 #define ARM1176_AUXCTL_PHD 0x10000000 /* inst. prefetch halting disable */ 353 #define ARM1176_AUXCTL_BFD 0x20000000 /* branch folding disable */ 354 #define ARM1176_AUXCTL_FSD 0x40000000 /* force speculative ops disable */ 355 #define ARM1176_AUXCTL_FIO 0x80000000 /* low intr latency override */ 356 357 /* Cortex-A9 Auxiliary Control Register (CP15 register 1, opcode2 1) */ 358 #define CORTEXA9_AUXCTL_PARITY 0x00000200 /* Enable parity */ 359 #define CORTEXA9_AUXCTL_1WAY 0x00000100 /* Alloc in one way only */ 360 #define CORTEXA9_AUXCTL_EXCL 0x00000080 /* Exclusive cache */ 361 #define CORTEXA9_AUXCTL_SMP 0x00000040 /* CPU is in SMP mode */ 362 #define CORTEXA9_AUXCTL_WRZERO 0x00000008 /* Write full line of zeroes */ 363 #define CORTEXA9_AUXCTL_L1PLD 0x00000004 /* L1 Dside prefetch */ 364 #define CORTEXA9_AUXCTL_L2PLD 0x00000002 /* L2 Dside prefetch */ 365 #define CORTEXA9_AUXCTL_FW 0x00000001 /* Forward Cache/TLB ops */ 366 367 /* XScale Auxiliary Control Register (CP15 register 1, opcode2 1) */ 368 #define XSCALE_AUXCTL_K 0x00000001 /* dis. write buffer coalescing */ 369 #define XSCALE_AUXCTL_P 0x00000002 /* ECC protect page table access */ 370 #define XSCALE_AUXCTL_MD_WB_RA 0x00000000 /* mini-D$ wb, read-allocate */ 371 #define XSCALE_AUXCTL_MD_WB_RWA 0x00000010 /* mini-D$ wb, read/write-allocate */ 372 #define XSCALE_AUXCTL_MD_WT 0x00000020 /* mini-D$ wt, read-allocate */ 373 #define XSCALE_AUXCTL_MD_MASK 0x00000030 374 375 /* ARM11 MPCore Auxiliary Control Register (CP15 register 1, opcode2 1) */ 376 #define MPCORE_AUXCTL_RS 0x00000001 /* return stack */ 377 #define MPCORE_AUXCTL_DB 0x00000002 /* dynamic branch prediction */ 378 #define MPCORE_AUXCTL_SB 0x00000004 /* static branch prediction */ 379 #define MPCORE_AUXCTL_F 0x00000008 /* instruction folding enable */ 380 #define MPCORE_AUXCTL_EX 0x00000010 /* exclusive L1/L2 cache */ 381 #define MPCORE_AUXCTL_SA 0x00000020 /* SMP/AMP */ 382 383 /* Cortex-A9 Auxiliary Control Register (CP15 register 1, opcode 1) */ 384 #define CORTEXA9_AUXCTL_FW 0x00000001 /* Cache and TLB updates broadcast */ 385 #define CORTEXA9_AUXCTL_L2_PLD 0x00000002 /* Prefetch hint enable */ 386 #define CORTEXA9_AUXCTL_L1_PLD 0x00000004 /* Data prefetch hint enable */ 387 #define CORTEXA9_AUXCTL_WR_ZERO 0x00000008 /* Ena. write full line of 0s mode */ 388 #define CORTEXA9_AUXCTL_SMP 0x00000040 /* Coherency is active */ 389 #define CORTEXA9_AUXCTL_EXCL 0x00000080 /* Exclusive cache bit */ 390 #define CORTEXA9_AUXCTL_ONEWAY 0x00000100 /* Allocate in on cache way only */ 391 #define CORTEXA9_AUXCTL_PARITY 0x00000200 /* Support parity checking */ 392 393 /* Marvell Feroceon Extra Features Register (CP15 register 1, opcode2 0) */ 394 #define FC_DCACHE_REPL_LOCK 0x80000000 /* Replace DCache Lock */ 395 #define FC_DCACHE_STREAM_EN 0x20000000 /* DCache Streaming Switch */ 396 #define FC_WR_ALLOC_EN 0x10000000 /* Enable Write Allocate */ 397 #define FC_L2_PREF_DIS 0x01000000 /* L2 Cache Prefetch Disable */ 398 #define FC_L2_INV_EVICT_LINE 0x00800000 /* L2 Invalidates Uncorrectable Error Line Eviction */ 399 #define FC_L2CACHE_EN 0x00400000 /* L2 enable */ 400 #define FC_ICACHE_REPL_LOCK 0x00080000 /* Replace ICache Lock */ 401 #define FC_GLOB_HIST_REG_EN 0x00040000 /* Branch Global History Register Enable */ 402 #define FC_BRANCH_TARG_BUF_DIS 0x00020000 /* Branch Target Buffer Disable */ 403 #define FC_L1_PAR_ERR_EN 0x00010000 /* L1 Parity Error Enable */ 404 405 /* Cache type register definitions 0 */ 406 #define CPU_CT_FORMAT(x) (((x) >> 29) & 0x7) /* reg format */ 407 #define CPU_CT_ISIZE(x) ((x) & 0xfff) /* I$ info */ 408 #define CPU_CT_DSIZE(x) (((x) >> 12) & 0xfff) /* D$ info */ 409 #define CPU_CT_S (1U << 24) /* split cache */ 410 #define CPU_CT_CTYPE(x) (((x) >> 25) & 0xf) /* cache type */ 411 412 #define CPU_CT_CTYPE_WT 0 /* write-through */ 413 #define CPU_CT_CTYPE_WB1 1 /* write-back, clean w/ read */ 414 #define CPU_CT_CTYPE_WB2 2 /* w/b, clean w/ cp15,7 */ 415 #define CPU_CT_CTYPE_WB6 6 /* w/b, cp15,7, lockdown fmt A */ 416 #define CPU_CT_CTYPE_WB7 7 /* w/b, cp15,7, lockdown fmt B */ 417 #define CPU_CT_CTYPE_WB14 14 /* w/b, cp15,7, lockdown fmt C */ 418 419 #define CPU_CT_xSIZE_LEN(x) ((x) & 0x3) /* line size */ 420 #define CPU_CT_xSIZE_M (1U << 2) /* multiplier */ 421 #define CPU_CT_xSIZE_ASSOC(x) (((x) >> 3) & 0x7) /* associativity */ 422 #define CPU_CT_xSIZE_SIZE(x) (((x) >> 6) & 0x7) /* size */ 423 #define CPU_CT_xSIZE_P (1U << 11) /* need to page-color */ 424 425 /* format 4 definitions */ 426 #define CPU_CT4_ILINE(x) ((x) & 0xf) /* I$ line size */ 427 #define CPU_CT4_DLINE(x) (((x) >> 16) & 0xf) /* D$ line size */ 428 #define CPU_CT4_L1IPOLICY(x) (((x) >> 14) & 0x3) /* I$ policy */ 429 #define CPU_CT4_L1_AIVIVT 1 /* ASID tagged VIVT */ 430 #define CPU_CT4_L1_VIPT 2 /* VIPT */ 431 #define CPU_CT4_L1_PIPT 3 /* PIPT */ 432 #define CPU_CT4_ERG(x) (((x) >> 20) & 0xf) /* Cache WriteBack Granule */ 433 #define CPU_CT4_CWG(x) (((x) >> 24) & 0xf) /* Exclusive Resv. Granule */ 434 435 /* Cache size identifaction register definitions 1, Rd, c0, c0, 0 */ 436 #define CPU_CSID_CTYPE_WT 0x80000000 /* write-through avail */ 437 #define CPU_CSID_CTYPE_WB 0x40000000 /* write-back avail */ 438 #define CPU_CSID_CTYPE_RA 0x20000000 /* read-allocation avail */ 439 #define CPU_CSID_CTYPE_WA 0x10000000 /* write-allocation avail */ 440 #define CPU_CSID_NUMSETS(x) (((x) >> 13) & 0x7fff) 441 #define CPU_CSID_ASSOC(x) (((x) >> 3) & 0x1ff) 442 #define CPU_CSID_LEN(x) ((x) & 0x07) 443 444 /* Cache size selection register definitions 2, Rd, c0, c0, 0 */ 445 #define CPU_CSSR_L2 0x00000002 446 #define CPU_CSSR_L1 0x00000000 447 #define CPU_CSSR_InD 0x00000001 448 449 /* Fault status register definitions */ 450 451 #define FAULT_TYPE_MASK 0x0f 452 #define FAULT_USER 0x10 453 454 #define FAULT_WRTBUF_0 0x00 /* Vector Exception */ 455 #define FAULT_WRTBUF_1 0x02 /* Terminal Exception */ 456 #define FAULT_BUSERR_0 0x04 /* External Abort on Linefetch -- Section */ 457 #define FAULT_BUSERR_1 0x06 /* External Abort on Linefetch -- Page */ 458 #define FAULT_BUSERR_2 0x08 /* External Abort on Non-linefetch -- Section */ 459 #define FAULT_BUSERR_3 0x0a /* External Abort on Non-linefetch -- Page */ 460 #define FAULT_BUSTRNL1 0x0c /* External abort on Translation -- Level 1 */ 461 #define FAULT_BUSTRNL2 0x0e /* External abort on Translation -- Level 2 */ 462 #define FAULT_ALIGN_0 0x01 /* Alignment */ 463 #define FAULT_ALIGN_1 0x03 /* Alignment */ 464 #define FAULT_TRANS_S 0x05 /* Translation -- Section */ 465 #define FAULT_TRANS_P 0x07 /* Translation -- Page */ 466 #define FAULT_DOMAIN_S 0x09 /* Domain -- Section */ 467 #define FAULT_DOMAIN_P 0x0b /* Domain -- Page */ 468 #define FAULT_PERM_S 0x0d /* Permission -- Section */ 469 #define FAULT_PERM_P 0x0f /* Permission -- Page */ 470 471 #define FAULT_IMPRECISE 0x400 /* Imprecise exception (XSCALE) */ 472 473 /* 474 * Address of the vector page, low and high versions. 475 */ 476 #define ARM_VECTORS_LOW 0x00000000U 477 #define ARM_VECTORS_HIGH 0xffff0000U 478 479 /* 480 * ARM Instructions 481 * 482 * 3 3 2 2 2 483 * 1 0 9 8 7 0 484 * +-------+-------------------------------------------------------+ 485 * | cond | instruction dependent | 486 * |c c c c| | 487 * +-------+-------------------------------------------------------+ 488 */ 489 490 #define INSN_SIZE 4 /* Always 4 bytes */ 491 #define INSN_COND_MASK 0xf0000000 /* Condition mask */ 492 #define INSN_COND_AL 0xe0000000 /* Always condition */ 493 494 #define THUMB_INSN_SIZE 2 /* Some are 4 bytes. */ 495 496 /* 497 * Defines and such for arm11 Performance Monitor Counters (p15, c15, c12, 0) 498 */ 499 #define ARM11_PMCCTL_E __BIT(0) /* enable all three counters */ 500 #define ARM11_PMCCTL_P __BIT(1) /* reset both Count Registers to zero */ 501 #define ARM11_PMCCTL_C __BIT(2) /* reset the Cycle Counter Register to zero */ 502 #define ARM11_PMCCTL_D __BIT(3) /* cycle count divide by 64 */ 503 #define ARM11_PMCCTL_EC0 __BIT(4) /* Enable Counter Register 0 interrupt */ 504 #define ARM11_PMCCTL_EC1 __BIT(5) /* Enable Counter Register 1 interrupt */ 505 #define ARM11_PMCCTL_ECC __BIT(6) /* Enable Cycle Counter interrupt */ 506 #define ARM11_PMCCTL_SBZa __BIT(7) /* UNP/SBZ */ 507 #define ARM11_PMCCTL_CR0 __BIT(8) /* Count Register 0 overflow flag */ 508 #define ARM11_PMCCTL_CR1 __BIT(9) /* Count Register 1 overflow flag */ 509 #define ARM11_PMCCTL_CCR __BIT(10) /* Cycle Count Register overflow flag */ 510 #define ARM11_PMCCTL_X __BIT(11) /* Enable Export of the events to the event bus */ 511 #define ARM11_PMCCTL_EVT1 __BITS(19,12) /* source of events for Count Register 1 */ 512 #define ARM11_PMCCTL_EVT0 __BITS(27,20) /* source of events for Count Register 0 */ 513 #define ARM11_PMCCTL_SBZb __BITS(31,28) /* UNP/SBZ */ 514 #define ARM11_PMCCTL_SBZ \ 515 (ARM11_PMCCTL_SBZa | ARM11_PMCCTL_SBZb) 516 517 #define ARM11_PMCEVT_ICACHE_MISS 0 /* Instruction Cache Miss */ 518 #define ARM11_PMCEVT_ISTREAM_STALL 1 /* Instruction Stream Stall */ 519 #define ARM11_PMCEVT_IUTLB_MISS 2 /* Instruction uTLB Miss */ 520 #define ARM11_PMCEVT_DUTLB_MISS 3 /* Data uTLB Miss */ 521 #define ARM11_PMCEVT_BRANCH 4 /* Branch Inst. Executed */ 522 #define ARM11_PMCEVT_BRANCH_MISS 6 /* Branch mispredicted */ 523 #define ARM11_PMCEVT_INST_EXEC 7 /* Instruction Executed */ 524 #define ARM11_PMCEVT_DCACHE_ACCESS0 9 /* Data Cache Access */ 525 #define ARM11_PMCEVT_DCACHE_ACCESS1 10 /* Data Cache Access */ 526 #define ARM11_PMCEVT_DCACHE_MISS 11 /* Data Cache Miss */ 527 #define ARM11_PMCEVT_DCACHE_WRITEBACK 12 /* Data Cache Writeback */ 528 #define ARM11_PMCEVT_PC_CHANGE 13 /* Software PC change */ 529 #define ARM11_PMCEVT_TLB_MISS 15 /* Main TLB Miss */ 530 #define ARM11_PMCEVT_DATA_ACCESS 16 /* non-cached data access */ 531 #define ARM11_PMCEVT_LSU_STALL 17 /* Load/Store Unit stall */ 532 #define ARM11_PMCEVT_WBUF_DRAIN 18 /* Write buffer drained */ 533 #define ARM11_PMCEVT_ETMEXTOUT0 32 /* ETMEXTOUT[0] asserted */ 534 #define ARM11_PMCEVT_ETMEXTOUT1 33 /* ETMEXTOUT[1] asserted */ 535 #define ARM11_PMCEVT_ETMEXTOUT 34 /* ETMEXTOUT[0 & 1] */ 536 #define ARM11_PMCEVT_CALL_EXEC 35 /* Procedure call executed */ 537 #define ARM11_PMCEVT_RETURN_EXEC 36 /* Return executed */ 538 #define ARM11_PMCEVT_RETURN_HIT 37 /* return address predicted */ 539 #define ARM11_PMCEVT_RETURN_MISS 38 /* return addr. mispredicted */ 540 #define ARM11_PMCEVT_CYCLE 255 /* Increment each cycle */ 541 542 /* Defines for ARM CORTEX performance counters */ 543 #define CORTEX_CNTENS_C __BIT(31) /* Enables the cycle counter */ 544 #define CORTEX_CNTENC_C __BIT(31) /* Disables the cycle counter */ 545 #define CORTEX_CNTOFL_C __BIT(31) /* Cycle counter overflow flag */ 546 547 #if !defined(__ASSEMBLER__) 548 #define ARMREG_READ_INLINE(name, __insnstring) \ 549 static inline uint32_t armreg_##name##_read(void) \ 550 { \ 551 uint32_t __rv; \ 552 __asm __volatile("mrc " __insnstring : "=r"(__rv)); \ 553 return __rv; \ 554 } 555 556 #define ARMREG_WRITE_INLINE(name, __insnstring) \ 557 static inline void armreg_##name##_write(uint32_t __val) \ 558 { \ 559 __asm __volatile("mcr " __insnstring :: "r"(__val)); \ 560 } 561 562 /* c0 registers */ 563 ARMREG_READ_INLINE(midr, "p15,0,%0,c0,c0,0") /* Main ID Register */ 564 ARMREG_READ_INLINE(ctr, "p15,0,%0,c0,c0,1") /* Cache Type Register */ 565 ARMREG_READ_INLINE(mpidr, "p15,0,%0,c0,c0,5") /* Multiprocess Affinity Register */ 566 ARMREG_READ_INLINE(pfr0, "p15,0,%0,c0,c1,0") /* Processor Feature Register 0 */ 567 ARMREG_READ_INLINE(pfr1, "p15,0,%0,c0,c1,1") /* Processor Feature Register 1 */ 568 ARMREG_READ_INLINE(mmfr0, "p15,0,%0,c0,c1,4") /* Memory Model Feature Register 0 */ 569 ARMREG_READ_INLINE(mmfr1, "p15,0,%0,c0,c1,5") /* Memory Model Feature Register 1 */ 570 ARMREG_READ_INLINE(mmfr2, "p15,0,%0,c0,c1,6") /* Memory Model Feature Register 2 */ 571 ARMREG_READ_INLINE(mmfr3, "p15,0,%0,c0,c1,7") /* Memory Model Feature Register 3 */ 572 ARMREG_READ_INLINE(isar0, "p15,0,%0,c0,c2,0") /* Instruction Set Attribute Register 0 */ 573 ARMREG_READ_INLINE(isar1, "p15,0,%0,c0,c2,1") /* Instruction Set Attribute Register 1 */ 574 ARMREG_READ_INLINE(isar2, "p15,0,%0,c0,c2,2") /* Instruction Set Attribute Register 2 */ 575 ARMREG_READ_INLINE(isar3, "p15,0,%0,c0,c2,3") /* Instruction Set Attribute Register 3 */ 576 ARMREG_READ_INLINE(isar4, "p15,0,%0,c0,c2,4") /* Instruction Set Attribute Register 4 */ 577 ARMREG_READ_INLINE(isar5, "p15,0,%0,c0,c2,5") /* Instruction Set Attribute Register 5 */ 578 ARMREG_READ_INLINE(ccsidr, "p15,1,%0,c0,c0,0") /* Cache Size ID Register */ 579 ARMREG_READ_INLINE(clidr, "p15,1,%0,c0,c0,1") /* Cache Level ID Register */ 580 ARMREG_READ_INLINE(csselr, "p15,2,%0,c0,c0,0") /* Cache Size Selection Register */ 581 ARMREG_WRITE_INLINE(csselr, "p15,2,%0,c0,c0,0") /* Cache Size Selection Register */ 582 /* c1 registers */ 583 ARMREG_READ_INLINE(sctrl, "p15,0,%0,c1,c0,0") /* System Control Register */ 584 ARMREG_WRITE_INLINE(sctrl, "p15,0,%0,c1,c0,0") /* System Control Register */ 585 ARMREG_READ_INLINE(auxctl, "p15,0,%0,c1,c0,1") /* Auxiliary Control Register */ 586 ARMREG_WRITE_INLINE(auxctl, "p15,0,%0,c1,c0,1") /* Auxiliary Control Register */ 587 ARMREG_READ_INLINE(cpacr, "p15,0,%0,c1,c0,2") /* Co-Processor Access Control Register */ 588 ARMREG_WRITE_INLINE(cpacr, "p15,0,%0,c1,c0,2") /* Co-Processor Access Control Register */ 589 /* c2 registers */ 590 ARMREG_READ_INLINE(ttbr, "p15,0,%0,c2,c0,0") /* Translation Table Base Register 0 */ 591 ARMREG_WRITE_INLINE(ttbr, "p15,0,%0,c2,c0,0") /* Translation Table Base Register 0 */ 592 ARMREG_READ_INLINE(ttbr1, "p15,0,%0,c2,c0,1") /* Translation Table Base Register 1 */ 593 ARMREG_WRITE_INLINE(ttbr1, "p15,0,%0,c2,c0,1") /* Translation Table Base Register 1 */ 594 ARMREG_READ_INLINE(ttbcr, "p15,0,%0,c2,c0,2") /* Translation Table Base Register */ 595 ARMREG_WRITE_INLINE(ttbcr, "p15,0,%0,c2,c0,2") /* Translation Table Base Register */ 596 /* c5 registers */ 597 ARMREG_READ_INLINE(dfsr, "p15,0,%0,c5,c0,0") /* Data Fault Status Register */ 598 ARMREG_READ_INLINE(ifsr, "p15,0,%0,c5,c0,1") /* Instruction Fault Status Register */ 599 /* c6 registers */ 600 ARMREG_READ_INLINE(dfar, "p15,0,%0,c6,c0,0") /* Data Fault Address Register */ 601 ARMREG_READ_INLINE(ifar, "p15,0,%0,c6,c0,2") /* Instruction Fault Address Register */ 602 /* c7 registers */ 603 ARMREG_WRITE_INLINE(icialluis, "p15,0,%0,c7,c1,0") /* Instruction Inv All (IS) */ 604 ARMREG_WRITE_INLINE(bpiallis, "p15,0,%0,c7,c1,6") /* Branch Invalidate All (IS) */ 605 ARMREG_READ_INLINE(par, "p15,0,%0,c7,c4,0") /* Physical Address Register */ 606 ARMREG_WRITE_INLINE(iciallu, "p15,0,%0,c7,c5,0") /* Instruction Invalidate All */ 607 ARMREG_WRITE_INLINE(icimvau, "p15,0,%0,c7,c5,1") /* Instruction Invalidate MVA */ 608 ARMREG_WRITE_INLINE(isb, "p15,0,%0,c7,c5,4") /* Instruction Synchronization Barrier */ 609 ARMREG_WRITE_INLINE(bpiall, "p15,0,%0,c5,c1,6") /* Breakpoint Invalidate All */ 610 ARMREG_WRITE_INLINE(dcimvac, "p15,0,%0,c7,c6,1") /* Data Invalidate MVA to PoC */ 611 ARMREG_WRITE_INLINE(dcisw, "p15,0,%0,c7,c6,2") /* Data Invalidate Set/Way */ 612 ARMREG_WRITE_INLINE(ats1cpr, "p15,0,%0,c7,c8,0") /* AddrTrans CurState PL1 Read */ 613 ARMREG_WRITE_INLINE(dccmvac, "p15,0,%0,c7,c10,1") /* Data Clean MVA to PoC */ 614 ARMREG_WRITE_INLINE(dccsw, "p15,0,%0,c7,c10,2") /* Data Clean Set/Way */ 615 ARMREG_WRITE_INLINE(dsb, "p15,0,%0,c7,c10,4") /* Data Synchronization Barrier */ 616 ARMREG_WRITE_INLINE(dmb, "p15,0,%0,c7,c10,5") /* Data Memory Barrier */ 617 ARMREG_WRITE_INLINE(dccmvau, "p15,0,%0,c7,c14,1") /* Data Clean MVA to PoU */ 618 ARMREG_WRITE_INLINE(dccimvac, "p15,0,%0,c7,c14,1") /* Data Clean&Inv MVA to PoC */ 619 ARMREG_WRITE_INLINE(dccisw, "p15,0,%0,c7,c14,2") /* Data Clean&Inv Set/Way */ 620 /* c9 registers */ 621 ARMREG_READ_INLINE(pmcr, "p15,0,%0,c9,c12,0") /* PMC Control Register */ 622 ARMREG_WRITE_INLINE(pmcr, "p15,0,%0,c9,c12,0") /* PMC Control Register */ 623 ARMREG_READ_INLINE(pmcntenset, "p15,0,%0,c9,c12,1") /* PMC Count Enable Set */ 624 ARMREG_WRITE_INLINE(pmcntenset, "p15,0,%0,c9,c12,1") /* PMC Count Enable Set */ 625 ARMREG_READ_INLINE(pmcntenclr, "p15,0,%0,c9,c12,2") /* PMC Count Enable Clear */ 626 ARMREG_WRITE_INLINE(pmcntenclr, "p15,0,%0,c9,c12,2") /* PMC Count Enable Clear */ 627 ARMREG_READ_INLINE(pmovsr, "p15,0,%0,c9,c12,3") /* PMC Overflow Flag Status */ 628 ARMREG_WRITE_INLINE(pmovsr, "p15,0,%0,c9,c12,3") /* PMC Overflow Flag Status */ 629 ARMREG_READ_INLINE(pmccntr, "p15,0,%0,c9,c13,0") /* PMC Cycle Counter */ 630 ARMREG_WRITE_INLINE(pmccntr, "p15,0,%0,c9,c13,0") /* PMC Cycle Counter */ 631 /* c13 registers */ 632 ARMREG_READ_INLINE(tpidrprw, "p15,0,%0,c13,c0,4") /* PL1 only Thread ID Register */ 633 ARMREG_WRITE_INLINE(tpidrprw, "p15,0,%0,c13,c0,4") /* PL1 only Thread ID Register */ 634 ARMREG_READ_INLINE(cbar, "p15,4,%0,c15,c0,0") /* Configuration Base Address Register */ 635 /* c13 registers */ 636 ARMREG_READ_INLINE(pmcrv6, "p15,0,%0,c15,c12,0") /* PMC Control Register (armv6) */ 637 ARMREG_WRITE_INLINE(pmcrv6, "p15,0,%0,c15,c12,0") /* PMC Control Register (armv6) */ 638 ARMREG_READ_INLINE(pmccntrv6, "p15,0,%0,c15,c12,1") /* PMC Cycle Counter (armv6) */ 639 ARMREG_WRITE_INLINE(pmccntrv6, "p15,0,%0,c15,c12,1") /* PMC Cycle Counter (armv6) */ 640 641 #endif /* !__ASSEMBLER__ */ 642 643 644 #define MPIDR_31 0x80000000 645 #define MPIDR_U 0x40000000 // 1 = Uniprocessor 646 #define MPIDR_MT 0x01000000 // AFF0 for SMT 647 #define MPIDR_AFF2 0x00ff0000 648 #define MPIDR_AFF1 0x0000ff00 649 #define MPIDR_AFF0 0x000000ff 650 651 #endif /* _ARM_ARMREG_H */ 652
Indexes created Fri Sep 26 20:09:58 GMT 2025