cpuconf.h revision 1.1.2.5
1 1.1.2.5 nathanw /* $NetBSD: cpuconf.h,v 1.1.2.5 2002/08/13 02:17:53 nathanw Exp $ */ 2 1.1.2.2 nathanw 3 1.1.2.2 nathanw /* 4 1.1.2.2 nathanw * Copyright (c 2002 Wasabi Systems, Inc. 5 1.1.2.2 nathanw * All rights reserved. 6 1.1.2.2 nathanw * 7 1.1.2.2 nathanw * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 1.1.2.2 nathanw * 9 1.1.2.2 nathanw * Redistribution and use in source and binary forms, with or without 10 1.1.2.2 nathanw * modification, are permitted provided that the following conditions 11 1.1.2.2 nathanw * are met: 12 1.1.2.2 nathanw * 1. Redistributions of source code must retain the above copyright 13 1.1.2.2 nathanw * notice, this list of conditions and the following disclaimer. 14 1.1.2.2 nathanw * 2. Redistributions in binary form must reproduce the above copyright 15 1.1.2.2 nathanw * notice, this list of conditions and the following disclaimer in the 16 1.1.2.2 nathanw * documentation and/or other materials provided with the distribution. 17 1.1.2.2 nathanw * 3. All advertising materials mentioning features or use of this software 18 1.1.2.2 nathanw * must display the following acknowledgement: 19 1.1.2.2 nathanw * This product includes software developed for the NetBSD Project by 20 1.1.2.2 nathanw * Wasabi Systems, Inc. 21 1.1.2.2 nathanw * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 1.1.2.2 nathanw * or promote products derived from this software without specific prior 23 1.1.2.2 nathanw * written permission. 24 1.1.2.2 nathanw * 25 1.1.2.2 nathanw * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 1.1.2.2 nathanw * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 1.1.2.2 nathanw * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 1.1.2.2 nathanw * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 1.1.2.2 nathanw * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 1.1.2.2 nathanw * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 1.1.2.2 nathanw * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 1.1.2.2 nathanw * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 1.1.2.2 nathanw * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 1.1.2.2 nathanw * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 1.1.2.2 nathanw * POSSIBILITY OF SUCH DAMAGE. 36 1.1.2.2 nathanw */ 37 1.1.2.2 nathanw 38 1.1.2.2 nathanw #ifndef _ARM_CPUCONF_H_ 39 1.1.2.2 nathanw #define _ARM_CPUCONF_H_ 40 1.1.2.2 nathanw 41 1.1.2.2 nathanw #if defined(_KERNEL_OPT) 42 1.1.2.2 nathanw #include "opt_cputypes.h" 43 1.1.2.2 nathanw #endif /* _KERNEL_OPT */ 44 1.1.2.2 nathanw 45 1.1.2.2 nathanw /* 46 1.1.2.2 nathanw * Step 1: Count the number of CPU types configured into the kernel. 47 1.1.2.2 nathanw */ 48 1.1.2.2 nathanw #if defined(_KERNEL_OPT) 49 1.1.2.2 nathanw #define CPU_NTYPES (defined(CPU_ARM2) + defined(CPU_ARM250) + \ 50 1.1.2.2 nathanw defined(CPU_ARM3) + \ 51 1.1.2.2 nathanw defined(CPU_ARM6) + defined(CPU_ARM7) + \ 52 1.1.2.2 nathanw defined(CPU_ARM7TDMI) + \ 53 1.1.2.2 nathanw defined(CPU_ARM8) + defined(CPU_ARM9) + \ 54 1.1.2.2 nathanw defined(CPU_SA110) + defined(CPU_SA1100) + \ 55 1.1.2.2 nathanw defined(CPU_SA1110) + \ 56 1.1.2.4 nathanw defined(CPU_IXP12X0) + \ 57 1.1.2.2 nathanw defined(CPU_XSCALE_80200) + \ 58 1.1.2.3 nathanw defined(CPU_XSCALE_80321) + \ 59 1.1.2.3 nathanw defined(CPU_XSCALE_PXA2X0)) 60 1.1.2.2 nathanw #else 61 1.1.2.2 nathanw #define CPU_NTYPES 2 62 1.1.2.2 nathanw #endif /* _KERNEL_OPT */ 63 1.1.2.2 nathanw 64 1.1.2.2 nathanw /* 65 1.1.2.2 nathanw * Step 2: Determine which ARM architecture versions are configured. 66 1.1.2.2 nathanw */ 67 1.1.2.2 nathanw #if !defined(_KERNEL_OPT) || \ 68 1.1.2.2 nathanw (defined(CPU_ARM2) || defined(CPU_ARM250) || defined(CPU_ARM3)) 69 1.1.2.2 nathanw #define ARM_ARCH_2 1 70 1.1.2.2 nathanw #else 71 1.1.2.2 nathanw #define ARM_ARCH_2 0 72 1.1.2.2 nathanw #endif 73 1.1.2.2 nathanw 74 1.1.2.2 nathanw #if !defined(_KERNEL_OPT) || \ 75 1.1.2.2 nathanw (defined(CPU_ARM6) || defined(CPU_ARM7)) 76 1.1.2.2 nathanw #define ARM_ARCH_3 1 77 1.1.2.2 nathanw #else 78 1.1.2.2 nathanw #define ARM_ARCH_3 0 79 1.1.2.2 nathanw #endif 80 1.1.2.2 nathanw 81 1.1.2.2 nathanw #if !defined(_KERNEL_OPT) || \ 82 1.1.2.2 nathanw (defined(CPU_ARM7TDMI) || defined(CPU_ARM8) || defined(CPU_ARM9) || \ 83 1.1.2.4 nathanw defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) || \ 84 1.1.2.4 nathanw defined(CPU_IXP12X0)) 85 1.1.2.2 nathanw #define ARM_ARCH_4 1 86 1.1.2.2 nathanw #else 87 1.1.2.2 nathanw #define ARM_ARCH_4 0 88 1.1.2.2 nathanw #endif 89 1.1.2.2 nathanw 90 1.1.2.2 nathanw #if !defined(_KERNEL_OPT) || \ 91 1.1.2.3 nathanw (defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ 92 1.1.2.3 nathanw defined(CPU_XSCALE_PXA2X0)) 93 1.1.2.2 nathanw #define ARM_ARCH_5 1 94 1.1.2.2 nathanw #else 95 1.1.2.2 nathanw #define ARM_ARCH_5 0 96 1.1.2.2 nathanw #endif 97 1.1.2.2 nathanw 98 1.1.2.2 nathanw #define ARM_NARCH (ARM_ARCH_2 + ARM_ARCH_3 + ARM_ARCH_4 + ARM_ARCH_5) 99 1.1.2.2 nathanw #if ARM_NARCH == 0 100 1.1.2.2 nathanw #error ARM_NARCH is 0 101 1.1.2.2 nathanw #endif 102 1.1.2.2 nathanw 103 1.1.2.2 nathanw /* 104 1.1.2.2 nathanw * Step 3: Define which MMU classes are configured: 105 1.1.2.2 nathanw * 106 1.1.2.2 nathanw * ARM_MMU_MEMC Prehistoric, external memory controller 107 1.1.2.2 nathanw * and MMU for ARMv2 CPUs. 108 1.1.2.2 nathanw * 109 1.1.2.2 nathanw * ARM_MMU_GENERIC Generic ARM MMU, compatible with ARM6. 110 1.1.2.2 nathanw * 111 1.1.2.2 nathanw * ARM_MMU_XSCALE XScale MMU. Compatible with generic ARM 112 1.1.2.2 nathanw * MMU, but also has several extensions which 113 1.1.2.2 nathanw * require different PTE layout to use. 114 1.1.2.2 nathanw */ 115 1.1.2.2 nathanw #if !defined(_KERNEL_OPT) || \ 116 1.1.2.2 nathanw (defined(CPU_ARM2) || defined(CPU_ARM250) || defined(CPU_ARM3)) 117 1.1.2.2 nathanw #define ARM_MMU_MEMC 1 118 1.1.2.2 nathanw #else 119 1.1.2.2 nathanw #define ARM_MMU_MEMC 0 120 1.1.2.2 nathanw #endif 121 1.1.2.2 nathanw 122 1.1.2.2 nathanw #if !defined(_KERNEL_OPT) || \ 123 1.1.2.2 nathanw (defined(CPU_ARM6) || defined(CPU_ARM7) || defined(CPU_ARM7TDMI) || \ 124 1.1.2.2 nathanw defined(CPU_ARM8) || defined(CPU_ARM9) || defined(CPU_SA110) || \ 125 1.1.2.4 nathanw defined(CPU_SA1100) || defined(CPU_SA1110) || defined(CPU_IXP12X0)) 126 1.1.2.2 nathanw #define ARM_MMU_GENERIC 1 127 1.1.2.2 nathanw #else 128 1.1.2.2 nathanw #define ARM_MMU_GENERIC 0 129 1.1.2.2 nathanw #endif 130 1.1.2.2 nathanw 131 1.1.2.2 nathanw #if !defined(_KERNEL_OPT) || \ 132 1.1.2.3 nathanw (defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ 133 1.1.2.3 nathanw defined(CPU_XSCALE_PXA2X0)) 134 1.1.2.2 nathanw #define ARM_MMU_XSCALE 1 135 1.1.2.2 nathanw #else 136 1.1.2.2 nathanw #define ARM_MMU_XSCALE 0 137 1.1.2.2 nathanw #endif 138 1.1.2.2 nathanw 139 1.1.2.2 nathanw #define ARM_NMMUS (ARM_MMU_MEMC + ARM_MMU_GENERIC + \ 140 1.1.2.2 nathanw ARM_MMU_XSCALE) 141 1.1.2.2 nathanw #if ARM_NMMUS == 0 142 1.1.2.2 nathanw #error ARM_NMMUS is 0 143 1.1.2.2 nathanw #endif 144 1.1.2.2 nathanw 145 1.1.2.5 nathanw /* 146 1.1.2.5 nathanw * Step 4: Define features that may be present on a subset of CPUs 147 1.1.2.5 nathanw * 148 1.1.2.5 nathanw * ARM_XSCALE_PMU Performance Monitoring Unit on 80200 and 80321 149 1.1.2.5 nathanw */ 150 1.1.2.5 nathanw 151 1.1.2.5 nathanw #if !defined(_KERNEL_OPT) || \ 152 1.1.2.5 nathanw (defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321)) 153 1.1.2.5 nathanw #define ARM_XSCALE_PMU 1 154 1.1.2.5 nathanw #else 155 1.1.2.5 nathanw #define ARM_XSCALE_PMU 0 156 1.1.2.5 nathanw #endif 157 1.1.2.5 nathanw 158 1.1.2.2 nathanw #endif /* _ARM_CPUCONF_H_ */ 159
Indexes created Mon Oct 20 01:09:56 GMT 2025