cpuconf.h revision 1.6 1 1.6 thorpej /* $NetBSD: cpuconf.h,v 1.6 2003/04/22 00:24:49 thorpej Exp $ */
2 1.1 thorpej
3 1.1 thorpej /*
4 1.5 thorpej * Copyright (c) 2002 Wasabi Systems, Inc.
5 1.1 thorpej * All rights reserved.
6 1.1 thorpej *
7 1.1 thorpej * Written by Jason R. Thorpe for Wasabi Systems, Inc.
8 1.1 thorpej *
9 1.1 thorpej * Redistribution and use in source and binary forms, with or without
10 1.1 thorpej * modification, are permitted provided that the following conditions
11 1.1 thorpej * are met:
12 1.1 thorpej * 1. Redistributions of source code must retain the above copyright
13 1.1 thorpej * notice, this list of conditions and the following disclaimer.
14 1.1 thorpej * 2. Redistributions in binary form must reproduce the above copyright
15 1.1 thorpej * notice, this list of conditions and the following disclaimer in the
16 1.1 thorpej * documentation and/or other materials provided with the distribution.
17 1.1 thorpej * 3. All advertising materials mentioning features or use of this software
18 1.1 thorpej * must display the following acknowledgement:
19 1.1 thorpej * This product includes software developed for the NetBSD Project by
20 1.1 thorpej * Wasabi Systems, Inc.
21 1.1 thorpej * 4. The name of Wasabi Systems, Inc. may not be used to endorse
22 1.1 thorpej * or promote products derived from this software without specific prior
23 1.1 thorpej * written permission.
24 1.1 thorpej *
25 1.1 thorpej * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
26 1.1 thorpej * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27 1.1 thorpej * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 1.1 thorpej * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
29 1.1 thorpej * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 1.1 thorpej * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 1.1 thorpej * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 1.1 thorpej * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 1.1 thorpej * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 1.1 thorpej * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 1.1 thorpej * POSSIBILITY OF SUCH DAMAGE.
36 1.1 thorpej */
37 1.1 thorpej
38 1.1 thorpej #ifndef _ARM_CPUCONF_H_
39 1.1 thorpej #define _ARM_CPUCONF_H_
40 1.1 thorpej
41 1.1 thorpej #if defined(_KERNEL_OPT)
42 1.1 thorpej #include "opt_cputypes.h"
43 1.1 thorpej #endif /* _KERNEL_OPT */
44 1.1 thorpej
45 1.1 thorpej /*
46 1.6 thorpej * IF YOU CHANGE THIS FILE, MAKE SURE TO UPDATE THE DEFINITION OF
47 1.6 thorpej * "PMAP_NEEDS_PTE_SYNC" IN <arm/arm32/pmap.h> FOR THE CPU TYPE
48 1.6 thorpej * YOU ARE ADDING SUPPORT FOR.
49 1.6 thorpej */
50 1.6 thorpej
51 1.6 thorpej /*
52 1.1 thorpej * Step 1: Count the number of CPU types configured into the kernel.
53 1.1 thorpej */
54 1.1 thorpej #if defined(_KERNEL_OPT)
55 1.1 thorpej #define CPU_NTYPES (defined(CPU_ARM2) + defined(CPU_ARM250) + \
56 1.1 thorpej defined(CPU_ARM3) + \
57 1.1 thorpej defined(CPU_ARM6) + defined(CPU_ARM7) + \
58 1.1 thorpej defined(CPU_ARM7TDMI) + \
59 1.1 thorpej defined(CPU_ARM8) + defined(CPU_ARM9) + \
60 1.1 thorpej defined(CPU_SA110) + defined(CPU_SA1100) + \
61 1.1 thorpej defined(CPU_SA1110) + \
62 1.3 ichiro defined(CPU_IXP12X0) + \
63 1.1 thorpej defined(CPU_XSCALE_80200) + \
64 1.2 thorpej defined(CPU_XSCALE_80321) + \
65 1.2 thorpej defined(CPU_XSCALE_PXA2X0))
66 1.1 thorpej #else
67 1.1 thorpej #define CPU_NTYPES 2
68 1.1 thorpej #endif /* _KERNEL_OPT */
69 1.1 thorpej
70 1.1 thorpej /*
71 1.1 thorpej * Step 2: Determine which ARM architecture versions are configured.
72 1.1 thorpej */
73 1.1 thorpej #if !defined(_KERNEL_OPT) || \
74 1.1 thorpej (defined(CPU_ARM2) || defined(CPU_ARM250) || defined(CPU_ARM3))
75 1.1 thorpej #define ARM_ARCH_2 1
76 1.1 thorpej #else
77 1.1 thorpej #define ARM_ARCH_2 0
78 1.1 thorpej #endif
79 1.1 thorpej
80 1.1 thorpej #if !defined(_KERNEL_OPT) || \
81 1.1 thorpej (defined(CPU_ARM6) || defined(CPU_ARM7))
82 1.1 thorpej #define ARM_ARCH_3 1
83 1.1 thorpej #else
84 1.1 thorpej #define ARM_ARCH_3 0
85 1.1 thorpej #endif
86 1.1 thorpej
87 1.1 thorpej #if !defined(_KERNEL_OPT) || \
88 1.1 thorpej (defined(CPU_ARM7TDMI) || defined(CPU_ARM8) || defined(CPU_ARM9) || \
89 1.3 ichiro defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) || \
90 1.3 ichiro defined(CPU_IXP12X0))
91 1.1 thorpej #define ARM_ARCH_4 1
92 1.1 thorpej #else
93 1.1 thorpej #define ARM_ARCH_4 0
94 1.1 thorpej #endif
95 1.1 thorpej
96 1.1 thorpej #if !defined(_KERNEL_OPT) || \
97 1.2 thorpej (defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
98 1.2 thorpej defined(CPU_XSCALE_PXA2X0))
99 1.1 thorpej #define ARM_ARCH_5 1
100 1.1 thorpej #else
101 1.1 thorpej #define ARM_ARCH_5 0
102 1.1 thorpej #endif
103 1.1 thorpej
104 1.1 thorpej #define ARM_NARCH (ARM_ARCH_2 + ARM_ARCH_3 + ARM_ARCH_4 + ARM_ARCH_5)
105 1.1 thorpej #if ARM_NARCH == 0
106 1.1 thorpej #error ARM_NARCH is 0
107 1.1 thorpej #endif
108 1.1 thorpej
109 1.1 thorpej /*
110 1.1 thorpej * Step 3: Define which MMU classes are configured:
111 1.1 thorpej *
112 1.1 thorpej * ARM_MMU_MEMC Prehistoric, external memory controller
113 1.1 thorpej * and MMU for ARMv2 CPUs.
114 1.1 thorpej *
115 1.1 thorpej * ARM_MMU_GENERIC Generic ARM MMU, compatible with ARM6.
116 1.1 thorpej *
117 1.6 thorpej * ARM_MMU_SA1 StrongARM SA-1 MMU. Compatible with generic
118 1.6 thorpej * ARM MMU, but has no write-through cache mode.
119 1.6 thorpej *
120 1.1 thorpej * ARM_MMU_XSCALE XScale MMU. Compatible with generic ARM
121 1.1 thorpej * MMU, but also has several extensions which
122 1.1 thorpej * require different PTE layout to use.
123 1.1 thorpej */
124 1.1 thorpej #if !defined(_KERNEL_OPT) || \
125 1.1 thorpej (defined(CPU_ARM2) || defined(CPU_ARM250) || defined(CPU_ARM3))
126 1.1 thorpej #define ARM_MMU_MEMC 1
127 1.1 thorpej #else
128 1.1 thorpej #define ARM_MMU_MEMC 0
129 1.1 thorpej #endif
130 1.1 thorpej
131 1.1 thorpej #if !defined(_KERNEL_OPT) || \
132 1.1 thorpej (defined(CPU_ARM6) || defined(CPU_ARM7) || defined(CPU_ARM7TDMI) || \
133 1.6 thorpej defined(CPU_ARM8) || defined(CPU_ARM9))
134 1.1 thorpej #define ARM_MMU_GENERIC 1
135 1.1 thorpej #else
136 1.1 thorpej #define ARM_MMU_GENERIC 0
137 1.1 thorpej #endif
138 1.1 thorpej
139 1.1 thorpej #if !defined(_KERNEL_OPT) || \
140 1.6 thorpej (defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) ||\
141 1.6 thorpej defined(CPU_IXP12X0))
142 1.6 thorpej #define ARM_MMU_SA1 1
143 1.6 thorpej #else
144 1.6 thorpej #define ARM_MMU_SA1 0
145 1.6 thorpej #endif
146 1.6 thorpej
147 1.6 thorpej #if !defined(_KERNEL_OPT) || \
148 1.2 thorpej (defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
149 1.2 thorpej defined(CPU_XSCALE_PXA2X0))
150 1.1 thorpej #define ARM_MMU_XSCALE 1
151 1.1 thorpej #else
152 1.1 thorpej #define ARM_MMU_XSCALE 0
153 1.1 thorpej #endif
154 1.1 thorpej
155 1.1 thorpej #define ARM_NMMUS (ARM_MMU_MEMC + ARM_MMU_GENERIC + \
156 1.6 thorpej ARM_MMU_SA1 + ARM_MMU_XSCALE)
157 1.1 thorpej #if ARM_NMMUS == 0
158 1.1 thorpej #error ARM_NMMUS is 0
159 1.4 briggs #endif
160 1.4 briggs
161 1.4 briggs /*
162 1.4 briggs * Step 4: Define features that may be present on a subset of CPUs
163 1.4 briggs *
164 1.4 briggs * ARM_XSCALE_PMU Performance Monitoring Unit on 80200 and 80321
165 1.4 briggs */
166 1.4 briggs
167 1.4 briggs #if !defined(_KERNEL_OPT) || \
168 1.4 briggs (defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321))
169 1.4 briggs #define ARM_XSCALE_PMU 1
170 1.4 briggs #else
171 1.4 briggs #define ARM_XSCALE_PMU 0
172 1.1 thorpej #endif
173 1.1 thorpej
174 1.1 thorpej #endif /* _ARM_CPUCONF_H_ */
175