cpuconf.h revision 1.12.24.1.4.1
1 /* $NetBSD: cpuconf.h,v 1.12.24.1.4.1 2007/11/10 02:56:41 matt Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Portions Copyright (c) 2007 Danger Inc 38 */ 39 40 #ifndef _ARM_CPUCONF_H_ 41 #define _ARM_CPUCONF_H_ 42 43 #if defined(_KERNEL_OPT) 44 #include "opt_cputypes.h" 45 #endif /* _KERNEL_OPT */ 46 47 #if defined(CPU_XSCALE_PXA250) || defined(CPU_XSCALE_PXA270) 48 #define __CPU_XSCALE_PXA2XX 49 #endif 50 51 #ifdef CPU_XSCALE_PXA2X0 52 #warning option CPU_XSCALE_PXA2X0 is obsolete. Use CPU_XSCALE_PXA250 and/or CPU_XSCALE_PXA270. 53 #endif 54 55 /* 56 * IF YOU CHANGE THIS FILE, MAKE SURE TO UPDATE THE DEFINITION OF 57 * "PMAP_NEEDS_PTE_SYNC" IN <arm/arm32/pmap.h> FOR THE CPU TYPE 58 * YOU ARE ADDING SUPPORT FOR. 59 */ 60 61 /* 62 * Step 1: Count the number of CPU types configured into the kernel. 63 */ 64 #if defined(_KERNEL_OPT) 65 #define CPU_NTYPES (defined(CPU_ARM2) + defined(CPU_ARM250) + \ 66 defined(CPU_ARM3) + \ 67 defined(CPU_ARM6) + defined(CPU_ARM7) + \ 68 defined(CPU_ARM7TDMI) + \ 69 defined(CPU_ARM8) + defined(CPU_ARM9) + \ 70 defined(CPU_ARM9E) + \ 71 defined(CPU_ARM10) + \ 72 defined(CPU_ARM11) + \ 73 defined(CPU_SA110) + defined(CPU_SA1100) + \ 74 defined(CPU_SA1110) + \ 75 defined(CPU_IXP12X0) + \ 76 defined(CPU_XSCALE_80200) + \ 77 defined(CPU_XSCALE_80321) + \ 78 defined(__CPU_XSCALE_PXA2XX) + \ 79 defined(CPU_XSCALE_IXP425)) \ 80 defined(CPU_ARM1136)) 81 #else 82 #define CPU_NTYPES 2 83 #endif /* _KERNEL_OPT */ 84 85 /* 86 * Step 2: Determine which ARM architecture versions are configured. 87 */ 88 #if !defined(_KERNEL_OPT) || \ 89 (defined(CPU_ARM2) || defined(CPU_ARM250) || defined(CPU_ARM3)) 90 #define ARM_ARCH_2 1 91 #else 92 #define ARM_ARCH_2 0 93 #endif 94 95 #if !defined(_KERNEL_OPT) || \ 96 (defined(CPU_ARM6) || defined(CPU_ARM7)) 97 #define ARM_ARCH_3 1 98 #else 99 #define ARM_ARCH_3 0 100 #endif 101 102 #if !defined(_KERNEL_OPT) || \ 103 (defined(CPU_ARM7TDMI) || defined(CPU_ARM8) || defined(CPU_ARM9) || \ 104 defined(CPU_SA110) || defined(CPU_SA1100) || \ 105 defined(CPU_SA1110) || defined(CPU_IXP12X0) || defined(CPU_XSCALE_IXP425)) 106 #define ARM_ARCH_4 1 107 #else 108 #define ARM_ARCH_4 0 109 #endif 110 111 #if !defined(_KERNEL_OPT) || \ 112 (defined(CPU_ARM9E) || defined(CPU_ARM10) || \ 113 defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ 114 defined(__CPU_XSCALE_PXA2XX)) 115 #define ARM_ARCH_5 1 116 #else 117 #define ARM_ARCH_5 0 118 #endif 119 120 #if defined(CPU_ARM11) || defined(CPU_ARM1136) 121 #define ARM_ARCH_6 1 122 #else 123 #define ARM_ARCH_6 0 124 #endif 125 126 #define ARM_NARCH (ARM_ARCH_2 + ARM_ARCH_3 + ARM_ARCH_4 + \ 127 ARM_ARCH_5 + ARM_ARCH_6) 128 #if ARM_NARCH == 0 129 #error ARM_NARCH is 0 130 #endif 131 132 #if ARM_ARCH_5 || ARM_ARCH_6 133 /* 134 * We could support Thumb code on v4T, but the lack of clean interworking 135 * makes that hard. 136 */ 137 #define THUMB_CODE 138 #endif 139 140 /* 141 * Step 3: Define which MMU classes are configured: 142 * 143 * ARM_MMU_MEMC Prehistoric, external memory controller 144 * and MMU for ARMv2 CPUs. 145 * 146 * ARM_MMU_GENERIC Generic ARM MMU, compatible with ARM6. 147 * 148 * ARM_MMU_SA1 StrongARM SA-1 MMU. Compatible with generic 149 * ARM MMU, but has no write-through cache mode. 150 * 151 * ARM_MMU_XSCALE XScale MMU. Compatible with generic ARM 152 * MMU, but also has several extensions which 153 * require different PTE layout to use. 154 * 155 * ARM_MMU_V6 ARM v6 MMU. Compatible with generic ARM 156 * MMU, but also has several extensions which 157 * require different PTE layouts to use. 158 */ 159 #if !defined(_KERNEL_OPT) || \ 160 (defined(CPU_ARM2) || defined(CPU_ARM250) || defined(CPU_ARM3)) 161 #define ARM_MMU_MEMC 1 162 #else 163 #define ARM_MMU_MEMC 0 164 #endif 165 166 #if !defined(_KERNEL_OPT) || \ 167 (defined(CPU_ARM6) || defined(CPU_ARM7) || defined(CPU_ARM7TDMI) || \ 168 defined(CPU_ARM8) || defined(CPU_ARM9) || defined(CPU_ARM9E) || \ 169 defined(CPU_ARM10)) 170 #define ARM_MMU_GENERIC 1 171 #else 172 #define ARM_MMU_GENERIC 0 173 #endif 174 175 #if !defined(_KERNEL_OPT) || \ 176 (defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) ||\ 177 defined(CPU_IXP12X0)) 178 #define ARM_MMU_SA1 1 179 #else 180 #define ARM_MMU_SA1 0 181 #endif 182 183 #if !defined(_KERNEL_OPT) || \ 184 (defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ 185 defined(__CPU_XSCALE_PXA2XX) || defined(CPU_XSCALE_IXP425)) 186 #define ARM_MMU_XSCALE 1 187 #else 188 #define ARM_MMU_XSCALE 0 189 #endif 190 191 #if !defined(_KERNEL_OPT) || \ 192 (defined(CPU_ARM11) || defined(CPU_ARM1136)) 193 #define ARM_MMU_V6 1 194 #else 195 #define ARM_MMU_V6 0 196 #endif 197 198 #define ARM_NMMUS (ARM_MMU_MEMC + ARM_MMU_GENERIC + \ 199 ARM_MMU_SA1 + ARM_MMU_XSCALE + ARM_MMU_V6) 200 #if ARM_NMMUS == 0 201 #error ARM_NMMUS is 0 202 #endif 203 204 /* 205 * Step 4: Define features that may be present on a subset of CPUs 206 * 207 * ARM_XSCALE_PMU Performance Monitoring Unit on 80200 and 80321 208 */ 209 210 #if !defined(_KERNEL_OPT) || \ 211 (defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321)) 212 #define ARM_XSCALE_PMU 1 213 #else 214 #define ARM_XSCALE_PMU 0 215 #endif 216 217 #endif /* _ARM_CPUCONF_H_ */ 218
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