cpuconf.h revision 1.13
1 /* $NetBSD: cpuconf.h,v 1.13 2007/01/06 00:50:54 christos Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #ifndef _ARM_CPUCONF_H_ 39 #define _ARM_CPUCONF_H_ 40 41 #if defined(_KERNEL_OPT) 42 #include "opt_cputypes.h" 43 #endif /* _KERNEL_OPT */ 44 45 #if defined(CPU_XSCALE_PXA250) || defined(CPU_XSCALE_PXA270) 46 #define __CPU_XSCALE_PXA2XX 47 #endif 48 49 #ifdef CPU_XSCALE_PXA2X0 50 #warning option CPU_XSCALE_PXA2X0 is obsolete. Use CPU_XSCALE_PXA250 and/or CPU_XSCALE_PXA270. 51 #endif 52 53 /* 54 * IF YOU CHANGE THIS FILE, MAKE SURE TO UPDATE THE DEFINITION OF 55 * "PMAP_NEEDS_PTE_SYNC" IN <arm/arm32/pmap.h> FOR THE CPU TYPE 56 * YOU ARE ADDING SUPPORT FOR. 57 */ 58 59 /* 60 * Step 1: Count the number of CPU types configured into the kernel. 61 */ 62 #if defined(_KERNEL_OPT) 63 #define CPU_NTYPES (defined(CPU_ARM2) + defined(CPU_ARM250) + \ 64 defined(CPU_ARM3) + \ 65 defined(CPU_ARM6) + defined(CPU_ARM7) + \ 66 defined(CPU_ARM7TDMI) + \ 67 defined(CPU_ARM8) + defined(CPU_ARM9) + \ 68 defined(CPU_ARM9E) + \ 69 defined(CPU_ARM10) + \ 70 defined(CPU_ARM11) + \ 71 defined(CPU_SA110) + defined(CPU_SA1100) + \ 72 defined(CPU_SA1110) + \ 73 defined(CPU_IXP12X0) + \ 74 defined(CPU_XSCALE_80200) + \ 75 defined(CPU_XSCALE_80321) + \ 76 defined(__CPU_XSCALE_PXA2XX) + \ 77 defined(CPU_XSCALE_IXP425)) 78 #else 79 #define CPU_NTYPES 2 80 #endif /* _KERNEL_OPT */ 81 82 /* 83 * Step 2: Determine which ARM architecture versions are configured. 84 */ 85 #if !defined(_KERNEL_OPT) || \ 86 (defined(CPU_ARM2) || defined(CPU_ARM250) || defined(CPU_ARM3)) 87 #define ARM_ARCH_2 1 88 #else 89 #define ARM_ARCH_2 0 90 #endif 91 92 #if !defined(_KERNEL_OPT) || \ 93 (defined(CPU_ARM6) || defined(CPU_ARM7)) 94 #define ARM_ARCH_3 1 95 #else 96 #define ARM_ARCH_3 0 97 #endif 98 99 #if !defined(_KERNEL_OPT) || \ 100 (defined(CPU_ARM7TDMI) || defined(CPU_ARM8) || defined(CPU_ARM9) || \ 101 defined(CPU_SA110) || defined(CPU_SA1100) || \ 102 defined(CPU_SA1110) || defined(CPU_IXP12X0) || defined(CPU_XSCALE_IXP425)) 103 #define ARM_ARCH_4 1 104 #else 105 #define ARM_ARCH_4 0 106 #endif 107 108 #if !defined(_KERNEL_OPT) || \ 109 (defined(CPU_ARM9E) || defined(CPU_ARM10) || \ 110 defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ 111 defined(__CPU_XSCALE_PXA2XX)) 112 #define ARM_ARCH_5 1 113 #else 114 #define ARM_ARCH_5 0 115 #endif 116 117 #if defined(CPU_ARM11) 118 #define ARM_ARCH_6 1 119 #else 120 #define ARM_ARCH_6 0 121 #endif 122 123 #define ARM_NARCH (ARM_ARCH_2 + ARM_ARCH_3 + ARM_ARCH_4 + \ 124 ARM_ARCH_5 + ARM_ARCH_6) 125 #if ARM_NARCH == 0 126 #error ARM_NARCH is 0 127 #endif 128 129 #if ARM_ARCH_5 || ARM_ARCH_6 130 /* 131 * We could support Thumb code on v4T, but the lack of clean interworking 132 * makes that hard. 133 */ 134 #define THUMB_CODE 135 #endif 136 137 /* 138 * Step 3: Define which MMU classes are configured: 139 * 140 * ARM_MMU_MEMC Prehistoric, external memory controller 141 * and MMU for ARMv2 CPUs. 142 * 143 * ARM_MMU_GENERIC Generic ARM MMU, compatible with ARM6. 144 * 145 * ARM_MMU_SA1 StrongARM SA-1 MMU. Compatible with generic 146 * ARM MMU, but has no write-through cache mode. 147 * 148 * ARM_MMU_XSCALE XScale MMU. Compatible with generic ARM 149 * MMU, but also has several extensions which 150 * require different PTE layout to use. 151 */ 152 #if !defined(_KERNEL_OPT) || \ 153 (defined(CPU_ARM2) || defined(CPU_ARM250) || defined(CPU_ARM3)) 154 #define ARM_MMU_MEMC 1 155 #else 156 #define ARM_MMU_MEMC 0 157 #endif 158 159 #if !defined(_KERNEL_OPT) || \ 160 (defined(CPU_ARM6) || defined(CPU_ARM7) || defined(CPU_ARM7TDMI) || \ 161 defined(CPU_ARM8) || defined(CPU_ARM9) || defined(CPU_ARM9E) || \ 162 defined(CPU_ARM10) || defined(CPU_ARM11)) 163 #define ARM_MMU_GENERIC 1 164 #else 165 #define ARM_MMU_GENERIC 0 166 #endif 167 168 #if !defined(_KERNEL_OPT) || \ 169 (defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) ||\ 170 defined(CPU_IXP12X0)) 171 #define ARM_MMU_SA1 1 172 #else 173 #define ARM_MMU_SA1 0 174 #endif 175 176 #if !defined(_KERNEL_OPT) || \ 177 (defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ 178 defined(__CPU_XSCALE_PXA2XX) || defined(CPU_XSCALE_IXP425)) 179 #define ARM_MMU_XSCALE 1 180 #else 181 #define ARM_MMU_XSCALE 0 182 #endif 183 184 #define ARM_NMMUS (ARM_MMU_MEMC + ARM_MMU_GENERIC + \ 185 ARM_MMU_SA1 + ARM_MMU_XSCALE) 186 #if ARM_NMMUS == 0 187 #error ARM_NMMUS is 0 188 #endif 189 190 /* 191 * Step 4: Define features that may be present on a subset of CPUs 192 * 193 * ARM_XSCALE_PMU Performance Monitoring Unit on 80200 and 80321 194 */ 195 196 #if !defined(_KERNEL_OPT) || \ 197 (defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321)) 198 #define ARM_XSCALE_PMU 1 199 #else 200 #define ARM_XSCALE_PMU 0 201 #endif 202 203 #endif /* _ARM_CPUCONF_H_ */ 204
Indexes created Tue Sep 23 23:09:58 GMT 2025